EE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting

Transcription

1 EE47 Lecture 6 This lecture is taped on Wed. Nov. 8 th due to conflict of regular class hours with a meeting Any questions regarding this lecture could be discussed during regular office hours or in class at the next lecture Please hand in your homework #8 solution to Yida Duan, otherwise bring it to H.K. s office hour Regular office hours held today, Nov. 9 th., :30 to 563 Cory Hall EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 1 EE47 Lecture 6 Oversampled ADCs 1 st order ΣΔ modulator (continued) In-band quantization noise analysis & dynamic range Issue: DC input results in periodic tones limit cycle oscillations nd order ΣΔ modulator Dynamic range Practical implementation Effect of various building block nonidealities on the ΣΔ performance Example EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page

2 Summary of Last Lecture Oversampled ADCs: Reduction of baseband quantization noise power by combining oversampling with clever use of feedback around the quantizer Allows trading speed for resolution No stringent requirements imposed on analog building blocks (more today) Takes advantage of low cost, low power digital filtering available in fine-line CMOS technology EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 3 1 st Order Sigma- Delta Modulators Analog 1-Bit ΣΔ modulators convert a continuous time analog input v IN into a 1-Bit digital sequence D OUT f s V IN + _ H(z) D OUT DAC Loop filter 1b Quantizer (comparator) EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 4

3 1 st Order ΣΔ Modulator 1 st order modulator, simplest loop filter an integrator V IN + _ H(z) = z -1 1 z -1 D OUT DAC Note: Non-linear system with memory difficult to analyze EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 5 1 st Order ΣΔ Modulator STF and NTF Integrator Quantization Error e(kt) x(kt) Σ 1 1 z H( z) = 1 z Σ Quantizer Model y(kt) Signal transfer function: Y( z) H( z) 1 STF = = = z X( z) 1 + H( z) Delay Noise transfer function: Y ( z) 1 NTF = = = 1 z E( z) 1+ H ( z) 1 Differentiator EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 6

4 Noise Transfer Function Yz () jωt NTF = = = z set z = e Ez () 1 + Hz () jωt NTF( jω) = (1 e )=e jωt/ = e jsin T/ jωt/ / ( ω ) jωt/ ( ω ) jπ ( ω ) = e e sin T/ j( ωt π) / = sin ( ωt/) e where T= 1/ fs Thus: NTF( f )=sin T / =sin π f / f e jωt/ jωt/ e ( s ) N ( f) = NTF( f) N ( f) y e EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 7 First Order ΣΔ Modulator Noise Transfer Characteristics Noise Shaping Function Low-pass Digital Filter N ( f) = NTF( f) N ( f) y ( π ) = 4sin f / f N ( f) First-Order Noise Shaping s e e f B f N f s / frequency Key Point: Most of quantization noise pushed out of frequency band of interest EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 8

5 Quantizer Error For quantizers with many bits Δ ( kt) = 1 Let s use the same expression for the 1-Bit case Use simulation to verify validity e Experience: Often sufficiently accurate to be useful, with enough exceptions to be careful EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 9 First Order ΣΔ Modulator Simulated Noise Transfer Characteristic Amplitude [ dbwn ] Signal Simulated output spectrum Computed NTF ( π ) N ( f) = 4 sin f / f y s Confirms assumption of quantization noise being white at insertion point Linearized model seems to be accurate Frequency [f /f s ] EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 10

6 First Order ΣΔ Modulator In-Band Quantization Noise 1 ( ) = 1 z ( ) ( π ) NTF z s B Y = Q B NTF f = 4 sin f / f for M >> 1 ( ) ( ) S S f NTF z df z= e π jft fs M fs M 1 Δ f 1 s ( sinπ ft) df S Q π 1 Δ 3 3 M 1 Total in-band quantization noise EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 11 1 st Order ΣΔ Dynamic Range full-scale signal power S X DR = 10log 10log inband noise power = SQ 1 Δ SX = sinusoidal input, STF = 1 π 1 Δ SQ = 3 3 M 1 SX 9 3 = M SQ π DR = 10log M = 10log + 30log M π π M DR db 3 4 db db DR = 3.4dB + 30log M X increase in M 9dB (1.5-Bit) increase in dynamic range EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 1

7 Oversampling and Noise Shaping ΣΔ modulators have interesting characteristics Unity gain for input signal V IN Significant attenuation of in-band quantization noise injected at quantizer input Performance significantly better than 1-Bit noise performance possible for frequencies << f s Increase in oversampling (M = f s /f N >> 1) improves SQNR considerably 1 st order ΣΔ: DR increases 9dB for each doubling of M To first order, SQNR independent of circuit complexity and accuracy Analysis assumes that the quantizer noise is white Not entirely true in practice, especially for low-order modulators Practical modulators suffer from other noise sources also (e.g. thermal noise) EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 13 1 st Order ΣΔ Modulator Response to DC Input Matlab & Simulink model from Lecture 5 used Input DC at 1/11 full-scale level 1 X Q 3 Y DC Input=1/11 FS z z Integrator Comparator EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 14

8 1 st Order ΣΔ Response to DC Input Amplitude [ dbwn ] DC Component Frequency [ f /f s ] DC input A = 1/11 Output spectrum shows DC component plus distinct tones!! Tones frequency shaped the same as quantization noise More prominent at higher frequencies Seems like periodic quantization noise EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 15 Limit Cycle Oscillation Output First order sigma-delta, DC input Time [t/t] DC input 1/11 Periodic sequence: Average =1/11 EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 16

9 1 st Order ΣΔ Limit Cycle Oscillation Amplitude In-band spurious tone with f ~ DC input level First-Order Noise Shaping f B f N Frequency f s / Problem: quantization noise becomes periodic in response to low level DC inputs & could fall within passband of interest! Solution: Use dithering (inject noise-like signal at the input ): randomizes quantization noise - If circuit thermal noise is large enough acts as dither Second order loop EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 17 1 st Order ΣΔ Modulator Linearized Model Analysis ( ) 1 1 Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 18

10 nd Order ΣΔ Modulator Two integrators in series Single quantizer (typically 1-bit) Feedback from output to both integrators Tones less prominent compared to 1st order EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 19 nd Order ΣΔ Modulator Linearized Model Analysis ( ) Recursive drivation: Y = X + E E + E n n 1 n n 1 n ( ) Using the delay operator z : Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 0

11 NTF z NTF 4 1 ( ) = ( 1 z ) ( f ) = ( π ) nd Order ΣΔ Modulator In-Band Quantization Noise = sin f / f for M >> 1 B Q = Q( ) ( ) z= e B fs M fs M 1 Δ f 1 s 4 π 1 Δ 5 5 M 1 s S S f NTF z df 4 ( sinπ ft) π jft 4 df EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 1 Quantization Noise nd Order ΣΔ Modulator vs 1 st Order Modulator S Q π 1 Δ 3 3 M 1 Noise Shaping Function Ideal Low-pass Digital Filter nd -Order Noise Shaping 1 st Order Noise Shaping S Q 4 π 1 Δ 5 5 M 1 f B Frequency f s / EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page

12 nd Order ΣΔ Modulator Dynamic Range full-scale signal power S X DR = 10log 10log inband noise power = SQ 1 Δ SX = sinusoidal input, STF = 1 4 π 1 Δ SQ = 5 5 M 1 SX 15 5 = M 4 SQ π DR = 10log M = 10log + 50log M 4 4 π π DR = 11.1dB+ 50log M X increase in M 15dB (.5-bit) increase in DR EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 3 nd Order vs 1 st Order ΣΔ Modulator Dynamic Range M 16 nd Order D.R. 49 db (7.8bit) 1 st Order D.R. 33dB (5.bit) Resolution ( nd order - 1 st order).6 bit 3 64 db (10.3bit) 4dB (6.7bit) 3.6 bit db (17.9bit) 68.8dB (11.1bit) 6.8 bit db (.8bit) 87dB (14.bit) 8.6 bit Note: For higher oversampling ratios resolution of nd order modulator significantly higher compared to 1 st order EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 4

13 nd Order ΣΔ Modulator Example Digital audio application Signal bandwidth 0kHz Desired resolution 16-bit 16 bit 98 db Dynamic Range DRnd order ΣΔ = -11.1dB + 50log M M = 153 min M 56= 8 to reasons: 1. Allow some margin so that thermal noise dominate & provides dithering. Choice of M power of ease of digital filter implementation Sampling rate (x0khz + 5kHz)M = 1MHz (quite reasonable!) EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 5 Limit Cycle Tones in 1 st Order & nd Order ΣΔ Modulator Higher oversampling ratio lower tones nd order tones much lower compared to 1 st 6dB 1 st Order ΣΔ Modulator Xincrease in M decreases the tones by 6dB for 1 st order loop and 1dB for nd order loop 1dB Inband Quantization noise nd Order ΣΔ Modulator Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 6, pp , April R. Gray, Spectral analysis of quantization noise in a single-loop sigma delta modulator with dc input, IEEE Trans. Commun., vol. 37, pp , June EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 6

14 ΣΔ Implementation Practical Design Considerations Internal node scaling & clipping Effect of finite opamp gain & linearity KT/C noise Opamp noise Effect of comparator nonidealities Power dissipation considerations EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 7 Switched-Capacitor Implementation nd Order ΣΔ Nodes Scaled for Maximum Dynamic Range Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full-scale (Δ) Note: Non-idealities associated with nd integrator and quantizer when referred to the ΣΔ input is attenuated by 1 st integrator high gain The only building block requiring low-noise and high accuracy is the 1 st integrator Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp , Dec EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 8

15 nd Order ΣΔ Modulator Example: Switched-Capacitor Implementation V IN Dout Fully differential front-end Two bottom-plate integrators 1-bit DAC is made of switches and Vrefs EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 9 Switched-Capacitor Implementation nd Order ΣΔ Phase 1 V IN Dout During phase 1: 1 st integrator samples Vin on 1 st stage C1 nd integrator samples output of 1 st integrator Comparator senses polarity of nd intg. output result saved in output latch S3 opens prior to S1 minimize effect of charge injection EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 30

16 Switched-Capacitor Implementation nd Order ΣΔ Phase V IN Dout Input sampled during φ 1 transferred to C integration Note: S connects integrator inputs to + or Vref, polarity depends on whether Dout is 0 or 1 EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 31 nd Order ΣΔ Modulator Switched-Capacitor Implementation The ½ loss in front of each integrator implemented by choice of: C =C 1 f 0 intg =f s /(4π) EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 3

17 Design Phase Simulations Design of oversampled ADCs requires simulation of extremely long data traces SPICE type simulators: Normally used to test for gross circuit errors only Too slow for detailed performance verification Typically, behavioral modeling is used in MATLAB-like environments Circuit non-idealities either computed or found by using SPICE at subcircuit level Non-idealities introduced in the behavioral model one-by-one first to fully understand the effect of each individually Next step is to add as many of the non-idealities simultaneously as possible to verify whether there are interaction among non-idealities EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 33 nd Order ΣΔ Effect of 1 st Integrator Maximum Signal Handling Capability on SNR 1 st integrator maximum signal handling: 1.4, 1.5,1.6, and 1.7X Δ Effect of 1 st Integrator maximum signal handling capability on converter SNR No SNR loss for max. sig. handling >1.7Δ Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 34

18 nd Order ΣΔ Effect of nd Integrator Maximum Signal Handling Capability on SNR nd integrator maximum signal handling: 0.75,1,1.5, 1.5, and 1.7X Δ Effect of nd Integrator maximum signal handling capability on SNR Νο SNR loss for max. sig. handling >1.7 Δ Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 35 nd Order ΣΔ Effect of Integrator Finite DC Gain V i Integrator φ 1 φ CI H( z) - Cs a V + o H( z) a opamp gain at DC ideal Finit DC Gain ( ) 1 Cs z = 1 CI 1 z a z Cs 1+ a + Cs = CI CI 1+ a 1 z Cs 1+ a + CI H DC = a 1 1 EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 36

19 nd Order ΣΔ Effect of Integrator Finite DC Gain log H ( s) a Ideal Integ. (a=infinite) e Q + _ D OUT ω 0 ω P1 = 0 a Integrator magnitude response Note: Quantization transfer function wrt output has integrator in the feedback path: H ( ω) Dout = 1 eq 1 + H( DC for ideal integ: Dout = 0 DC for real integ: Dout 1 e a Q EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 37 nd Order ΣΔ Effect of Integrator Finite DC Gain Max signal level a f 0 /a Low integrator DC gain Increase in total in-band quantization noise Can be shown: If a > M (oversampling ratio) Insignificant degradation in SNR Normally DC gain designed to be >> M in order to suppress nonlinearities EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 38

20 nd Order ΣΔ Effect of Integrator Finite DC Gain M / a Example: a =M 0.4dB degradation in SNR a =M 1.4dB degradation in SNR Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 39 nd Order ΣΔ Effect of Comparator Non-Idealities on ΣΔ Performance 1-bit A/D Single comparator Speed must be adequate for the operating sampling rate Input referred offset- feedback loop & high DC intg. Gain suppresses the effect ΣΔ performance quite insensitive to comparator offset Input referred comparator noise- same as offset Hysteresis= Minimum overdrive required to change the output EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 40

21 nd Order ΣΔ Comparator Hysteresis Hysteresis= Minimum overdrive required to change the output EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 41 nd Order ΣΔ Comparator Hysteresis Hysteresis/Δ Comparator hysteresis < Δ/5 does not affect SNR E.g. Δ=1V, comparator hysteresis up to 40mV tolerable Key Point: One of the main advantages of ΣΔ ADCS Highly tolerant of comparator and in general building-block non-idealities EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 4

22 nd Order ΣΔ Effect of Integrator Nonlinearities u(kt) Ideal Integrator Delay v(kt) v(kt+ T) = u(kt) + v(kt) With non-linearity added: 3 v(kt + T ) = u(kt ) + α u( kt ) + α 3 u( kt ) v(kt ) + β v( kt ) + β 3 v( kt ) +... Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 43 nd Order ΣΔ Effect of Integrator Nonlinearities (Single-Ended) α = β = 0.01, 0.0, 0.05, 0.1% Simulation for single-ended topology Even order nonlinearities can be significantly attenuated by using differential circuit topologies Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 44

23 nd Order ΣΔ Effect of Integrator Nonlinearities α 3 = β 3 = 6dB =1-Bit 0.05, 0.,1% Simulation for single-ended topology Odd order nonlinearities (3 rd in this case) Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 45 nd Order ΣΔ Effect of Integrator Nonlinearities Odd order nonlinearities (usually 3 rd ) could case significant loss of SNR for high resolution oversampled ADCs Two significant source of non-linearities: Non-linearities associated with opamp used to build integrators Opamp open-loop non-linearities are suppressed by the loopgain since there is feedback around the opamp Class A opamps tend to have lower open loop gain but more linear output versus input transfer characteristic Class A/B opamps typically have higher open loop gain but non-linear transfer function. At times this type is preferred for ΣΔ AFE due to its supperior slew rate compared to class A type Integrator capacitor non-linearites Poly-Sio-Poly capacitors have in the order of 10ppm/V non-linearity Metal-Sio-Metal Cs ~ 1ppm/V EECS 47 Lecture 6: Oversampling Data Converters 007 H. K. Page 46