EE247 Lecture 26. EE247 Lecture 26

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1 EE247 Lecture 26 Administrative EE247 Final exam: Date: Mon. Dec. 18 th Time: 12:30pm-3:30pm Location: 241 Cory Hall Extra office hours: Thurs. Dec. 14 th, 10:30am-12pm Closed book/course notes No calculators/cell phones/pdas/computers Bring two 8x11 paper with your own notes Final exam covers the entire course material unless specified otherwise EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 1 EE247 Lecture 26 Oversampled ADCs (continued) 2 nd order ΣΔ modulator Dynamic range Practical implementation Effect of various building block nonidealities on the ΣΔ performance Higher order ΣΔ modulators Cascaded modulators (multi-stage) Single-loop single-quantizer modulators with multi-order filtering in the forward path EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 2

2 Summary of Last Lecture Oversampled ADCs: Allows trading speed for resolution No stringent requirements imposed on analog building blocks Takes advantage of low cost, low power digital filtering Relaxed transition band requirements for analog anti-aliasing filters Further reduction of baseband quantization noise power by combining oversampling with clever use of feedback By simply increasing oversampling ratio: 2X increase in sampling ratio 0.5-bit increase in resolution Embedding the quantizer in a 1 st order feedback loop 1.5-bit increase is resolution per 2x increase in sampling rate Problem: Limit cycle oscillations at levels exceeding quantization noise! EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 3 Noise Shaping Function 1 st Order ΣΔ Limit Cycle Oscillation Ideal Low-pass Digital Filter In-band spurious tone with f ~ DC input level First-Order Noise Shaping f B f N Frequency f s /2 Problem: quantization noise becomes periodic in response to low level DC inputs & could fall within passband of interest! Solution: Use dithering (inject noise-like signal at the input ): randomizes quantization noise - Circuit thermal noise if large enough acts as dither Second order loop EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 4

3 1 st Order ΣΔ Modulator Linearized Model Analysis ( ) 1 1 Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 5 2 nd Order ΣΔ Modulator Two integrators in series Single quantizer (typically 1-bit) Feedback from output to both integrators Tones less prominent compared to 1st order EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 6

4 2 nd Order ΣΔ Modulator Linearized Model Analysis ( ) Recursive drivation: Y = X + E 2E + E n n 1 n n 1 n 2 ( ) Using the delay operator z : Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 7 NTF z NTF 4 B 2 Y = Q( ) ( ) z= e B f s f s 2 2 M M 2 1 Δ f Δ 5 π 5 M 12 s 2 nd Order ΣΔ Modulator In-Band Quantization Noise S S f NTF z df 1 ( ) = ( 1 z ) 2 ( f ) = ( π ) = 2 sin f / f for M >> 1 s 4 2 ( 2sinπ ft) 2π jft 4 df EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 8

5 Quantization Noise 2 nd Order ΣΔ Modulator vs 1 st Order Modulator S Y 2 2 π 1 Δ M Noise Shaping Function Ideal Low-pass Digital Filter 2 nd -Order Noise Shaping 1 st Order Noise Shaping S Y 4 2 π 1 Δ 5 5 M 12 f B Frequency f s /2 EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 9 2 nd Order ΣΔ Modulator Dynamic Range peak signal power S X DR = 10log 10log peak noise power = SY 2 1 Δ SX = sinusoidal input, STF = π 1 Δ M DR (2 nd ) DR (1 st ) SY = 5 5 M db 33dB S db 42dB X 5 = M db 87dB SY 2π DR = 10log M 10log 50log M 4 4 2π = + 2π DR = 11.1dB +50log M 2X increase in M 15dB (2.5-bit) increase in DR EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 10

6 Digital audio application Signal bandwidth 20kHz Resolution 16-bit 2 nd Order ΣΔ Modulator Example 16 bit 98 db Dynamic Range DR = 11.1dB + 50log M M = 153 min M 256=2 8 to allow some margin so that thermal noise dominants & provides dithering & also for ease of digital filter implementation Sampling rate (2x20kHz + 5kHz)M = 12MHz (quite reasonable!) EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 11 Limit Cycle Tones in 1 st Order & 2 nd Order ΣΔ Modulator Higher oversampling ratio lower tones 2 nd order much lower tones compared to 1 st 6dB 1 st Order ΣΔ Modulator 2Xincrease in M decreases the tones by 6dB for 1 st order loop and 12dB for 2 nd order loop 12dB Quantization noise 2 nd Order ΣΔ Modulator Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April R. Gray, Spectral analysis of quantization noise in a single-loop sigma delta modulator with dc input, IEEE Trans. Commun., vol. 37, pp , June EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 12

7 ΣΔ Implementation Practical Design Considerations Internal node scaling & clipping Effect of finite opamp gain & linearity KT/C noise Opamp noise Effect of comparator nonidealities Power dissipation considerations EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 13 Switched-Capacitor Implementation 2 nd Order ΣΔ Nodes Scaled for Maximum Dynamic Range Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full-scale (Δ) Note: Non-idealities associated with 2 nd integrator and quantizer when referred to the ΣΔ input is attenuated by 1 st integrator high gain The only building block requiring low-noise and accuracy is the 1 st integrator Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 23, no. 6, pp , Dec EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 14

8 2 nd Order ΣΔ Modulator Example: Switched-Capacitor Implementation IN Dout Fully differential front-end Two bottom-plate integrators 1-bit DAC is made of switches and Vrefs EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 15 Switched-Capacitor Implementation 2 nd Order ΣΔ Phase 1 Sample inputs on 1 st stage C 1, sample output of 1 st stage on C 1 of 2 nd stage Comparator compares output of 2 nd integrator result of comparison saved on output latch At the end of phase1, S3 opens prior to S1 opening charge injection just DC offset EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 16

9 Switched-Capacitor Implementation 2 nd Order ΣΔ Phase 2 Enable feedback from output to input of both integrators Integrate Reset comparator At the end of phase 2 S4 opens before S2 EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 17 2 nd Order ΣΔ Modulator Switched-Capacitor Implementation The ½ loss in front of each integrator implemented by choice of: C 2 =2C 1 f 0 intg =f s /(4π) EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 18

10 Design Phase Simulations Design of oversampled ADCs requires simulation of extremely long data traces SPICE type simulators: Normally used to test for gross circuit errors only Too slow and inaccurate for performance verification Typically, behavioral modeling is used in MATLAB-like environments Circuit non-idealities either computed or found by using SPICE at subcircuit level Non-idealities introduced in the behavioral model one-by-one first to fully understand the effect of each individually Next step is to add as many of the non-idealities simultaneously as possible to verify whether there are interaction among non-idealities EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 19 2 nd Order ΣΔ Effect of 1 st Integrator Maximum Signal Handling Capability on SNR 1 st integrator maximum signal handling: 1.4, 1.5,1.6, and 1.7X Δ Effect of 1 st Integrator maximum signal handling capability on converter SNR No SNR loss for max. sig. handling >1.7Δ Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 20

11 2 nd Order ΣΔ Effect of 2 nd Integrator Maximum Signal Handling Capability on SNR 2nd integrator maximum signal handling: 0.75,1,1.25, 1.5, and 1.7X Δ Effect of 2nd Integrator maximum signal handling capability on SNR Νο SNR loss for max. sig. handling >1.7 Δ Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 21 2 nd Order ΣΔ Effect of Integrator Finite DC Gain V i Integrator φ 1 φ 2 CI H( z) - Cs a V + o H( z) a opamp gain at DC ideal Finit DC Gain ( ) 1 Cs z = 1 CI 1 z a z Cs 1+ a + Cs = CI CI 1+ a 1 z Cs 1+ a + CI H DC = a 1 1 EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 22

12 2 nd Order ΣΔ Effect of Integrator Finite DC Gain log H ( s) a Ideal Integ. (a=infinite) Max signal level a ω 0 ω P1 = 0 a Integrator magnitude response f 0 /a Low integrator DC gain Increase in total in-band quantization noise Can be shown: If a > M (oversampling ratio) Insignificant degradation in SNR Normally DC gain designed to be >> M in order to suppress nonlinearities EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 23 2 nd Order ΣΔ Effect of Integrator Finite DC Gain M / a Example: a =2M 0.4dB degradation in SNR a =M 1dB degradation in SNR Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 24

13 2 nd Order ΣΔ Effect of Comparator Non-Idealities on ΣΔ Performance 1-bit A/D Single comparator Speed must be adequate for the operating sampling rate Input referred offset- feedback loop suppresses the effect ΣΔ performance quite insensitive to comparator offset Input referred comparator noise- same as offset Hysteresis= Minimum overdrive required to change the output EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 25 2 nd Order ΣΔ Comparator Hysteresis Hysteresis= Minimum overdrive required to change the output EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 26

14 2 nd Order ΣΔ Comparator Hysteresis Comparator hysteresis < Δ/25 does not affect SNR E.g. Δ=1V, comparator offset/hysteresis up to 40mV tolerable Key Point: One of the main advantages of ΣΔ ADCS Highly tolerant of comparator and in general building-block non-idealities EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 27 2 nd Order ΣΔ Effect of Integrator Nonlinearities u(kt) Ideal Integrator Delay v(kt) v(kt+ T) = u(kt) + v(kt) With non-linearity added: 2 3 v(kt + T ) = u(kt ) + α 2 u( kt ) + α 3 u( kt ) v(kt ) + β 2 v( kt ) + β 3 v( kt ) +... Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 28

15 2 nd Order ΣΔ Effect of Integrator Nonlinearities α 2 = β 2 = 0.01, 0.02, 0.05, 0.1% Simulation for single-ended topology Even order nonlinearities can be significantly attenuated by using differential circuit topologies Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 29 2 nd Order ΣΔ Effect of Integrator Nonlinearities α 3 = β 3 = 6dB =1-Bit 0.05, 0.2,1% Simulation for single-ended topology Odd order nonlinearities (3 rd in this case) Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 30

16 V i φ 1 φ 2 Cs 2 nd Order ΣΔ Effect of KT/C noise CI - + V o 2 2KT vn = Cs 2 kt 1 kt vn / f = 2 = 4 Cs fs /2 Cs fs Total in-band noise: 2 n input referred v 2kT = Cs M kt = 4 f Cs fs 0 For the example of digital audio with 16-bit (96dB) & M=256 (110dB SQNR) Cs=1pF 7μVrms noise If FS=2V p-p-d then thermal -101dB degrades overall SNR by ~10dB Cs=1pF, CI=2pF small capacitor area compared to Nyquist ADC Since thermal noise provides some level of dithering better not choose much larger capacitors! EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 31 2 nd Order ΣΔ Effect of Finite Opamp Bandwidth Vi+ Vi- s φ1 φ 2 C I C - + Vo Unity-gain-freq. Input/Output z-transform = f u =1/τ V o φ 2 settling error T=1/f s time Assumptions: Opamp does not slew Opamp has only one pole exponential settling EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 32

17 2 nd Order ΣΔ Effect of Finite Opamp Bandwidth ΣΔ does not require high opamp bandwidth f u > 2f s adequate Note: Bandwidth requirements significantly more relaxed compared to Nyquist rate ADCs EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 33 2 nd Order ΣΔ Effect of Slew Limited Settling Clock φ 1 φ 2 Vo-ideal Vo-real Slewing Slewing EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 34

18 2 nd Order ΣΔ Effect of Slew Limited Settling Input Signal = -5dB T/τ =2 Assumption: Opamp settling includes a single-pole setting of τ =1/2f s + slewing Low slew rate degrades SNR rapidly- increases quantization noise and causes signal distortion Minimum slew rate of 1.2 (Δ x f s ) required EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 35 Modulator Testing Should make provisions for testing the modulator (AFE) separate from the decimator (digital back-end) Data acquisition board used to collect 1-bit digital output at f s rate Analyze data in a PC environment or dedicated test equipment in manufacturing environments can be used Need to run DFT on the collected data and also make provisions to perform the function of digital decimation filter in software Typically, at this stage, parts of the design phase behavioral modeling effort can be utilized Good testing strategy vital for debugging/improving challenging designs f s Filtered Sinwave AFE Data Acq. PC Matlab EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 36

19 2 nd Order ΣΔ Implementation Example: Digital Audio Application 5V supply, Δ = 4Vp-p-d, M=256 ideal quantization Minimum capacitor values computed based on -104dB noise wrt maximum signal Max. inband KT/C noise = 7μVrms (noise thermal noise dominates provide dithering & reduce limit cycle oscillations) C1=(2kT)/(M v 2 n )=1pF C2=2C1 Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 37 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured Performance Summary (Does Not Include Decimator) Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 38

20 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured SNDR M=256, 0dB=4V p-p-d f sampling : 12.8MHz Signal Frequency: 2.8kHz Optimum -3dB wrt to Δ Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 39 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 40

21 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured & simulated spurious tones performance as a function of DC input signal Sampling rate=12.8mhz, M=256 Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 41 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured & simulated noise tone performance for near zero DC input of Δ Sampling rate=12.8mhz, M=256 Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 42

22 2 nd Order ΣΔ Implementation Example: Digital Audio Applications Measured & simulated worst-case noise DC input of Δ Both indicate maximum 22.5kHz around -100dB level Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 43 2 nd Order ΣΔ Implementation Example: Integrator Opamp Class A/B opamp High slewrate S.C. common-mode feedback Input referred noise (both thermal and 1/f) important for high resolution performance Minimum required DC gain> M=256, usually DC gain designed to be much higher to suppress nonlinearities (particularly, for class A/B amps Minimum required slew rate of 1.2(Δfs) 65V/usec Minimum opamp settling time constant 1/2fs~30nsec Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 44

23 2 nd Order ΣΔ Implementation Example: Comparator Comparator simple design, No preamp, basically a latch w reset Minimum acceptable hysteresis or offset (based on analysis) Δ/25 160mV Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 45 2 nd Order ΣΔ Implementation Example: Subcircuit Performance Our computed Over-Design Factor minimum required DC Gain 48dB x8 (compensates of non-linear open-loop gain) Unity-gain freq =2fs=25MHz x2 Slew rate = 65V/usec x5 Output range 1.7Δ=6.8V! X0.9 Settling time constant= 30nsec x4 Comparator offset 160mV x12 Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp , April EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 46

24 Higher Order ΣΔ Modulator Dynamic Range ( ) L 1 1 Y( z) = z X( z) + 1 z E( z), L ΣΔ order S S S S X Y X Y 2 Δ 2L 2 1 = sinusoidal input, STF = π 1 = M 32 ( L + 1) = M 2L 2π 2L + 1 2L L+ 1 ( L + ) 32 1 DR = 10log M 2L 2π DR 2L ( L + 1) = 10log +( 2L ) 2π 2L Δ logm 2X increase in M (6L+3)dB or (L+0.5)-bit increase in DR EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 47 ΣΔ Modulator Dynamic Range As a Function of Modulator Order L=3 L=2 L=1 Potential stability issues for L >2 EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 48

25 Higher Order ΣΔ Modulators Extending ΣΔ Modulators to higher orders by adding integrators in the forward path (similar to 2 nd order) Issues with stability Two different architectural approaches used to implement ΣΔ modulators of order >2 Single-loop single-quantizer modulators with multiorder filtering in the forward path Cascade of lower order modulators (multi-stage) EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 49 Higher Order ΣΔ Modulators Mult-Order Filter E(z) X(z) Σ H() z Σ Y(z) H( z) 1 Y( z) = X( z) + E( z) 1 + H( z) 1 + H( z) Y( z) 1 NTF = = E( z ) 1 + H( z ) Zeros of NTF (poles of H(z)) can be strategically positioned to suppress baseband noise spectrum Main issue Loop stability for 3 rd and higher orders EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 50

26 Higher Order ΣΔ Modulators Cascaded Modulators Cascade two or more stable ΣΔ stages Quantization error of each stage is quantized by the succeeding stage and subtracted digitally Order of noise shaping equals sum of the orders of the stages Quantization noise cancellation depends on the precision of analog signal paths Quantization noise further randomized less limit cycle oscillation problems Typically, no potential instability EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 51 2-Stage Cascaded ΣΔ Modulators Main ΣΔ quantizes the signal The quantization error is then quantized by the 2 nd quantizer The quantized error is then subtracted from the results in the digital domain EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 52

27 2 nd Order (1-1) Cascaded ΣΔ Modulators 2 nd order noise shaping EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 53 3 rd Order Cascaded ΣΔ Modulators (1) Cascade of ΣΔs Can implement 3 rd order noise shaping with This is also called MASH (multi-stage noise shaping) EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 54

28 3rd Order Cascaded ΣΔ Modulators (2) Cascade of 2-1 ΣΔs Advantages of 2-1 cascade: Low sensitivity to precision of analog paths Low spurious noise tones No potential instability 3rd order noise shaping EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 55 Sensitivity of Cascade of (1-1-1) ΣΔ Modulators to Matching of Analog & Digital Gains Accuracy of < 0.1% 2dB loss in DR EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 56

29 Sensitivity of Cascade of (2-1) ΣΔ Modulators to Matching Error Accuracy of < + 3% 2dB loss in DR Main advantage of 2-1 cascade compared to topology: Low sensitivity to precision of analog paths (over one order of magnitude less sensitive compared to (1-1-1)!) EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page Cascaded ΣΔ Modulators Accuracy of < + 3% 2dB loss in DR Ref: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp , March EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 58

30 2-1 Cascaded ΣΔ Modulators Effect of gain parameters on signal-to-noise ratio EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 59 Comparison of 2 nd order & Cascaded (2-1) ΣΔ Modulator Digital Audio Application, f N =50kHz Reference Architecture Dynamic Range Peak SNDR Oversampling rate Differential input range Power Dissipation Active Area Brandt,JSSC 4/91 2 nd order 98dB (16-bits) 94dB 256 (theoretical SNR=109dB) 4Vppd 5V supply 13.8mW 0.39mm 2 Williams, JSSC 3/94 (2+1) Order 104dB (17-bits) 98dB 128 (theoretical SNR=128dB) 8Vppd 5V supply 47.2mW 5.2mm 2 EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 60

31 2-1 Cascaded ΣΔ Modulators Measured Dynamic Range Versus Oversampling Ratio 21dB/Octave 3dB/Octave Ref: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp , March EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 61 Summary Oversampled ADCs decouple SQNR from circuit complexity and accuracy If a 1-Bit DAC is used, the converter is inherently linear independent of component matching Typically, used for high resolution & low frequency applications e.g. digital audio 2 nd order ΣΔ used extensively due to lower levels of limit cycle related spurious tones ΣΔ modulators of order greater than 2: Single-loop, single-quantizer modulators with multi-order filtering in the forward path Cascaded (multi-stage) modulators EECS 247 Lecture 26: Oversampling Data Converters 2006 H. K. Page 62