EE247 Lecture 14. To avoid having EE247 & EE 142 or EE290C midterms on the same day, EE247 midterm moved from Oct. 20 th to Thurs. Oct.

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1 Administrative issues EE247 Lecture 14 To avoid having EE247 & EE 142 or EE29C midterms on the same day, EE247 midterm moved from Oct. 2 th to Thurs. Oct. 27 th Homework # 4 due on Thurs. Oct. 2 th H.K. s office hours changed from 3-4 to 2:3 to 3:3 EECS 247 Lecture 14: Data Converters 25 H.K. Page 1 EE247 Lecture 14 Data Converters Spectral testing including windowing Practical aspects of converter testing Signal source Clock generator Evaluation board considerations Evaluation set-up Debugging EECS 247 Lecture 14: Data Converters 25 H.K. Page 2

2 ADC Testing (Continued) Need to find "decision levels", i.e. input voltages at all code boundaries One way: Adjust voltage source to find exact code trip points "code boundary servo" More versatile: Histogram testing Apply a signal with known distribution (ramp or sinusoid) and analyze digital code distribution at ADC output Spectral testing- Reveals ADC errors associated with dynamic behavior i.e. ADC performance as a function of frequency Direct Discrete-Fourier-Transform (DFT) based measurements Feasable when input signal can be locked to sampling frequency Resticts input signal frequency DFT measurements including windowing EECS 247 Lecture 14: Data Converters 25 H.K. Page 3 Direct DFT Choice of Number of Cycles & Number of Samples To overcome frequency spectrum leakage problem: Number of Cycles integer N/cycles = f s / f x non-integer Preferable to have N power of 2 (FFT instead of DFT) Signal Amplitude Signal Amplitude N/cycles = fs / fx=6 integer Time N/cycles = fs / fx=5.55 non-intege Time EECS 247 Lecture 14: Data Converters 25 H.K. Page 4

3 Windowing Spectral leakage can be virtually eliminated by windowing time samples prior to the DFT Windows taper smoothly down to zero at the beginning and the end of the observation window Time samples are multiplied by window coefficients on a sample-by-sample basis Windowing sinusoidal waveforms places the window spectrum at the sinewave frequency Convolution in frequency EECS 247 Lecture 14: Data Converters 25 H.K. Page 5 Window Time samples are multiplied by window coefficients on a sample-by-sample basis Multiplication in the time domain corresponds to convolution in the frequency domain Example: Nuttall window Time EECS 247 Lecture 14: Data Converters 25 H.K. Page 6

4 Windowed Data Signal before windowing Signal after windowing Windowing removes the discontinuity at block boundaries Signal Amplitude Windowed Signal Amplitude Time x Time.8 1 x 1-3 EECS 247 Lecture 14: Data Converters 25 H.K. Page 7 Nuttall Window DFT Only first 2 bins shown Response attenuated by -12dB for bins > 5 Lots of windows to choose from (go by name of inventor- Blackman, Harris ) Various window trade-off attenuation versus width (smearing of sinusoids) Normalized Amplitude [db] DFT Bin EECS 247 Lecture 14: Data Converters 25 H.K. Page 8

5 DFT of Windowed Signal Spectra of signal before and after windowing Window gives ~ 1dB attenuation of sidelobes (use longer window for higher attenuation) Signal energy smeared over several (approximately 1) bins Spectrum not Windowed [ dbfs ] Windowed Spectrum [ dbfs ] Before windowing Frequency [ f x / f s ] After windowing Frequency [ f x / f s ] EECS 247 Lecture 14: Data Converters 25 H.K. Page 9 Integer Cycles versus Windowing Integer number of cycles Signal energy for a single sinusoid falls into single DFT bin Requires careful choice of f x Ideal for simulations Measurements need to lock f x to f s (PLL) Windowing No restrictions on f x no need to have the signal locked to f s ideal for measurements Signal energy (and harmonics) distributed over several DFT bins Requires more data points for a fixed accuracy EECS 247 Lecture 14: Data Converters 25 H.K. Page 1

6 Spectral ADC Testing ADC with B bits ±1 full scale input B = 1; delta = 2/(2^B-1); th = -1+delta/2:delta:1-delta/2; x = sin( ); y = adc(x, th) * delta - 1; s = abs(fft(y)/n*2);s = s(1:n/2); f = (:length(s)-1) / N; EECS 247 Lecture 14: Data Converters 25 H.K. Page 11 ADC Output Spectrum Signal amplitude: Bin: N * fx/fs + 1 (Matlab arrays start at 1) A = dbfs Ampliutde [dbfs] N=248 SNR? f/fs EECS 247 Lecture 14: Data Converters 25 H.K. Page 12

7 ADC Simulated Output Spectrum Noise bins: all except signal bin bx = N*fx/fs + 1; As = 2*log1(s(bx)) s(bx) = ; An = 1*log1(sum(s.^2)) SNR = As - An SNR = 62dB (1 bits) Computed SQNR = 6.2xN+1.76dB Note: In a real circuit including thermal/flicker noise the measured total noise is the sum of quantization & noise associated with the circuit EECS 247 Lecture 14: Data Converters 25 H.K. Page 13 Amplitude [dbfs] N=248 f /f s Why is noise floor 62dB? DFT bins act like an analog spectrum analyzer with bandwidth of f s /N, rather than f s /2 The DFT noise floor is 1log 1 (N/2)dB below the actual noise floor (assuming white noise) Amplitude [dbfs] N=248 3dB f /f s -12 For N=248: 3dB EECS 247 Lecture 14: Data Converters 25 H.K. Page 14

8 DFT Plot Annotation 1. Specify how many DFT points (N) are used, or 2. Shift DFT noise floor by 1log 1 (N/2)dB, or 3. Normalize to "noise power in 1Hz bandwidth" EECS 247 Lecture 14: Data Converters 25 H.K. Page 15 Signal S DC Distortion D Noise N Spectral Performance Metrics ADC Including Nonlinearities Signal-to-noise ratio SNR = S / N Signal-to-distortion ratio SDR = S / D Signal-to-noise+distortion ratio SNDR = S / (N+D) Spurious-free dynamic range SFDR EECS 247 Lecture 14: Data Converters 25 H.K. Page 16

9 Harmonic Components At multiples of f x Aliasing: f signal = f x =.18 f s f 2 = 2 f =.36 f s f 3 = 3 f =.54 f s.46 f s f 4 = 4 f =.72 f s.28 f s f 5 = 5 f =.9 f s.1 f s f 6 = 6 f = 1.8 f s.8 f s EECS 247 Lecture 14: Data Converters 25 H.K. Page 17 Spectrum versus INL, DNL.3 DNL and INL of 1 Bit converter DNL [LSB] -.3 Good DNL and poor INL suggests distortion problem 2 INL [LSB] INL Not fully symmetric bin # EECS 247 Lecture 14: Data Converters 25 H.K. Page 18

10 Relationship INL-SFDR/SNDR Depends on "shape" of INL Rule of Thumb: SFDR 2log(2 B /INL) E.g. 1LSB INL, 1b SFDR 6dB Beware, this is of course only true under the same conditions at which the INL was taken, i.e. typically low input frequency EECS 247 Lecture 14: Data Converters 25 H.K. Page 19 ADC Noise Example At right is the spectrum of a 1-Bit converter SNDR = 47dB something s amiss Distortion? SDR = 59.9dB no Amplitude [ dbfs ] N = 496 SNR = 49.3dB SDR = 59.9dB SNDR = 47.dB SFDR = 6.9dB Must be a noise problem, but is it thermal or quantization noise? Frequency [ f / f s ] EECS 247 Lecture 14: Data Converters 25 H.K. Page 2

11 Noise Investigation At right is the spectrum of the same 1-Bit converter for f x = f s / 16 Since f x divides f s, the quantization noise is periodic! It falls into the same bins the harmonics would normally occupy Amplitude [ dbfs ] N = 496 SNR = 65.dB SDR = 48.4dB SNDR = 47.2dB SFDR = 49.5dB Hence SNR thermal noise SDR quantization noise (apparently the culprit) Frequency [ f / f s ] EECS 247 Lecture 14: Data Converters 25 H.K. Page 21 Noise Investigation After re-design and re-fab. Same test performed: (f x = f s / 16) The quantization noise is not a major error: SDR = 74dB SNR = 56.1dB This corresponds to Gaussian thermal noise with variance /2 at the converter input a reasonable design choice Amplitude [ dbfs ] N = 496 SNR = 56.1dB SDR = 73.9dB SNDR = 55.dB SFDR = 77.5dB Frequency [ f / f s ] EECS 247 Lecture 14: Data Converters 25 H.K. Page 22

12 Noise Investigation The DNL and INL confirm the good result DNL [LSB] DNL and INL of 1 Bit converter -.2 / +.2 LSB But the INL shows some bowing let s see if our test masked a distortion problem INL [LSB] / +.2 LSB 5 1 bin # EECS 247 Lecture 14: Data Converters 25 H.K. Page 23 Noise Investigation For that we revert to simulating with f s /f x noninteger A 3 rd harmonic is barely visible Amplitude [ dbfs ] N = 496 SNR = 55.9dB SDR = 76.4dB SNDR = 55.1dB SFDR = 77.3dB How can we lift it out of the noise? Frequency [ f / f s ] EECS 247 Lecture 14: Data Converters 25 H.K. Page 24

13 Noise Investigation Increasing N, the number of samples (and hence the measurement or simulation time) distributes the noise over more bins More bins less noise power per bin (total noise stays constant) Amplitude [ dbfs ] -5-1 N = SNR = 55.9dB SDR = 77.9dB SNDR = 55.2dB SFDR = 78.5dB SFDR = 78dB for 1Bit is acceptable in many -15 applications Frequency [ f / f s ] EECS 247 Lecture 14: Data Converters 25 H.K. Page 25 SNR Degradation due to DNL [Source: Ion Opris] For ideal quantizer we assumed uniform quantization error over +/- /2 Let's now add uniform DNL over +/-.5LSB and repeat math... EECS 247 Lecture 14: Data Converters 25 H.K. Page 26

14 SNR Degradation due to DNL Integrate triangular pdf: e e = 2 (1 e) de = 6 SNR = 6.2 N 1.25 [db] Compare to ideal quantizer: e + / 2 2 = / e de = 12 3dB SNR = 6.2 N [db] EECS 247 Lecture 14: Data Converters 25 H.K. Page 27 SNR Degradation due to DNL More general case: Uniform quantization error ±.5 Uniform DNL error ±DNL [LSB] Convolution yields trapezoid SQNR becomes: N SQNR = 2 DNL EECS 247 Lecture 14: Data Converters 25 H.K. Page 28

15 SNR Degradation due to DNL Degradation in db: 8 SQNR 1 deg = log 8 1 DNL _ 2 SNR Degradation [db] DNL [LSB] EECS 247 Lecture 14: Data Converters 25 H.K. Page Uniform DNL? # of occurrences DNL DNL distribution of 12-bit ADC test chip Not quite uniform... EECS 247 Lecture 14: Data Converters 25 H.K. Page 3

16 Effective Number of Bits (ENOB) Is a 12-Bit converter with 68dB SNDR really a 12-Bit converter? Effective Number of Bits 1.76dB ENOB = SNDR 6.2dB = = 11.Bits 6.2 EECS 247 Lecture 14: Data Converters 25 H.K. Page 31 ENOB At best, we get "ideal" ENOB only for zero thermal noise, zero DNL, zero INL Low noise is costly, 4x penalty in power per (ENOB-) bit or 6dB SNDR Rule of thumb for good performance /power tradeoff: ENOB < N-1 EECS 247 Lecture 14: Data Converters 25 H.K. Page 32

17 ENOB Survey R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on Selected Areas in Communications, pp , April 1999 EECS 247 Lecture 14: Data Converters 25 H.K. Page 33 Converter Testing Practical Aspects EECS 247 Lecture 14: Data Converters 25 H.K. Page 34

18 Just Got Silicon Back... Now what? Practical aspects of converter testing Equipment requirements Pitfalls EECS 247 Lecture 14: Data Converters 25 H.K. Page 35 Direct ADC-DAC Test Device Under Test (DUT) Signal Generator V in V out Specrum ADC DAC Analyzer Clock Generator Need a very good DAC Actually a good way to "get started"... EECS 247 Lecture 14: Data Converters 25 H.K. Page 36

19 Direct ADC-DAC Test Device Under Test (DUT) Signal Generator Bandpass or Lowpass Filter V in ADC DAC Notch Filter Clock Generator Spectrum Analyzer Issues to beware of: Linearity of the signal generator output has to be much better than ADC linearity Spectrum analyzer nonlinearities May need to build/purchase filters to address one or both above problems Clock generator signal jitter EECS 247 Lecture 14: Data Converters 25 H.K. Page 37 Filtering ADC Input Signal Signal Generator Output Signal Amplitude Bandpass Filter... 2f in 3f in 4f in... f f in ADC Input Signal Amplitude... f in 2f in 3f in 4f in... f EECS 247 Lecture 14: Data Converters 25 H.K. Page 38

20 Filtering Input to Spectrum Analyzer Prevent Signal Distortion Incurred by Spec. Analyzer DAC Output Signal Amplitude Notch (Band Reject) Filter... Spectrum Analyzer Input Signal Amplitude f in 2f in 3f in 4f in... f f in 2f in 3f in 4f in... f... EECS 247 Lecture 14: Data Converters 25 H.K. Page 39 ADC Test Setup Specs? Signal Generator V in Evaluation Board? ADC How to get data across? Data Acquisition PC Clock Generator Specs? EECS 247 Lecture 14: Data Converters 25 H.K. Page 4

21 Example: State-Of-The-Art ADC (21).35micron technology & 3V Supply [W. Yang et al., "A 3-V 34-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE J. of Solid-State Circuits, Dec. 21] Your converter will perform even better... Testing a high performance converter may be just as challenging as designing it! Key to success is to be aware of test setup and equipment limitations EECS 247 Lecture 14: Data Converters 25 H.K. Page 41 Signal Source Need: f in =f s /2=37.5MHz Let's see, how about the "value priced" signal generator available in most labs... f=...15mhz Harmonic distortion (f>1mhz): -35dBc Does not cover the required frequency range & poor linearity EECS 247 Lecture 14: Data Converters 25 H.K. Page 42

22 A Better Signal Source OK, now we've spent about $4k, this should work now... (?) f=1khz...3ghz Harmonic distortion (f>1mhz): -3dBc! Still need a filter to elliminate harmonic distortion! EECS 247 Lecture 14: Data Converters 25 H.K. Page 43 Filtering Out Harmonics BP Filter Amplitude... f in 2f in 3f in 4f in... f Given HD=-3dBc, we need a stopband rejection > 65dB to get SFDR>95dB EECS 247 Lecture 14: Data Converters 25 H.K. Page 44

23 Available Filters or Fixed frequency filters! Want to test at many frequencies Need to have many different filters! EECS 247 Lecture 14: Data Converters 25 H.K. Page 45 Example: ADC Linearity Test EECS 247 Lecture 14: Data Converters 25 H.K. Page 46

24 Tunable Filter EECS 247 Lecture 14: Data Converters 25 H.K. Page 47 Filter Distortion Beware: The filters themselves could also introduce distortion Distortion is usually not specified, need to contact manufacturer directly! Often guaranteed: HD<-85dBc, Don't trust your filters blindly... EECS 247 Lecture 14: Data Converters 25 H.K. Page 48

25 Clock Generator Let us check if for the clock a "valuepriced" signal generator will suffice... No! The clock signal controls sampling instants which we assumed to be precisely equi-distant in time (period T) Variability in T causes errors "Aperture Uncertainty" or "Aperture Jitter" How much Jitter can we tolerate? EECS 247 Lecture 14: Data Converters 25 H.K. Page 49 Clock Jitter Sampling jitter adds an error voltage proportional to the product of (t J -t ) and the derivative of the input signal at the sampling instant x(t) x (t ) actual sampling time t J Jitter doesn t matter when sampling dc signals (x (t )=) nominal (ideal) sampling time t EECS 247 Lecture 14: Data Converters 25 H.K. Page 5

26 Clock Jitter The error voltage is e = x (t )(t J t ) x(t) x (t ) actual sampling time t J error nominal sampling time t EECS 247 Lecture 14: Data Converters 25 H.K. Page 51 Sinusoidal input Amplitude: Frequency: Jitter: max x x x Jitter Example A f x dt ( π ) x(t) = Asin 2 ft x ( π ) x'(t) = 2π f Acos 2 ft x'(t) 2π f A Requirement: e(t) x'(t)dt e(t) 2π f Adt x # of Bits Worst case A A fs 2 2 = FS fx = A e(t) << dt << B 2 π f s f s FS B+ 1 1 MHz 1 MHz 1 MHz dt <<.5 ps.8 ps 1.2 ps EECS 247 Lecture 14: Data Converters 25 H.K. Page 52

27 Law of Jitter The worst case looks pretty stringent what about the average? Let s calculate the mean squared jitter error (variance) If we re sampling a sinusoidal signal x(t) = Asin(2πf x t), then x (t) = 2πf x Acos(2πf x t) E{[x (t)] 2 } = 2π 2 f x2 A 2 Assume the jitter has variance E{(t J -t ) 2 } = τ 2 EECS 247 Lecture 14: Data Converters 25 H.K. Page 53 Law of Jitter If x (t) and the jitter are independent E{[x (t)(t J -t )] 2 }= E{[x (t)] 2 } E{(t J -t ) 2 } Hence, the jitter error power is E{e 2 } = 2p 2 f x2 A 2 t 2 If the jitter is uncorrelated from sample to sample, this jitter noise is white EECS 247 Lecture 14: Data Converters 25 H.K. Page 54

28 Law of Jitter DR jitter 2 A / 2 = π f A τ x 1 = 2 2 2π f τ x = 2log ( 2πf τ ) x ADC under test: SNR=73dB f in =37.5MHz τ<1ps rms! EECS 247 Lecture 14: Data Converters 25 H.K. Page 55 More on Jitter Once we have a good enough generator, other circuit and test setup related issues may determine jitter, but... Usually, clock jitter in the single-digit pico-second range can be prevented by appropriate design techniques Separate supplies Separate analog and digital clocks Short inverter chains between clock source and destination Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter: RMS noise proportional to input frequency RMS noise proportional to input amplitude In cases where clock jitter limits the dynamic range, it s easy to tell, but may be difficult to fix... EECS 247 Lecture 14: Data Converters 25 H.K. Page 56

29 Evaluation Board Planning begins with converter pin-out Example of poor pin-out clock pin right next to a digital output... Not "Black Magic", but weeks of design time and studying Key aspects Supply/ground routing, bypass capacitors Coupling between signals Good idea to look at ADC vendor datasheets for example layouts/schematics/application notes EECS 247 Lecture 14: Data Converters 25 H.K. Page 57 Vendor Eval Board Layout [Analog Devices AD9235 Data Sheet] EECS 247 Lecture 14: Data Converters 25 H.K. Page 58

30 One thing to remember... A converter does not just have one "input" pin but: Clock Power Supply, Ground Reference Voltage For good practices on how to avoid issues see e.g.: Analog Devices Application Note 345: "Grounding for Low-and-High-Frequency Circuits" Maxim Application Note 729: "Dynamic Testing of High-Speed ADCs, Part 2" EECS 247 Lecture 14: Data Converters 25 H.K. Page 59 How to Get the Bits Off Chip? "Full swing" CMOS signaling works well for f CLK <1MHz But we want to build faster ADCs... Alternative to CMOS: LVDS Low Voltage Differential Signaling LVDS vs. CMOS: Higher speed, more power efficient at high speed Two pins/bit! EECS 247 Lecture 14: Data Converters 25 H.K. Page 6