Analog-to-Digital Converters

Size: px
Start display at page:

Download "Analog-to-Digital Converters"

Transcription

1 EE47 Lecture 3 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ modulator Practical implementation Effect of various building block nonidealities on the ΣΔ performance Integrator maximum signal handling capability Integrator finite DC gain Comparator hysteresis Integrator non-linearity EECS 47- Lecture 3 Oversampled ADCs 009 Page 1 Analog-to-Digital Converters Two categories: Nyquist rate ADCs f sig max ~ 0.5xf sampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max. ~14bits Oversampled ADCs f sig max << 0.5xf sampling Maximum possible signal bandwidth lower compared to nyquist Maximum achievable resolution high (18 to 0bits!) EECS 47- Lecture 3 Oversampled ADCs 009 Page

2 The Case for Oversampling Nyquist sampling: Signal f s B Freq narrow transition AA-Filter f s >B +δ Sampler Nyquist ADC DSP Oversampling: Signal f s >> f N?? B Freq wide transition AA-Filter f s = Mf N Sampler Oversampled ADC DSP Nyquist rate f N ~B Oversampling rate M = f s /f N >> 1 EECS 47- Lecture 3 Oversampled ADCs 009 Page 3 Nyquist v.s. Oversampled Converters Antialiasing Requirements X(f) Input Signal f B frequency Nyquist Sampling f B f s f S ~f B Anti-aliasing Filter f s Oversampling frequency f B f S >> f B f s frequency EECS 47- Lecture 3 Oversampled ADCs 009 Page 4

3 Oversampling Benefits Almost no stringent requirements imposed on analog building blocks Takes advantage of the availability of low cost, low power digital filtering Relaxed transition band requirements for analog anti-aliasing filters Reduced baseband quantization noise power Allows trading speed for resolution EECS 47- Lecture 3 Oversampled ADCs 009 Page 5 ADC Converters Baseband Noise For a quantizer with quantization step size Δ and sampling rate f s : Quantization noise power distributed uniformly across Nyquist bandwidth ( f s /) N e (f) N B -f B f s / -f s / f B Power spectral density: e Δ 1 N(f) e = = fs 1 fs Noise is distributed over the Nyquist band f s / to f s / EECS 47- Lecture 3 Oversampled ADCs 009 Page 6

4 Oversampled Converters Baseband Noise fb fb Δ 1 SB = N e( f )df = df fb fb 1 fs N e (f) Δ fb = 1 f N B s where for fb = f s/ Δ SB0 = -f s / -f B f B f s / 1 fb SB0 SB = SB0 = f s M fs where M = = oversampling ratio f B EECS 47- Lecture 3 Oversampled ADCs 009 Page 7 B Oversampled Converters Baseband Noise fb SB0 SB = SB0 = f s M fs where M = = oversampling ratio f X increase in M 3dB reduction in S B ½ bit increase in resolution/octave oversampling To further increase the improvement in resolution: Embed quantizer in a feedback loop Noise shaping (sigma delta modulation) EECS 47- Lecture 3 Oversampled ADCs 009 Page 8

5 Pulse-Count Modulation V in =/8 Nyquist ADC t/ts 1 /8 V in =/8 Oversampled ADC, M = t/ts Mean of pulse-count signal approximates analog input! EECS 47- Lecture 3 Oversampled ADCs 009 Page 9 Pulse-Count Output Spectrum Magnitude /8 Digital filter B f s /4 f s / f Signal band of interest: low frequencies, f < B << f s Quantization error: high frequency, B f s / Separate with digital low-pass filter! EECS 47- Lecture 3 Oversampled ADCs 009 Page 10

6 Oversampled ADC Predictive Coding v IN + _ ADC D OUT 1-bit Digital Filter N-bit Predictor Quantize the difference signal rather than the signal itself Smaller input to ADC Buy dynamic range Only works if combined with oversampling 1-Bit digital output Digital filter computes average N-bit output EECS 47- Lecture 3 Oversampled ADCs 009 Page 11 Oversampled ADC Signal B Freq wide transition Analog AA-Filter f s = Mf N Sampler E.g. Pulse-Count Modulator Modulator 1-Bit Digital f s1 = M f N Decimator narrow transition Digital AA-Filter N-Bit Digital f s = f N + δ DSP Decimator: Digital (low-pass) filter Removes quantization noise for f > B Provides anti-alias filtering for DSP Narrow transition band, high-order (digital filters with high order consume significantly smaller power & area compared to analog filters) 1-Bit input, N-Bit output (essentially computes average ) EECS 47- Lecture 3 Oversampled ADCs 009 Page 1

7 Modulator or Analog Front End (AFE) Objectives: Convert analog input to 1-Bit pulse density stream Move quantization error to high frequencies f >>B Operates at high frequency f s >> f N M = 8 56 (typical).104 Since modulator operated at high frequencies need to keep analog circuitry simple ΣΔ = ΔΣ Modulator EECS 47- Lecture 3 Oversampled ADCs 009 Page 13 Sigma- Delta Modulators Analog 1-Bit ΣΔ modulators convert a continuous time analog input v IN into a 1-Bit sequence D OUT f s V IN + _ H(z) D OUT DAC Loop filter 1b Quantizer (comparator) EECS 47- Lecture 3 Oversampled ADCs 009 Page 14

8 Sigma-Delta Modulators The loop filter H can be either switched-capacitor or continuous time Switched-capacitor filters are easier to implement + frequency characteristics scale with clock rate Continuous time filters provide anti-aliasing protection f s V IN + _ H(z) D OUT DAC EECS 47- Lecture 3 Oversampled ADCs 009 Page 15 Oversampling A/D Conversion f s f s /M Input Signal Bandwidth B=f s /M Oversampling Modulator (AFE) f s Decimation Filter f s /M f s = sampling rate M= oversampling ratio Analog front-end oversampled noise-shaping modulator Converts original signal to a 1-bit digital output at the high rate of (BXM) Digital back-end digital filter (decimator) Removes out-of-band quantization noise Provides anti-aliasing to allow lower sampling rate EECS 47- Lecture 3 Oversampled ADCs 009 Page 16

9 1 st Order ΣΔ Modulator 1 st order modulator, simplest loop filter an integrator V IN + _ H(z) = z -1 1 z -1 D OUT DAC Note: Non-linear system with memory difficult to analyze EECS 47- Lecture 3 Oversampled ADCs 009 Page 17 1 st Order ΣΔ Modulator Switched-capacitor implementation V IN φ 1 φ φ - + 1,0 D OUT +Δ/ -Δ/ Full-scale input range Δ Note that Δ here is different from Nyquist rate ADC Δ (1LSB) EECS 47- Lecture 3 Oversampled ADCs 009 Page 18

10 1 st Order ΔΣ Modulator V IN -Δ/ V IN +Δ/ + _ D OUT -Δ/ or +Δ/ DAC Properties of the 1 st order modulator: Maximum analog input range is equal to the DAC reference levels The average value of D OUT must equal the average value of V IN +1 s (or 1 s) density in D OUT is an inherently monotonic function of V IN To 1 st order, linearity is not dependent on component matching Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error but loose this inherent monotonicity & relaxed matching requirements EECS 47- Lecture 3 Oversampled ADCs 009 Page 19 Analog input -Δ/ V in +Δ/ 1 st Order ΣΔ Modulator Sine Wave Tally of quantization error 1 X z z Integrator Q Comparator 1-Bit quantizer 3 Y 1-Bit digital output stream, -1, +1 Instantaneous quantization error Implicit 1-Bit DAC +Δ/, -Δ/ (Δ = ) M chosen to be 8 (low) to ease observability EECS 47- Lecture 3 Oversampled ADCs 009 Page 0

11 1 st Order Modulator Signals st Order Sigma-Delta X Q Y Xanalog input Q tally of q-error Ydigital/DAC output Amplitude Average of Y approximates X That is exactly what the digital filter does Time [ t/t ] T = 1/f s = 1/ (M f N ) *M is usually >>8 EECS 47- Lecture 3 Oversampled ADCs 009 Page 1 ΣΔ Modulator Characteristics Inherently linear for 1-Bit DAC Quantization noise and thermal noise (KT/C) distributed over f s / to +f s / Total noise within signal bandwidth reduced by 1/M Required capacitor sizes x1/m compared to nyquist rate ADCs Very high SQNR achievable (> 0 Bits!) To first order, quantization error independent of component matching Limited to moderate & low speed EECS 47- Lecture 3 Oversampled ADCs 009 Page

12 30 1 st Order ΣΔ Modulator Output Spectrum Quantization noise definitely not white! Amplitude [ dbwn ] Input Frequency [ f /f s ] Skewed towards higher frequencies Notice the distinct tones dbwn (db White Noise) scale sets the 0dB line at the noise per bin of a random -1, +1 sequence EECS 47- Lecture 3 Oversampled ADCs 009 Page 3 Quantization Noise Analysis Integrator Quantization Error e(kt) x(kt) Σ 1 z H( z) = 1 z 1 Σ Quantizer Model y(kt) Sigma-Delta modulators are nonlinear systems with memory difficult to analyze directly Representing the quantizer as an additive noise source linearizes the system EECS 47- Lecture 3 Oversampled ADCs 009 Page 4

13 Signal Transfer Function 1 z H( z) = 1 z ω0 H( jω ) = jω 1 x(kt) Σ - Integrator H(z) y(kt) Signal transfer function low pass function: 1 HSig ( jω ) = 1 + s ω0 Y( z) H( z) 1 HSig ( z) = = = z X( z) 1 + H( z) Delay Magnitude f 0 Frequency EECS 47- Lecture 3 Oversampled ADCs 009 Page 5 v i Σ - v i Σ - ω 0 jω v f n f 0 Noise Transfer Function Qualitative Analysis ω0 jω v n v o v o v eq eq vn v = f f 0 = f f 0 eq vn v Σ v i - ω0 jω v o f 0 Frequency Input referred-noise DC (s-plane) EECS 47- Lecture 3 Oversampled ADCs 009 Page 6

14 x(kt) 1 st Order ΣΔ Modulator STF and NTF Σ Quantization Error e(kt) Integrator 1 z H( z) = 1 1 z Σ Quantizer Model y(kt) Signal transfer function: Y( z) H( z) 1 STF = = = z X( z) 1 + H( z) Delay Noise transfer function: Y ( z) 1 NTF = = = 1 z E( z) 1+ H ( z) 1 Differentiator EECS 47- Lecture 3 Oversampled ADCs 009 Page 7 jωt/ Noise Transfer Function Y() z 1 1 jωt NTF = = = 1 z set z = e Ez () 1 + Hz () jωt NTF( jω) = (1 e )=e = e jsin T/ jωt/ / j ( ωt ) e ( ω ) jωt/ ( ω ) jπ ( ω ) = e e sin T/ ( ωt π) / = sin / where T = 1/ fs Thus: NTF( f ) =sin T / =sin π f / f e jωt/ jωt/ e ( s ) Output noise power spectrum: N ( f) = NTF( f) N ( f) y e EECS 47- Lecture 3 Oversampled ADCs 009 Page 8

15 First Order ΣΔ Modulator Noise Transfer Characteristics Noise Shaping Function Low-pass Digital Filter N ( f ) = NTF( f ) N ( f ) y ( π ) = 4sin f / f N ( f ) First-Order Noise Shaping s e e f B f N f s / frequency Key Point: Most of quantization noise pushed out of frequency band of interest EECS 47- Lecture 3 Oversampled ADCs 009 Page 9 Quantizer Error For quantizers with many bits Pdf 1/Δ e Δ ( kt ) = 1 -Δ/ Let s use the same expression for the 1-bit case Use simulation to verify validity +Δ/ Quant. Noise Experience: Often sufficiently accurate to be useful, with enough exceptions to be careful EECS 47- Lecture 3 Oversampled ADCs 009 Page 30

16 First Order ΣΔ Modulator Simulated Noise Transfer Characteristic Amplitude [ dbwn ] Signal Simulated output spectrum Computed NTF ( π ) N ( f ) = 4 sin f / f y s Confirms assumption of quantization noise being white at insertion point Linearized model seems to be accurate Frequency [f /f s ] EECS 47- Lecture 3 Oversampled ADCs 009 Page 31 First Order ΣΔ Modulator In-Band Quantization Noise ( ) NTF z = 1 z 1 s ( ) ( π ) NTF f = 4 sin f / f for M >> 1 Y B B Q ( ) ( ) S = S f NTF z df z= e π jft fs M fs M 1 Δ f 1 s ( sinπ ft) df S Q π 1 Δ 3 3 M 1 Total in-band quantization noise EECS 47- Lecture 3 Oversampled ADCs 009 Page 3

17 1 st Order ΣΔ Dynamic Range full-scale signal power S X DR = 10log 10log inband noise power = SQ S S S S X Q X Q 1 Δ = sinusoidal input, STF = 1 π 1 Δ = 3 3 M = M π DR = 10log M = 10log + 30log M π π M DR db 3 4 db db DR = 3.4dB + 30log M X increase in M 9dB (1.5-Bit) increase in dynamic range EECS 47- Lecture 3 Oversampled ADCs 009 Page 33 Oversampling and Noise Shaping ΣΔ modulators have interesting characteristics Unity gain for input signal V IN Significant attenuation of in-band quantization noise injected at quantizer input Performance significantly better than 1-bit noise quantizer possible for frequencies << f s Increase in oversampling (M = f s /f N >> 1) improves SQNR considerably 1 st order ΣΔ: DR increases 9dB for each doubling of M To first order, SQNR independent of circuit complexity and accuracy Analysis assumes that the quantizer noise is white Not entirely true in practice, especially for low-order modulators Practical modulators suffer from other noise sources also (e.g. thermal & 1/f noise) EECS 47- Lecture 3 Oversampled ADCs 009 Page 34

18 1 st Order ΣΔ Modulator Response to DC Input Matlab & Simulink model used Input DC at 1/11 full-scale level 1 X Q 3 Y DC Input=1/11 FS z z Integrator Comparator EECS 47- Lecture 3 Oversampled ADCs 009 Page 35 1 st Order ΣΔ Response to DC Input Amplitude [ dbwn ] DC Component Frequency [ f /f s ] DC input A = 1/11 Output spectrum shows DC component plus distinct tones!! Tones frequency shaped the same as quantization noise More prominent at higher frequencies Seems like periodic quantization noise EECS 47- Lecture 3 Oversampled ADCs 009 Page 36

19 Output Limit Cycle Oscillation First order sigma-delta, DC input Time [t/t] DC input 1/11 Periodic sequence: Average =1/11 EECS 47- Lecture 3 Oversampled ADCs 009 Page 37 1 st Order ΣΔ Limit Cycle Oscillation Amplitude In-band spurious tone with f ~ DC input level First-Order Noise Shaping f B f N Frequency f s / Problem: quantization noise becomes periodic in response to low level DC inputs & could fall within passband of interest! Solution: Use dithering (inject noise-like signal at the input ): randomizes quantization noise - If circuit thermal noise is large enough acts as dither Second order loop EECS 47- Lecture 3 Oversampled ADCs 009 Page 38

20 1 st Order ΣΔ Modulator Linearized Model Analysis ( ) 1 1 Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 47- Lecture 3 Oversampled ADCs 009 Page 39 nd Order ΣΔ Modulator Two integrators in series Single quantizer (typically 1-bit) Feedback from output to both integrators Tones less prominent compared to 1st order EECS 47- Lecture 3 Oversampled ADCs 009 Page 40

21 nd Order ΣΔ Modulator Linearized Model Analysis ( ) Recursive drivation: Y = X + E E + E n n 1 n n 1 n ( ) Using the delay operator z : Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 47- Lecture 3 Oversampled ADCs 009 Page 41 NTF z NTF 4 1 ( ) = ( 1 z ) ( f ) = ( π ) nd Order ΣΔ Modulator In-Band Quantization Noise = sin f / f for M >> 1 B Q = Q ( ) ( ) z= e B fs fs M M 1 Δ f 1 s S S f NTF z df 4 1 Δ 5 π 5 M 1 s 4 ( sinπ ft) π jft 4 df EECS 47- Lecture 3 Oversampled ADCs 009 Page 4

22 Quantization Noise nd Order ΣΔ Modulator vs 1 st Order Modulator S Q π 1 Δ 3 3 M 1 Noise Shaping Function Ideal Low-pass Digital Filter nd -Order Noise Shaping 1 st Order Noise Shaping S Q 4 π 1 Δ 5 5 M 1 f B Frequency f s / EECS 47- Lecture 3 Oversampled ADCs 009 Page 43 4 nd Order ΣΔ Modulator Dynamic Range full-scale signal power S X DR = 10log 10log inband noise power = SQ S S S S X Q X Q 1 Δ = sinusoidal input, STF = 1 π 1 Δ = 5 5 M = M 4 π DR = 10log M = 10log + 50log M 4 4 π π DR = 11.1dB+ 50log M X increase in M 15dB (.5-bit) increase in DR EECS 47- Lecture 3 Oversampled ADCs 009 Page 44

23 nd Order vs 1 st Order ΣΔ Modulator Dynamic Range M 16 nd Order D.R. 49 db (7.8bit) 1 st Order D.R. 33dB (5.bit) Resolution ( nd order - 1 st order).6 bit 3 64 db (10.3bit) 4dB (6.7bit) 3.6 bit db (17.9bit) 68.8dB (11.1bit) 6.8 bit db (.8bit) 87dB (14.bit) 8.6 bit Note: For higher oversampling ratios resolution of nd order modulator significantly higher compared to 1 st order EECS 47- Lecture 3 Oversampled ADCs 009 Page 45 Digital audio application Signal bandwidth 0kHz Desired resolution 16-bit nd Order ΣΔ Modulator Example 16 bit 98 db Dynamic Range DRnd order ΣΔ = -11.1dB + 50log M M = 153 min M 56= 8 ( DR=109dB) two reasons: 1. Allow some margin so that thermal noise dominate & provides dithering to minimize level of in-band limit cycle oscillation. Choice of M power of ease of digital filter implementation Sampling rate (x0khz + 5kHz)M = 1MHz (quite reasonable!) EECS 47- Lecture 3 Oversampled ADCs 009 Page 46

24 Limit Cycle Tones in 1 st Order & nd Order ΣΔ Modulator Higher oversampling ratio lower tones nd order tones much lower compared to 1 st 6dB 1 st Order ΣΔ Modulator Xincrease in M decreases the tones by 6dB for 1 st order loop and 1dB for nd order loop 1dB Inband Quantization noise nd Order ΣΔ Modulator Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 6, pp , April R. Gray, Spectral analysis of quantization noise in a single-loop sigma delta modulator with dc input, IEEE Trans. Commun., vol. 37, pp , June EECS 47- Lecture 3 Oversampled ADCs 009 Page 47 ΣΔ Implementation Practical Design Considerations Internal node scaling & clipping Effect of finite opamp gain & linearity KT/C noise Opamp noise Effect of comparator nonidealities Power dissipation considerations EECS 47- Lecture 3 Oversampled ADCs 009 Page 48

25 Switched-Capacitor Implementation nd Order ΣΔ Nodes Scaled for Maximum Dynamic Range Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full-scale (Δ) Note: Non-idealities associated with nd integrator and quantizer when referred to the ΣΔ input is attenuated by 1 st integrator high gain The only building block requiring low-noise and high accuracy is the 1 st integrator Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp , Dec EECS 47- Lecture 3 Oversampled ADCs 009 Page 49 nd Order ΣΔ Modulator Example: Switched-Capacitor Implementation V IN Dout Fully differential front-end Two bottom-plate integrators 1-bit DAC is made of switches and Vrefs EECS 47- Lecture 3 Oversampled ADCs 009 Page 50

26 Switched-Capacitor Implementation nd Order ΣΔ Phase 1 V IN Dout During phase 1: 1 st integrator samples Vin on 1 st stage C1 nd integrator samples output of 1 st integrator Comparator senses polarity of nd intg. output result saved in output latch S3 opens prior to S1 minimize effect of charge injection EECS 47- Lecture 3 Oversampled ADCs 009 Page 51 Switched-Capacitor Implementation nd Order ΣΔ Phase V IN Dout Note: S connects integrator inputs to + or Vref, polarity depends on whether Dout is 0 or 1 Input sampled during φ 1 or + C1xVref transferred to C DAC output subtraction & integration EECS 47- Lecture 3 Oversampled ADCs 009 Page 5

27 nd Order ΣΔ Modulator Switched-Capacitor Implementation The ½ loss in front of each integrator implemented by choice of: C =C 1 f 0 intg =f s /(4π) EECS 47- Lecture 3 Oversampled ADCs 009 Page 53 Design Phase Simulations Design of oversampled ADCs requires simulation of extremely long data traces due to the oversampled nature of the system SPICE type simulators: Normally used to test for gross circuit errors only Too slow for detailed performance verification Typically, behavioral modeling is used in MATLAB-like environments Circuit non-idealities either computed or found by using SPICE at subcircuit level Non-idealities introduced in the behavioral model one-by-one first to fully understand the effect of each individually Next step is to add as many of the non-idealities simultaneously as possible to verify whether there are interaction among non-idealities EECS 47- Lecture 3 Oversampled ADCs 009 Page 54

28 Example: Testing ΣΔ ADC Note: The Nyquist ADC tests such as INL and DNL test do not apply to ΣΔ modulator type ADCS nd order ΣΔ M=56 Analytical Measured ΣΔ testing is performed via SNDR as a function of input signal level EECS 47- Lecture 3 Oversampled ADCs 009 Page 55 nd Order ΣΔ Effect of 1 st Integrator Maximum Signal Handling Capability on SNR Behavioral model Non-idealities tested one by one M=56 1 st integrator maximum signal handling: 1.4, 1.5,1.6, and 1.7X Δ Effect of 1 st Integrator maximum signal handling capability on converter SNR No SNR loss for max. sig. handling >1.7Δ Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47- Lecture 3 Oversampled ADCs 009 Page 56

29 nd Order ΣΔ Effect of nd Integrator Maximum Signal Handling Capability on SNR nd integrator maximum signal handling: 0.75,1,1.5, 1.5, and 1.7X Δ Effect of nd Integrator maximum signal handling capability on SNR Νο SNR loss for max. sig. handling >1.7 Δ Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47- Lecture 3 Oversampled ADCs 009 Page 57 nd Order ΣΔ Effect of Integrator Finite DC Gain V i Integrator φ 1 φ CI Cs - a + a opamp gain at DC V o H ( z) H ( z) ideal Finit DC Gain ( ) 1 Cs z = 1 CI 1 z a z Cs 1 + a + Cs = CI CI 1 + a 1 z Cs 1 + a + CI H DC = a 1 1 EECS 47- Lecture 3 Oversampled ADCs 009 Page 58

30 log H ( s) a nd Order ΣΔ Effect of Integrator Finite DC Gain Ideal Integ. (a=infinite) ω 0 ω P1 = 0 a Integrator magnitude response e Q + _ H ( ω ) D OUT Note: Quantization transfer function wrt output has integrator in the feedback path: Dout = 1 eq 1 + H( DC for ideal integ: Dout = 0 DC for real integ: Dout 1 e a Q EECS 47- Lecture 3 Oversampled ADCs 009 Page 59 1 st & nd Order ΣΔ Effect of Integrator Finite DC Gain Max signal level a f 0 /a Low integrator DC gain Increase in total in-band quantization noise Can be shown: If a > M (oversampling ratio) Insignificant degradation in SNR Normally DC gain designed to be >> M in order to suppress nonlinearities EECS 47- Lecture 3 Oversampled ADCs 009 Page 60

31 nd Order ΣΔ Effect of Integrator Finite DC Gain M / a Example: a =M 0.4dB degradation in SNR a =M 1.4dB degradation in SNR Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47- Lecture 3 Oversampled ADCs 009 Page 61 nd Order ΣΔ Effect of Comparator Non-Idealities on ΣΔ Performance 1-bit A/D Single comparator Speed must be adequate for the operating sampling rate Input referred offset- feedback loop & high DC intg. gain suppresses the effect ΣΔ performance quite insensitive to comparator offset Input referred comparator noise- same as offset Hysteresis= Minimum overdrive required to change the output EECS 47- Lecture 3 Oversampled ADCs 009 Page 6

32 nd Order ΣΔ Comparator Hysteresis Hysteresis= Minimum overdrive required to change the output EECS 47- Lecture 3 Oversampled ADCs 009 Page 63 nd Order ΣΔ Comparator Hysteresis Hysteresis/Δ Comparator hysteresis < Δ/5 does not affect SNR E.g. Δ=1V, comparator hysteresis up to 40mV tolerable Key Point: One of the main advantages of ΣΔ ADCS Highly tolerant of comparator and in general building-block non-idealities EECS 47- Lecture 3 Oversampled ADCs 009 Page 64

33 nd Order ΣΔ Effect of Integrator Nonlinearities u(kt) Ideal Integrator Delay v(kt) v(kt + T ) = u(kt ) + v(kt ) With non-linearity added: 3 v(kt + T ) = u(kt ) + α u( kt ) + α 3 u( kt ) v(kt ) + β v( kt ) + β 3 v( kt ) +... Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47- Lecture 3 Oversampled ADCs 009 Page 65 nd Order ΣΔ Effect of Integrator Nonlinearities (Single-Ended) α = β = 0.01, 0.0, 0.05, 0.1% Simulation for single-ended topology Effect of even order nonlinearities can be significantly suppressed by using differential circuit topologies Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47- Lecture 3 Oversampled ADCs 009 Page 66

34 nd Order ΣΔ Effect of Integrator Nonlinearities α 3 = β 3 = 6dB =1Bit 0.05, 0.,1% 6dB =1Bit Simulation for single-ended topology Odd order nonlinearities (3 rd in this case) Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec EECS 47- Lecture 3 Oversampled ADCs 009 Page 67 nd Order ΣΔ Effect of Integrator Nonlinearities Odd order nonlinearities (usually 3 rd ) could case significant loss of SNR for high resolution oversampled ADCs Two significant source of non-linearities: Non-linearities associated with opamp used to build integrators Opamp open-loop non-linearities are suppressed by the loopgain since there is feedback around the opamp Class A opamps tend to have lower open loop gain but more linear output versus input transfer characteristic Class A/B opamps typically have higher open loop gain but non-linear transfer function. At times this type is preferred for ΣΔ AFE due to its superior slew rate compared to class A type Integrator capacitor non-linearites Poly-Sio-Poly capacitors non-linearity in the order of 10ppm/V Metal-Sio-Metal capacitors ~ 1ppm/V EECS 47- Lecture 3 Oversampled ADCs 009 Page 68

Summary Last Lecture

Summary Last Lecture Interleaved ADCs EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations

More information

EE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting

EE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting EE47 Lecture 6 This lecture is taped on Wed. Nov. 8 th due to conflict of regular class hours with a meeting Any questions regarding this lecture could be discussed during regular office hours or in class

More information

The Case for Oversampling

The Case for Oversampling EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ

More information

Summary Last Lecture

Summary Last Lecture EE47 Lecture 5 Pipelined ADCs (continued) How many bits per stage? Algorithmic ADCs utilizing pipeline structure Advanced background calibration techniques Oversampled ADCs Why oversampling? Pulse-count

More information

EE247 Lecture 26. EE247 Lecture 26

EE247 Lecture 26. EE247 Lecture 26 EE247 Lecture 26 Administrative EE247 Final exam: Date: Mon. Dec. 18 th Time: 12:30pm-3:30pm Location: 241 Cory Hall Extra office hours: Thurs. Dec. 14 th, 10:30am-12pm Closed book/course notes No calculators/cell

More information

EE247 Lecture 24. EE247 Lecture 24

EE247 Lecture 24. EE247 Lecture 24 EE247 Lecture 24 Administrative EE247 Final exam: Date: Wed. Dec. 15 th Time: -12:30pm-3:30pm- Location: 289 Cory Closed book/course notes No calculators/cell phones/pdas/computers Bring one 8x11 paper

More information

EE247 Lecture 27. EE247 Lecture 27

EE247 Lecture 27. EE247 Lecture 27 EE247 Lecture 27 Administrative EE247 Final exam: Date: Wed. Dec. 19 th Time: 12:30pm-3:30pm Location: 70 Evans Hall Extra office hours: Thurs. Dec. 13 th, 10:am2pm Closed course notes/books No calculators/cell

More information

EE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K.

EE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K. EE247 Lecture 22 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Figures of merit (FOM) and trends for ADCs How to use/not use FOM Oversampled ADCs EECS 247 Lecture 22:

More information

EE247 Lecture 26. EE247 Lecture 26

EE247 Lecture 26. EE247 Lecture 26 EE247 Lecture 26 Administrative Project submission: Project reports due Dec. 5th Please make an appointment with the instructor for a 15minute meeting on Monday Dec. 8 th Prepare to give a 3 to 7 minute

More information

EE247 Lecture 26. EE247 Lecture 26

EE247 Lecture 26. EE247 Lecture 26 EE247 Lecture 26 Administrative Final exam: Date: Tues. Dec. 13 th Time: 12:3pm-3:3pm Location: 285 Cory Office hours this week: Tues: 2:3p to 3:3p Wed: 1:3p to 2:3p (extra) Thurs: 2:3p to 3:3p Closed

More information

EE247 Lecture 25. Oversampled ADCs (continued)

EE247 Lecture 25. Oversampled ADCs (continued) EE247 Lecture 25 Oversampled ADCs (continued) Higher order ΣΔ modulators Last lecture Cascaded ΣΔ modulators (MASH) (continued) Single-loop single-quantizer modulators with multi-order filtering in the

More information

Tones. EECS 247 Lecture 21: Oversampled ADC Implementation 2002 B. Boser 1. 1/512 1/16-1/64 b1. 1/10 1 1/4 1/4 1/8 k1z -1 1-z -1 I1. k2z -1.

Tones. EECS 247 Lecture 21: Oversampled ADC Implementation 2002 B. Boser 1. 1/512 1/16-1/64 b1. 1/10 1 1/4 1/4 1/8 k1z -1 1-z -1 I1. k2z -1. Tones 5 th order Σ modulator DC inputs Tones Dither kt/c noise EECS 47 Lecture : Oversampled ADC Implementation B. Boser 5 th Order Modulator /5 /6-/64 b b b b X / /4 /4 /8 kz - -z - I kz - -z - I k3z

More information

Lecture #6: Analog-to-Digital Converter

Lecture #6: Analog-to-Digital Converter Lecture #6: Analog-to-Digital Converter All electrical signals in the real world are analog, and their waveforms are continuous in time. Since most signal processing is done digitally in discrete time,

More information

BandPass Sigma-Delta Modulator for wideband IF signals

BandPass Sigma-Delta Modulator for wideband IF signals BandPass Sigma-Delta Modulator for wideband IF signals Luca Daniel (University of California, Berkeley) Marco Sabatini (STMicroelectronics Berkeley Labs) maintain the same advantages of BaseBand converters

More information

Analog to Digital Conversion

Analog to Digital Conversion Analog to Digital Conversion Florian Erdinger Lehrstuhl für Schaltungstechnik und Simulation Technische Informatik der Uni Heidelberg VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg

More information

Oversampling Converters

Oversampling Converters Oversampling Converters Behzad Razavi Electrical Engineering Department University of California, Los Angeles Outline Basic Concepts First- and Second-Order Loops Effect of Circuit Nonidealities Cascaded

More information

Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC

Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC Jinseok Koh Wireless Analog Technology Center Texas Instruments Inc. Dallas, TX Outline Fundamentals for ADCs Over-sampling and Noise

More information

CHAPTER. delta-sigma modulators 1.0

CHAPTER. delta-sigma modulators 1.0 CHAPTER 1 CHAPTER Conventional delta-sigma modulators 1.0 This Chapter presents the traditional first- and second-order DSM. The main sources for non-ideal operation are described together with some commonly

More information

Cascaded Noise-Shaping Modulators for Oversampled Data Conversion

Cascaded Noise-Shaping Modulators for Oversampled Data Conversion Cascaded Noise-Shaping Modulators for Oversampled Data Conversion Bruce A. Wooley Stanford University B. Wooley, Stanford, 2004 1 Outline Oversampling modulators for A/D conversion Cascaded noise-shaping

More information

System on a Chip. Prof. Dr. Michael Kraft

System on a Chip. Prof. Dr. Michael Kraft System on a Chip Prof. Dr. Michael Kraft Lecture 5: Data Conversion ADC Background/Theory Examples Background Physical systems are typically analogue To apply digital signal processing, the analogue signal

More information

ESE 531: Digital Signal Processing

ESE 531: Digital Signal Processing ESE 531: Digital Signal Processing Lec 11: February 20, 2018 Data Converters, Noise Shaping Lecture Outline! Review: Multi-Rate Filter Banks " Quadrature Mirror Filters! Data Converters " Anti-aliasing

More information

Second-Order Sigma-Delta Modulator in Standard CMOS Technology

Second-Order Sigma-Delta Modulator in Standard CMOS Technology SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 1, No. 3, November 2004, 37-44 Second-Order Sigma-Delta Modulator in Standard CMOS Technology Dragiša Milovanović 1, Milan Savić 1, Miljan Nikolić 1 Abstract:

More information

Lecture 390 Oversampling ADCs Part I (3/29/10) Page 390-1

Lecture 390 Oversampling ADCs Part I (3/29/10) Page 390-1 Lecture 390 Oversampling ADCs Part I (3/29/0) Page 390 LECTURE 390 OVERSAMPLING ADCS PART I LECTURE ORGANIZATION Outline Introduction Deltasigma modulators Summary CMOS Analog Circuit Design, 2 nd Edition

More information

Fundamentals of Data Converters. DAVID KRESS Director of Technical Marketing

Fundamentals of Data Converters. DAVID KRESS Director of Technical Marketing Fundamentals of Data Converters DAVID KRESS Director of Technical Marketing 9/14/2016 Analog to Electronic Signal Processing Sensor (INPUT) Amp Converter Digital Processor Actuator (OUTPUT) Amp Converter

More information

ECEN 610 Mixed-Signal Interfaces

ECEN 610 Mixed-Signal Interfaces Spring 2014 S. Hoyos-ECEN-610 1 ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Oversampling ADC Spring 2014 S. Hoyos-ECEN-610 2 Spring 2014 S. Hoyos-ECEN-610

More information

ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter

ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter Brian L. Young youngbr@eecs.oregonstate.edu Oregon State University June 6, 28 I. INTRODUCTION The goal of the Spring 28, ECE 627 project

More information

INF4420. ΔΣ data converters. Jørgen Andreas Michaelsen Spring 2012

INF4420. ΔΣ data converters. Jørgen Andreas Michaelsen Spring 2012 INF4420 ΔΣ data converters Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Oversampling Noise shaping Circuit design issues Higher order noise shaping Introduction So far we have considered

More information

! Multi-Rate Filter Banks (con t) ! Data Converters. " Anti-aliasing " ADC. " Practical DAC. ! Noise Shaping

! Multi-Rate Filter Banks (con t) ! Data Converters.  Anti-aliasing  ADC.  Practical DAC. ! Noise Shaping Lecture Outline ESE 531: Digital Signal Processing! (con t)! Data Converters Lec 11: February 16th, 2017 Data Converters, Noise Shaping " Anti-aliasing " ADC " Quantization "! Noise Shaping 2! Use filter

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Final Exam EECS 247 H. Khorramabadi Tues., Dec. 14, 2010 FALL 2010 Name: SID: Total number of

More information

MASH 2-1 MULTI-BIT SIGMA-DELTA MODULATOR FOR WLAN L 2 ( ) ( ) 1( 1 1 1

MASH 2-1 MULTI-BIT SIGMA-DELTA MODULATOR FOR WLAN L 2 ( ) ( ) 1( 1 1 1 MASH 2- MULTI-BIT SIGMA-DELTA MODULATOR FOR WLAN Yu hang, Ning Xie, Hui Wang and Yejun He College of Information Engineering, Shenzhen University, Shenzhen, Guangdong 58060, China kensouren@yahoo.com.cn

More information

NPTEL. VLSI Data Conversion Circuits - Video course. Electronics & Communication Engineering.

NPTEL. VLSI Data Conversion Circuits - Video course. Electronics & Communication Engineering. NPTEL Syllabus VLSI Data Conversion Circuits - Video course COURSE OUTLINE This course covers the analysis and design of CMOS Analog-to-Digital and Digital-to-Analog Converters,with about 7 design assigments.

More information

EE247 Midterm Exam Statistics

EE247 Midterm Exam Statistics EE247 Lecture 22 Pipelined ADCs (continued) Effect gain stage, sub-dac non-idealities on overall ADC performance Digital calibration (continued) Correction for inter-stage gain nonlinearity Implementation

More information

ESE 531: Digital Signal Processing

ESE 531: Digital Signal Processing ESE 531: Digital Signal Processing Lec 12: February 21st, 2017 Data Converters, Noise Shaping (con t) Lecture Outline! Data Converters " Anti-aliasing " ADC " Quantization " Practical DAC! Noise Shaping

More information

Electronic Noise. Analog Dynamic Range

Electronic Noise. Analog Dynamic Range Electronic Noise Dynamic range in the analog domain Resistor noise Amplifier noise Maximum signal levels Tow-Thomas Biquad noise example Implications on power dissipation EECS 247 Lecture 4: Dynamic Range

More information

Cascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University

Cascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University Cascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University Bruce A. Wooley - 1 - Copyright 2005, Stanford University Outline Oversampling modulators for A-to-D conversion

More information

EE247 Lecture 11. Switched-Capacitor Filters (continued) Effect of non-idealities Bilinear switched-capacitor filters Filter design summary

EE247 Lecture 11. Switched-Capacitor Filters (continued) Effect of non-idealities Bilinear switched-capacitor filters Filter design summary EE47 Lecture 11 Switched-Capacitor Filters (continued) Effect of non-idealities Bilinear switched-capacitor filters Filter design summary Comparison of various filter topologies Data Converters EECS 47

More information

Lecture Outline. ESE 531: Digital Signal Processing. Anti-Aliasing Filter with ADC ADC. Oversampled ADC. Oversampled ADC

Lecture Outline. ESE 531: Digital Signal Processing. Anti-Aliasing Filter with ADC ADC. Oversampled ADC. Oversampled ADC Lecture Outline ESE 531: Digital Signal Processing Lec 12: February 21st, 2017 Data Converters, Noise Shaping (con t)! Data Converters " Anti-aliasing " ADC " Quantization "! Noise Shaping 2 Anti-Aliasing

More information

EE247 Lecture 11. EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics 2009 H. K. Page 1. Typical Sampling Process C.T. S.D. D.T.

EE247 Lecture 11. EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics 2009 H. K. Page 1. Typical Sampling Process C.T. S.D. D.T. EE247 Lecture Data converters Sampling, aliasing, reconstruction Amplitude quantization Static converter error sources Offset Full-scale error Differential non-linearity (DNL) Integral non-linearity (INL)

More information

Lecture 10, ANIK. Data converters 2

Lecture 10, ANIK. Data converters 2 Lecture, ANIK Data converters 2 What did we do last time? Data converter fundamentals Quantization noise Signal-to-noise ratio ADC and DAC architectures Overview, since literature is more useful explaining

More information

EE247 Lecture 9. Sampling Sine Waves Frequency Spectrum

EE247 Lecture 9. Sampling Sine Waves Frequency Spectrum EE247 Lecture 9 Switched-capacitor filters (continued) Example of anti-aliasing prefilter for S.. filters Switched-capacitor network electronic noise Switched-capacitor integrators DDI integrators LDI

More information

Data Converters. Oversampling and Low-Order ΔΣ Modulators. Overview. Speed vs. accuracy of ADCs. Principle of oversampling. Principle of oversampling

Data Converters. Oversampling and Low-Order ΔΣ Modulators. Overview. Speed vs. accuracy of ADCs. Principle of oversampling. Principle of oversampling Data Converters Overview Principle of oversampling Oversampling and Low-Order ΔΣ Modulators Noise shaping st -order ΔΣ modulator nd -order ΔΣ modulator Pietro Andreani Dept. of Electrical and Information

More information

Data Conversion Techniques (DAT115)

Data Conversion Techniques (DAT115) Data Conversion Techniques (DAT115) Hand in Report Second Order Sigma Delta Modulator with Interleaving Scheme Group 14N Remzi Yagiz Mungan, Christoffer Holmström [ 1 20 ] Contents 1. Task Description...

More information

Oversampling Data Converters Tuesday, March 15th, 9:15 11:40

Oversampling Data Converters Tuesday, March 15th, 9:15 11:40 Oversampling Data Converters Tuesday, March 15th, 9:15 11:40 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Last time and today, Tuesday 15th of March:

More information

System-on-Chip. Oversampling and Low-Order ΔΣ Modulators. Overview. Principle of oversampling. Speed vs. accuracy of ADCs. Principle of oversampling

System-on-Chip. Oversampling and Low-Order ΔΣ Modulators. Overview. Principle of oversampling. Speed vs. accuracy of ADCs. Principle of oversampling System-on-Chip Overview Principle of oversampling Oversampling and Low-Order ΔΣ Modulators Noise shaping st -order ΣΔ modulator nd -order ΣΔ modulator Pietro Andreani Dept. of Electrical and Information

More information

Outline. Noise and Distortion. Noise basics Component and system noise Distortion INF4420. Jørgen Andreas Michaelsen Spring / 45 2 / 45

Outline. Noise and Distortion. Noise basics Component and system noise Distortion INF4420. Jørgen Andreas Michaelsen Spring / 45 2 / 45 INF440 Noise and Distortion Jørgen Andreas Michaelsen Spring 013 1 / 45 Outline Noise basics Component and system noise Distortion Spring 013 Noise and distortion / 45 Introduction We have already considered

More information

Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009

Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009 Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009 Introduction The first thing in design an ADC is select architecture of ADC that is depend on parameters like bandwidth, resolution,

More information

Summary of Last Lecture

Summary of Last Lecture EE47 Lecture 7 DAC Converters (continued) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Sampling switch

More information

Data Converter Topics. Suggested Reference Texts

Data Converter Topics. Suggested Reference Texts Data Converter Topics Basic Operation of Data Converters Uniform sampling and reconstruction Uniform amplitude quantization Characterization and Testing Common ADC/DAC Architectures Selected Topics in

More information

Design of Bandpass Delta-Sigma Modulators: Avoiding Common Mistakes

Design of Bandpass Delta-Sigma Modulators: Avoiding Common Mistakes Design of Bandpass Delta-Sigma Modulators: Avoiding Common Mistakes R. Jacob Baker and Vishal Saxena Department of Electrical and Computer Engineering Boise State University 1910 University Dr., ET 201

More information

EE247 Lecture 11. Example: Switched-capacitor filters in CODEC integrated circuits. Switched-capacitor filter design summary

EE247 Lecture 11. Example: Switched-capacitor filters in CODEC integrated circuits. Switched-capacitor filter design summary EE47 Lecture 11 Filters (continued) Example: Switched-capacitor filters in CODEC integrated circuits Switched-capacitor filter design summary Comparison of various filter topologies New Topic: Data Converters

More information

The need for Data Converters

The need for Data Converters The need for Data Converters ANALOG SIGNAL (Speech, Images, Sensors, Radar, etc.) PRE-PROCESSING (Filtering and analog to digital conversion) DIGITAL PROCESSOR (Microprocessor) POST-PROCESSING (Digital

More information

Lecture 9, ANIK. Data converters 1

Lecture 9, ANIK. Data converters 1 Lecture 9, ANIK Data converters 1 What did we do last time? Noise and distortion Understanding the simplest circuit noise Understanding some of the sources of distortion 502 of 530 What will we do today?

More information

ADVANCES in VLSI technology result in manufacturing

ADVANCES in VLSI technology result in manufacturing INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2013, VOL. 59, NO. 1, PP. 99 104 Manuscript received January 8, 2013; revised March, 2013. DOI: 10.2478/eletel-2013-0012 Rapid Prototyping of Third-Order

More information

Chapter 2: Digitization of Sound

Chapter 2: Digitization of Sound Chapter 2: Digitization of Sound Acoustics pressure waves are converted to electrical signals by use of a microphone. The output signal from the microphone is an analog signal, i.e., a continuous-valued

More information

6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers

6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers 6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Bandwidth Constraints

More information

INTRODUCTION TO DELTA-SIGMA ADCS

INTRODUCTION TO DELTA-SIGMA ADCS ECE37 Advanced Analog Circuits Lecture INTRODUCTION TO DELTA-SIGMA ADCS Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen understanding of CMOS

More information

Enhancing Analog Signal Generation by Digital Channel Using Pulse-Width Modulation

Enhancing Analog Signal Generation by Digital Channel Using Pulse-Width Modulation Enhancing Analog Signal Generation by Digital Channel Using Pulse-Width Modulation Angelo Zucchetti Advantest angelo.zucchetti@advantest.com Introduction Presented in this article is a technique for generating

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering And Computer Sciences MULTIFREQUENCY CELL IMPEDENCE MEASUREMENT

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering And Computer Sciences MULTIFREQUENCY CELL IMPEDENCE MEASUREMENT UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering And Computer Sciences MULTIFREQUENCY CELL IMPEDENCE MEASUREMENT EE247 Term Project Eddie Ng Mounir Bohsali Professor

More information

Design of Pipeline Analog to Digital Converter

Design of Pipeline Analog to Digital Converter Design of Pipeline Analog to Digital Converter Vivek Tripathi, Chandrajit Debnath, Rakesh Malik STMicroelectronics The pipeline analog-to-digital converter (ADC) architecture is the most popular topology

More information

INF4420 Switched capacitor circuits Outline

INF4420 Switched capacitor circuits Outline INF4420 Switched capacitor circuits Spring 2012 1 / 54 Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators 2 / 54 Introduction Discrete time analog

More information

EE247 Lecture 16. EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs 2009 Page 1

EE247 Lecture 16. EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs 2009 Page 1 EE47 Lecture 6 D/A Converters (continued) Self calibration techniques Current copiers (last lecture) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations

More information

A 2.5 V 109 db DR ADC for Audio Application

A 2.5 V 109 db DR ADC for Audio Application 276 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.4, DECEMBER, 2010 A 2.5 V 109 db DR ADC for Audio Application Gwangyol Noh and Gil-Cho Ahn Abstract A 2.5 V feed-forward second-order deltasigma

More information

Multirate DSP, part 3: ADC oversampling

Multirate DSP, part 3: ADC oversampling Multirate DSP, part 3: ADC oversampling Li Tan - May 04, 2008 Order this book today at www.elsevierdirect.com or by calling 1-800-545-2522 and receive an additional 20% discount. Use promotion code 92562

More information

EE247 Lecture 11. Switched-Capacitor Filters (continued) Effect of non-idealities Bilinear switched-capacitor filters Filter design summary

EE247 Lecture 11. Switched-Capacitor Filters (continued) Effect of non-idealities Bilinear switched-capacitor filters Filter design summary EE247 Lecture 11 Switched-Capacitor Filters (continued) Effect of non-idealities Bilinear switched-capacitor filters Filter design summary Comparison of various filter topologies Data Converters EECS 247

More information

Administrative. No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed.

Administrative. No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed. Administrative No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page EE247 Lecture 2 ADC Converters Sampling (continued)

More information

Quick View. Analog input time. Oversampling & pulse density modulation fs (sampling rate) >> fn (Nyquist rate)

Quick View. Analog input time. Oversampling & pulse density modulation fs (sampling rate) >> fn (Nyquist rate) SigmaDelta ADC Quick View Analog input time Oversampling & pulse density modulation sampling rate >> fn Nyquist rate One bit digital output Higher input > more 's Lower input > more 's Oversampling ratio

More information

Understanding Delta-Sigma Data Converters

Understanding Delta-Sigma Data Converters Understanding Delta-Sigma Data Converters Richard Schreier Analog Devices, Inc. Gabor C. Temes Oregon State University OlEEE IEEE Press iwiley- INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION Foreword

More information

Telecommunication Electronics

Telecommunication Electronics Politecnico di Torino ICT School Telecommunication Electronics C5 - Special A/D converters» Logarithmic conversion» Approximation, A and µ laws» Differential converters» Oversampling, noise shaping Logarithmic

More information

Appendix A Comparison of ADC Architectures

Appendix A Comparison of ADC Architectures Appendix A Comparison of ADC Architectures A comparison of continuous-time delta-sigma (CT ), pipeline, and timeinterleaved (TI) SAR ADCs which target wide signal bandwidths (greater than 100 MHz) and

More information

NOISE IN SC CIRCUITS

NOISE IN SC CIRCUITS ECE37 Advanced Analog Circuits Lecture 0 NOISE IN SC CIRCUITS Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen Understanding of CMOS analog circuit

More information

RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE

RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE Mehdi Taghizadeh and Sirus Sadughi Department of Electrical Engineering, Science and Research Branch,

More information

Pipeline vs. Sigma Delta ADC for Communications Applications

Pipeline vs. Sigma Delta ADC for Communications Applications Pipeline vs. Sigma Delta ADC for Communications Applications Noel O Riordan, Mixed-Signal IP Group, S3 Semiconductors noel.oriordan@s3group.com Introduction The Analog-to-Digital Converter (ADC) is a key

More information

CONTINUOUS-TIME (CT) ΔΣ modulators have gained

CONTINUOUS-TIME (CT) ΔΣ modulators have gained 530 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 56, NO. 7, JULY 009 DT Modeling of Clock Phase-Noise Effects in LP CT ΔΣ ADCs With RZ Feedback Martin Anderson, Member, IEEE, and

More information

INF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen

INF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen INF4420 Switched capacitor circuits Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators

More information

Analog-to-Digital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999

Analog-to-Digital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999 Analog-to-Digital Converter Survey & Analysis Update: July 16,1999 References: 1. R.H. Walden, Analog-to-digital converter survey and analysis, IEEE Journal on Selected Areas in Communications, vol. 17,

More information

SIGMA-DELTA CONVERTER

SIGMA-DELTA CONVERTER SIGMA-DELTA CONVERTER (1995: Pacífico R. Concetti Western A. Geophysical-Argentina) The Sigma-Delta A/D Converter is not new in electronic engineering since it has been previously used as part of many

More information

LOW SAMPLING RATE OPERATION FOR BURR-BROWN

LOW SAMPLING RATE OPERATION FOR BURR-BROWN LOW SAMPLING RATE OPERATION FOR BURR-BROWN TM AUDIO DATA CONVERTERS AND CODECS By Robert Martin and Hajime Kawai PURPOSE This application bulletin describes the operation and performance of Burr-Brown

More information

Advanced AD/DA converters. ΔΣ DACs. Overview. Motivations. System overview. Why ΔΣ DACs

Advanced AD/DA converters. ΔΣ DACs. Overview. Motivations. System overview. Why ΔΣ DACs Advanced AD/DA converters Overview Why ΔΣ DACs ΔΣ DACs Architectures for ΔΣ DACs filters Smoothing filters Pietro Andreani Dept. of Electrical and Information Technology Lund University, Sweden Advanced

More information

Electronics A/D and D/A converters

Electronics A/D and D/A converters Electronics A/D and D/A converters Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED December 1, 2014 1 / 26 Introduction The world is analog, signal processing nowadays is

More information

EE247 Lecture 27 Today:

EE247 Lecture 27 Today: EE247 Lecture 27 Today: ΣΔ Modulator (continued) Examples of systems utilizing analog-digital interface circuitry Acknowledgements EECS 247 Lecture 27: Oversampled ADCs Cont'd & Final Remarks 2005 H. K.

More information

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/25

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/25 Gábor C. Temes School of Electrical Engineering and Computer Science Oregon State University temes@ece.orst.edu 1/25 Noise Intrinsic (inherent) noise: generated by random physical effects in the devices.

More information

The Real World is Analog ADC are necessary to convert the real world signals (analog) into the digital form for easy processing. Digital Processing

The Real World is Analog ADC are necessary to convert the real world signals (analog) into the digital form for easy processing. Digital Processing Data Converters The Real World is Analog ADC are necessary to convert the real world signals (analog) into the digital form for easy processing ADC Digital Processing (Computer, DSP...) DAC Real World:

More information

Design Examples. MEAD March Richard Schreier. ANALOG DEVICES R. SCHREIER ANALOG DEVICES, INC.

Design Examples. MEAD March Richard Schreier. ANALOG DEVICES R. SCHREIER ANALOG DEVICES, INC. Design Examples MEAD March 008 Richard Schreier Richard.Schreier@analog.com ANALOG DEVICES Catalog nd -Order Lowpass Architecture: Single-bit, switched-capacitor Application: General-purpose, low-frequency

More information

Summary Last Lecture

Summary Last Lecture EE247 Lecture 23 Converters Techniques to reduce flash complexity Interpolating (continued) Folding Multi-Step s Two-Step flash Pipelined s EECS 247 Lecture 23: Data Converters 26 H.K. Page 1 Summary Last

More information

AN ABSTRACT OF THE THESIS OF. Title: Effects and Compensation of the Analog Integrator Nonidealities in Dual- GAL- C. Temes

AN ABSTRACT OF THE THESIS OF. Title: Effects and Compensation of the Analog Integrator Nonidealities in Dual- GAL- C. Temes AN ABSTRACT OF THE THESIS OF Yaohua Yang for the degree of Master of Science in Electrical & Computer Engineering presented on February 20, 1993. Title: Effects and Compensation of the Analog Integrator

More information

Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies

Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies A. Pena Perez, V.R. Gonzalez- Diaz, and F. Maloberti, ΣΔ Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies, IEEE Proceeding of Latin American Symposium on Circuits and Systems, Feb.

More information

National Instruments Flex II ADC Technology The Flexible Resolution Technology inside the NI PXI-5922 Digitizer

National Instruments Flex II ADC Technology The Flexible Resolution Technology inside the NI PXI-5922 Digitizer National Instruments Flex II ADC Technology The Flexible Resolution Technology inside the NI PXI-5922 Digitizer Kaustubh Wagle and Niels Knudsen National Instruments, Austin, TX Abstract Single-bit delta-sigma

More information

Design And Simulation Of First Order Sigma Delta ADC In 0.13um CMOS Technology Jaydip H. Chaudhari PG Student L. C. Institute of Technology, Bhandu

Design And Simulation Of First Order Sigma Delta ADC In 0.13um CMOS Technology Jaydip H. Chaudhari PG Student L. C. Institute of Technology, Bhandu Design And Simulation Of First Order Sigma Delta ADC In 0.13um CMOS Technology Jaydip H. Chaudhari PG Student L. C. Institute of Technology, Bhandu Gireeja D. Amin Assistant Professor L. C. Institute of

More information

Chapter 2 DDSM and Applications

Chapter 2 DDSM and Applications Chapter DDSM and Applications. Principles of Delta-Sigma Modulation In order to explain the concept of noise shaping in detail, we start with a stand-alone quantizer (see Fig..a) with a small number of

More information

Choosing the Best ADC Architecture for Your Application Part 3:

Choosing the Best ADC Architecture for Your Application Part 3: Choosing the Best ADC Architecture for Your Application Part 3: Hello, my name is Luis Chioye, I am an Applications Engineer with the Texas Instruments Precision Data Converters team. And I am Ryan Callaway,

More information

A 98dB 3.3V 28mW-per-channel multibit audio DAC in a standard 0.35µm CMOS technology

A 98dB 3.3V 28mW-per-channel multibit audio DAC in a standard 0.35µm CMOS technology A 98dB 3.3V 28mW-per-channel multibit audio DAC in a standard 0.35µm CMOS technology M. Annovazzi, V. Colonna, G. Gandolfi, STMicroelectronics Via Tolomeo, 2000 Cornaredo (MI), Italy vittorio.colonna@st.com

More information

Lab.3. Tutorial : (draft) Introduction to CODECs

Lab.3. Tutorial : (draft) Introduction to CODECs Lab.3. Tutorial : (draft) Introduction to CODECs Fig. Basic digital signal processing system Definition A codec is a device or computer program capable of encoding or decoding a digital data stream or

More information

Active Filter Design Techniques

Active Filter Design Techniques Active Filter Design Techniques 16.1 Introduction What is a filter? A filter is a device that passes electric signals at certain frequencies or frequency ranges while preventing the passage of others.

More information

EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design 2009 Page 1. EE247 Lecture 18

EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design 2009 Page 1. EE247 Lecture 18 EE247 Lecture 8 ADC Converters Sampling (continued) Bottom-plate switching Track & hold T/H circuits T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation T/H

More information

Laboratory Manual 2, MSPS. High-Level System Design

Laboratory Manual 2, MSPS. High-Level System Design No Rev Date Repo Page 0002 A 2011-09-07 MSPS 1 of 16 Title High-Level System Design File MSPS_0002_LM_matlabSystem_A.odt Type EX -- Laboratory Manual 2, Area MSPS ES : docs : courses : msps Created Per

More information

Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators Ahmed Gharbiya and David A. Johns

Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators Ahmed Gharbiya and David A. Johns 1224 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 12, DECEMBER 2008 Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators Ahmed Gharbiya and David A.

More information

EE 230 Lecture 39. Data Converters. Time and Amplitude Quantization

EE 230 Lecture 39. Data Converters. Time and Amplitude Quantization EE 230 Lecture 39 Data Converters Time and Amplitude Quantization Review from Last Time: Time Quantization How often must a signal be sampled so that enough information about the original signal is available

More information

A/D Conversion and Filtering for Ultra Low Power Radios. Dejan Radjen Yasser Sherazi. Advanced Digital IC Design. Contents. Why is this important?

A/D Conversion and Filtering for Ultra Low Power Radios. Dejan Radjen Yasser Sherazi. Advanced Digital IC Design. Contents. Why is this important? 1 Advanced Digital IC Design A/D Conversion and Filtering for Ultra Low Power Radios Dejan Radjen Yasser Sherazi Contents A/D Conversion A/D Converters Introduction ΔΣ modulator for Ultra Low Power Radios

More information

Amplitude Quantization

Amplitude Quantization Amplitude Quantization Amplitude quantization Quantization noise Static ADC performance measures Offset Gain INL DNL ADC Testing Code boundary servo Histogram testing EECS Lecture : Amplitude Quantization

More information

Data Converters. Specifications for Data Converters. Overview. Testing and characterization. Conditions of operation

Data Converters. Specifications for Data Converters. Overview. Testing and characterization. Conditions of operation Data Converters Overview Specifications for Data Converters Pietro Andreani Dept. of Electrical and Information Technology Lund University, Sweden Conditions of operation Type of converter Converter specifications

More information