EE247 Lecture 12. EE247 Lecture 12

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1 EE47 Lecture Administrative issues Midterm exam Oct. 9th. o You can only bring one 8x paper with notes o No books, class handouts, calculators, computers, cell phones... Final exam date in process of changingfeedback so far from students the only conflicting other final is EE4- if you have any other finals last chance to announce EECS 47 Lecture : Data Converters 4 H.K. Page Data Converters EE47 Lecture Summary last lecture ADC & DAC testing DNL & INL Code boundry servo test Histogram testing Spectral testing EECS 47 Lecture : Data Converters 4 H.K. Page

2 A/D & D/A Conversion A/D Conversion D/A Conversion EECS 47 Lecture : Data Converters 4 H.K. Page 3 Classification f s > f max Nyquist Sampling "Nyquist Converters" Actually always slightly oversampled f s >> f max Oversampling "Oversampled Converters" Anti-alias filtering is often trivial Oversampling is also used to reduce quantization noise, see later in the course... f s < f max Undersampling (Subsampling) EECS 47 Lecture : Data Converters 4 H.K. Page 4

3 Ideal ADC ("Quantizer") Quantization step (= LSB) E.g. N = 3 Bits Full-scale input range: -.5 ( N -.5) Digital Output Code ADC characteristics ideal converter A/D Characteristics [] Quantization error: bounded by / + / for inputs within full-scale range V in ADC Model D + out ε q (V in ) Quantization error [LSB] ADC Input Voltage [/ ] EECS 47 Lecture : Data Converters 4 H.K. Page 5 ADC Signal-to-Quantization Noise Ratio If certain conditions are met, quantization error can be viewed as being "random", and is often referred to as noise In this case, we can define a peak signal-to-quantization noise ratio, SQNR, for sinusoidal inputs: N SQNR = =.5 = 6.N +.76 db N e.g. N SQNR 8 5 db 74 db 6 98 db db Actual converters do not quite achieve this performance due to other errors, including Electronic noise Deviations from the ideal quantization levels EECS 47 Lecture : Data Converters 4 H.K. Page 6

4 Static Converter Errors Deviations of characteristic from ideal Offset Full-scale error Differential nonlinearity, DNL Integral nonlinearity, INL EECS 47 Lecture : Data Converters 4 H.K. Page 7 Offset Error ADC DAC Ref: Understanding Data Converters, Texas Instruments Application Report SLAA3, Mixed-Signal Products, 995. EECS 47 Lecture : Data Converters 4 H.K. Page 8

5 ADC Actual full scale point Full Scale Error Ideal full scale point DAC Ideal full scale point Full scale error Full scale error Actual full scale point EECS 47 Lecture : Data Converters 4 H.K. Page 9 Offset and Full Scale Errors Alternative Specification in % Full Scale = % * (LSB value)/ N Gain error can be extracted from offset & full-scale error Non-trivial to build a converter with extremely good offset/full-scale specs Typically offset/full-scale is most easily compensated by the digital pre/post-processor More interesting: Linearity DNL, INL EECS 47 Lecture : Data Converters 4 H.K. Page

6 Offset and Full-Scale Error Note: For further measurements (DNL, INL) connecting the endpoints & deriving ideal codes based on the non-ideal endpoints elliminates offset and fullscale error Digital Output Code ADC characteristics ideal converter Offset error Full-scale error ADC Input Voltage [LSB] EECS 47 Lecture : Data Converters 4 H.K. Page ADC Differential Nonlinearity DNL = deviation of code width from (LSB) ADC characteristics ideal converter -.4 LSB DNL error Endpoints connected Ideal characterisctics derived DNL measured Digital Output Code LSB DNL error +.4 LSB DNL error ADC Input Voltage [/D] EECS 47 Lecture : Data Converters 4 H.K. Page

7 ADC Differential Nonlinearity Examples 8 ADC characteristics ideal converter 8 ADC characteristics ideal converter 7 7 Digital Output Code Missing code (+.5/- LSB DNL) Digital Output Code Non-monotonic (> LSB DNL) ADC Input Voltage [/D] ADC Input Voltage [/D] EECS 47 Lecture : Data Converters 4 H.K. Page 3 DAC Differential Nonlinearity EECS 47 Lecture : Data Converters 4 H.K. Page 4

8 Impact of DNL on Performance Same as a somewhat larger quantization error, consequently degrades SQNR How much later in the course... People sometimes speak of "DNL noise", i.e. "additional quantization noise due to DNL" EECS 47 Lecture : Data Converters 4 H.K. Page 5 ADC Integral Nonlinearity INL = deviation of code transition from its ideal location A straight line through the endpoints is usually used as reference, i.e. offset and full scale errors are ignored in INL calculation Ideal converter steps is found for the endpoint line, then INL is measured Digital Output Code LSB INL Note that INL errors can be much larger than DNL errors and vice-versa ADC Input Voltage [/D] EECS 47 Lecture : Data Converters 4 H.K. Page 6

9 DAC Integral Nonlinearity EECS 47 Lecture : Data Converters 4 H.K. Page 7 DAC DNL and INL * Ref: Understanding Data Converters, Texas Instruments Application Report SLAA3, Mixed-Signal Products, 995. EECS 47 Lecture : Data Converters 4 H.K. Page 8

10 Example: INL & DNL Large INL & Small DNL Large DNL & Small INL EECS 47 Lecture : Data Converters 4 H.K. Page 9 Monotonicity Monotonicity guaranteed if INL =.5 LSB The best fit straight line is taken as the reference for determining the INL. This implies DNL = LSB Note: these conditions are sufficient but not necessary for monotonicity EECS 47 Lecture : Data Converters 4 H.K. Page

11 How to measure DNL/INL? DAC: "trivial", apply codes and use a good voltmeter to measure output ADC Need to find "decision levels", i.e. input voltages at all code boundaries One way: Adjust voltage source to find exact code trip points "code boundary servo" More versatile: Histogram testing Apply a signal with known distibution and analyze digital code distribution at ADC output EECS 47 Lecture : Data Converters 4 H.K. Page Code Boundary Servo Input Digital Code A Digital Comp. B A<B A B i C R ADC Input V REF f S ADC C i ADC Output EECS 47 Lecture : Data Converters 4 H.K. Page

12 Code Boundary Servo i and i are small, and C is large, so the ADC analog input moves a small fraction of an LSB each sampling period For a code input of, the ADC analog input settles to the code boundary shown ADC Digital Output V REF ADC Analog Input V REF EECS 47 Lecture : Data Converters 4 H.K. Page 3 Code Boundary Servo Input Digital Code A A<B i C Good DVM V REF f S Digital Comp. B A B R ADC C i ADC Output EECS 47 Lecture : Data Converters 4 H.K. Page 4

13 Code Boundary Servo A very good digital voltmeter (DVM) measures the analog input voltage corresponding to the desired code boundary DVMs have some interesting properties They can have very high resolutions (8½ decimal digit meters are inexpensive) To achieve stable readings, DVMs average voltage measurements over multiple 6Hz ac line cycles to filter out pickup in the measurement loop EECS 47 Lecture : Data Converters 4 H.K. Page 5 Code Boundary Servo ADCs of all kinds are notorious for kicking back high-frequency, signal-dependent glitches to their analog inputs R Good DVM V REF f S ADC A magnified view of an analog input glitch follows C EECS 47 Lecture : Data Converters 4 H.K. Page 6

14 Code Boundary Servo Just before the input is sampled and conversion starts, the analog input is pretty quiet As the converter begins to quantize the signal, it kicks back charge analog input start of conversion /f S time EECS 47 Lecture : Data Converters 4 H.K. Page 7 Code Boundary Servo The difference between what the ADC measures and what the DVM measures is not ADC INL, it s error in the INL measurement analog input DVM measures the average input including the glitch How do we control this error? ADC converts this voltage /f S time EECS 47 Lecture : Data Converters 4 H.K. Page 8

15 Code Boundary Servo A large C fixes this Good DVM At the expense of longer measurement time V REF f S R ADC C EECS 47 Lecture : Data Converters 4 H.K. Page 9 Histogram Testing Code boundary measurements are slow Long testing time May miss dynamic errors Histogram testing Quantize input with known pdf (e.g. ramp or sinusoid) Derive INL and DNL from deviation of measured pdf from expected result EECS 47 Lecture : Data Converters 4 H.K. Page 3

16 Histogram Test Setup V REF Ramp V REF ADC PC Time DNL follows directly from total number of occurrences of each code EECS 47 Lecture : Data Converters 4 H.K. Page 3 A/D Histogram Test Using Ramp Signal Example: Ramp slope: µv/µsec LSB =mv Each ADC code msec f s =khz T s =µsec n = samples/code Digital Output ADC Input/Output Analog input n/f s Ramp Time EECS 47 Lecture : Data Converters 4 H.K. Page 3

17 A/D Histogram Test Using Ramp Signal Example: Ramp slope: µv/usec LSB =mv Each ADC code msec Digital Output ADC Input/Output f s =khz T s =µsec n = samples/code n/f s Time Ramp Analog input # of Samples Per code EECS 47 Lecture : Data Converters 4 H.K. Page 33 Measuring DNL Error Ramp speed is adjusted to provide e.g. an average of outputs of each ADC code (for / LSB resolution) Ramps can be quite slow for high resolution ADCs Example: 6bit ADC & (65,536 codes)( conversions/code), conversions/sec = 65.6 sec EECS 47 Lecture : Data Converters 4 H.K. Page 34

18 Ramp Histogram Ideal 3 Bit ADC 7 ADC characteristics ideal converter Digital Output Code Code Count ADC Input Voltage [/D] ADC output code EECS 47 Lecture : Data Converters 4 H.K. Page 35 Ramp Histogram Example 3 Bit ADC 7 ADC characteristics ideal converter 8 Digital Output Code LSB DNL +.4 LSB INL Code Count LSB DNL ADC Input Voltage [/D] ADC output code EECS 47 Lecture : Data Converters 4 H.K. Page 36

19 Example 3 Bit ADC DNL Extracted from Histogram Remove over-range bins ( and full-scale) Compute average count/bin Code Count, End bins removed ADC output code EECS 47 Lecture : Data Converters 4 H.K. Page 37 Example 3 Bit ADC DNL Extracted from Histogram Scale:. divide by average count. subtract (ideal bins have exactly the average count, which, after normalization, is ) DNL = Counts / Mean(Counts) Result is DNL ADC output code EECS 47 Lecture : Data Converters 4 H.K. Page 38

20 Example 3 Bit ADC INL Extracted from Histogram DNL width of all codes (DNL + LSB) DNL used to reconstruct the exact converter characteristic (having measured only the histogram) INL is the deviation from a straight line through the end points Reconstructed Characteristic ADC Input Voltage EECS 47 Lecture : Data Converters 4 H.K. Page 39 Example 3 Bit ADC DNL & INL Extracted from Histogram DNL and INL of 3 Bit converter (from histogram testing) Digital Output Code ADC characteristics ideal converter -.4 LSB DNL +.4 LSB INL +.4 LSB DNL DNL [LSB] INL [LSB] avg=-.9e-7, std.dev=.5, range=.8 bin # avg=., std.dev=., range= ADC Input Voltage [/D] bin # EECS 47 Lecture : Data Converters 4 H.K. Page 4

21 ADC Histogram Testing Sinusoidal Inputs Precise ramps not readily available Solution: use sinusoidal test signal 5 5 ADC Output- Raw Histogram Problem: ideal histogram is not flat but has bath-tub shape EECS 47 Lecture : Data Converters 4 H.K. Page 4 A/D Histogram Test Using Sinusoidal Signals At sinusoid midpoint crossings: dv/dt max. least # of samples At sinusoid amplitude peaks: dv/dt min. highest # of samples Digital Output Time ADC Input/Output Analog input Sinusoid # of Samples Per code EECS 47 Lecture : Data Converters 4 H.K. Page 4

22 After Correction for Sinusoidal pdf.4 x -3 Linearized Histogram EECS 47 Lecture : Data Converters 4 H.K. Page 43 Resulting DNL and INL.5 DNL = +.3 / - LSB, missing code if (DNL>-.9) DNL [LSB] code INL = +.7 / -.69 LSB INL [LSB] code EECS 47 Lecture : Data Converters 4 H.K. Page 44

23 Correction for Sinusoidal pdf References: [] M. V. Bossche, J. Schoukens, and J. Renneboog, Dynamic Testing and Diagnostics of A/D Converters, IEEE Transactions on Circuits and Systems, vol. CAS-33, no. 8, Aug [] IEEE Standard 57 Is it necessary to know the exact amplitude and offset of sine input? No! EECS 47 Lecture : Data Converters 4 H.K. Page 45 DNL/INL Code function [dnl,inl] = dnl_inl_sin(y); %DNL_INL_SIN % dnl and inl ADC output % input y contains the ADC output % vector obtained from quantizing a % sinusoid % Boris Murmann, Aug % Bernhard Boser, Sept % histogram boundaries minbin=min(y); maxbin=max(y); % histogram h = hist(y, minbin:maxbin); % cumulative histogram ch = cumsum(h); % transition levels T = -cos(pi*ch/sum(h)); % linearized histogram hlin = T(:end) - T(:end-); % truncate at least first and last % bin, more if input did not clip ADC trunc=; hlin_trunc = hlin(+trunc:end-trunc); % calculate lsb size and dnl lsb= sum(hlin_trunc) / (length(hlin_trunc)); dnl= [ hlin_trunc/lsb-]; misscodes = length(find(dnl<-.9)); % calculate inl inl= cumsum(dnl); EECS 47 Lecture : Data Converters 4 H.K. Page 46

24 DNL/INL Code Test % converter model B = 6; % bits range = ^(B-) - ; % thresholds (ideal converter) th = -range:range; % ideal thresholds th() = th()+.7; % error fs = e6; fx = 494e3 + pi; % try fs/! C = round( * ^B / (fs / fx)); t = :/fs:c/fx; x = (range+) * sin(*pi*fx.*t); y = adc(x, th) - ^(B-); hist(y, min(y):max(y)); DNL [LSB] INL [LSB] DNL = +.7 / -.7 LSB, missing codes (DNL<-.9) INL = +.76 / -.63 LSB code dnl_inl_sin(y); EECS 47 Lecture : Data Converters 4 H.K. Page 47 Limitations of Histogram Testing The histogram (as any ADC test, of course) characterizes one particular converter. Test many devices to get valid statistics. Histogram testing assumes monotonicity. E.g. code flips will not be detected. Dynamic sparkle codes produce only minor DNL/INL errors. E.g. 3, 3,, 3,, 4, 4, look at ADC output to detect. Noise not detected or improves DNL. E.g. 9, 9, 9,, 9, 9, 9,, 9,,,, Ref: B. Ginetti and P. Jespers, Reliability of Code Density Test for High Resolution ADCs, Electron. Lett., vol. 7, pp. 3-3, Nov. 99. EECS 47 Lecture : Data Converters 4 H.K. Page 48

25 Hiding Problems in the Noise INL 5 missing codes DNL "smeared out" by noise! Always look at both DNL/INL INL usually does not lie... [Source: David Robertson, Analog Devices] EECS 47 Lecture : Data Converters 4 H.K. Page 49 Why Additional Tests/Metrics? Static testing does not tell the full story E.g. no info about "noise" Frequency dependence (f s and f in )? In principle we can vary f s and f in when performing histogram tests Result of such sweeps is usually not very useful Hard to separate error sources, ambiguity Typically we use f s =f snom and f in << f s / for histogram tests For additional info Spectral testing EECS 47 Lecture : Data Converters 4 H.K. Page 5

26 Direct ADC-DAC Test Device Under Test (DUT) Signal Generator V in ADC DAC V out Specrum Analyzer Clock Generator Need DAC with much better performance compared to ADC under test Actually a good way to "get started"... EECS 47 Lecture : Data Converters 4 H.K. Page 5 DFT Test Device Under Test (DUT) Signal Generator V in ADC Data Acquisition System PC Clock Generator EECS 47 Lecture : Data Converters 4 H.K. Page 5

27 Analyzing ADC outputs via DFT x(t) x(k) An ideal, infinite resolution ADC would preserve ideal, single tone spectrum Deviations reveal ADC non-idealities EECS 47 Lecture : Data Converters 4 H.K. Page 53 Discrete Fourier Transform The DFT of a block of N time samples {x(k)} = {x(), x(), x(),,x(n-)} yields a set of N frequency bins {A m } = {A,A,A,,A N- } where: N- mn A m = S x n W N n= W N e jp/n m =,,,,N- EECS 47 Lecture : Data Converters 4 H.K. Page 54

28 DFT Properties DFT of N samples spaced T=/f s seconds: N frequency bins Bin m represents frequencies at m * f s /N [Hz] DFT frequency resolution: Proportional to /(NT) in [Hz/bin] EECS 47 Lecture : Data Converters 4 H.K. Page 55 DFT Magnitude Plots Because A m magnitudes are symmetric around f S /, it is redundant to plot A m s for m >N/ f s / f s Usually magnitudes are plotted on a log scale normalized so that a full scale sinewave of rms value a FS yields a peak bin of dbfs: A m (dbfs) = log A m a FS N/ EECS 47 Lecture : Data Converters 4 H.K. Page 56

29 Normalized DFT fs = e6; fx = 5e3; Afs = ; N = ; % time vector t = linspace(, (N-)/fs, N); % signal y = Afs * cos(*pi*fx*t); % spectrum s = * log(abs(fft(y)/n/afs*)); % drop redundant half s = s(:n/); % frequency vector (normalized to fs) f = (:length(s)-) / N; Magnitude [ dbfs ] Amplitude Time x Frequency [ f / f s ] EECS 47 Lecture : Data Converters 4 H.K. Page 57 Another Example Signal Amplitude Amplitude [ dbfs ] Time x Frequency [ f / s f ] This does not look like the spectrum of a sinusoid EECS 47 Lecture : Data Converters 4 H.K. Page 58

30 DFT Periodicity The DFT implicitly assumes that time sample blocks repeat every N samples With a non-integral number of periods periods within our observation window, the input yields a huge amplitude/phase discontinuity at the block boundary This energy spreads into all frequency bins as spectral leakage Spectral leakage can be eliminated by either An integral number of sinusoids in each block Windowing Signal Amplitude Signal Amplitude Time x Time x -4 EECS 47 Lecture : Data Converters 4 H.K. Page 59 Integral Number of Periods fs = e6; 5 % number of full cycles in test cycles = 67; % power of speeds up analysis % but make N/cycles non-integer! N = ^; % signal frequency fx = fs*cycles/n Amplitude [ db ] Frequency [ f / s f ] EECS 47 Lecture : Data Converters 4 H.K. Page 6