Analog ó Digital Conversion Sampled Data Acquisition Systems Discrete Sampling and Nyquist Digital to Analog Conversion Analog to Digital Conversion

Transcription

1 Today Analog ó Digital Conversion Sampled Data Acquisition Systems Discrete Sampling and Nyquist Digital to Analog Conversion Analog to Digital Conversion

2 Analog Digital Analog Beneits o digital systems Digital signals Immune to noise But, Analog signal can lose accuracy due to noise added to the desired signal Digital, i no bits are lost, guarantees 100% accuracy Improved storage density More powerul signal processing Digital system is only precise up to least signiicant bit Getting analog to digital is not noiseless Digital systems also introduce high requency noise

3 Key Elements o a Sampled Signal Processing System * An audio CD process would be an example o a system that has all o these components. (The recording artist is on the let ( Analog World ), the listener would be on the right. Some systems do not have all o these parts (e.g. a digital oscilloscope generally has no analog output.)

4 Key Elements o a Sampled Signal Processing System Interace to sampled system: Precision buer/gain ampliiers preserve the integrity o analog signal. Sometimes auto-scale input Anti-alias (low pass) ilter, typically with steep roll-o to ensure there are no signal components > sample /2. * *re: Analog Devices; Application Note AN-282

5 Key Elements o a Sampled Signal Processing System Converts the analog signal into a digital representation: Sample and Hold * is analog circuitry that ensures the ADC sees a stable, unchanging signal or the time required to accurately perorm the conversion. (allows or undersampling advanced topic in A/D) A/D can be any o a wide range o devices. More on this later. *re: Analog Devices; Application Note AN-282

6 Key Elements o a Sampled Signal Processing System A Digital Signal Processor (DSP) * is a microprocessor optimized or manipulating digitized analog signals: Perorm operations such as digital iltering and FFTs. Oten is also used or system control. Vector processors. Field programmable gate arrays (FPGA). *re: Analog Devices; Application Note AN-282

7 In many systems the signal is converted back into analog (sometimes ater short or long term storage in memory): Key Elements o a Sampled Signal Processing System Latch holds the digital data until the D/A can inish the conversion. This also allows the DSP processor to move on to other tasks. The D/A reverses the process used on the input side o the system. Some systems are made to aithully reproduce (CD players) or improve (noise cancelling headphones) on the original analog input. *re: Analog Devices; Application Note AN-282 *

8 Key Elements o a Sampled Signal Processing System The inal part o the process includes additional conditioning in the analog domain. Some D/As can produce inband glitches that must be removed at this stage. Analog iltering can be used to compensate or the discrete nature o the D/A, improving overall system idelity. * *re: Analog Devices; Application Note AN-282

9 Discrete Sampling at 5Hz Sample interval = 200mS Sample Rate = 5Hz Milliseconds F = 10Hz = 5Hz S

10 Discrete Sampling at 10Hz Sample interval = 100mS Sample Rate = 10Hz Milliseconds F = 10Hz = 10Hz S

11 Discrete Sampling at 20Hz F Milliseconds Sample interval = 50mS Sample Rate = 20Hz = Hz S = 10Hz 20

12 Discrete Sampling at 20Hz F Milliseconds Sample interval = 50mS Sample Rate = 20Hz = Hz S = 10Hz 20

13 Aliasing Original Signal Seconds Sample Freq. Sample Period F = 18Hz S = 20Hz TS = 50mS Sample_Rate_2.XLS

14 Aliasing in the Frequency Domain The requency o aliased signals is the dierence between and sum o the sampling requency S and signal being sampled, F. These aliased signals repeat around each integer multiple o the sampling requency. A L = and = + S F A H S F F = 8 S A L S AH Nyquist Frequency Hz

15 Aliasing in the Frequency Domain The requency o aliased signals is the dierence between and sum o the sampling requency S and signal being sampled, F. These aliased signals repeat around each integer multiple o the sampling requency. A L = and = + S F A H S F F = 4 S A L S AH Nyquist Frequency Hz

16 Aliasing in the Frequency Domain The requency o aliased signals is the dierence between and sum o the sampling requency S and signal being sampled, F. These aliased signals repeat around each integer multiple o the sampling requency. A L = and = + S F = A L 2 S F A H S S F AH Nyquist Frequency Hz

17 Aliasing in the Frequency Domain The requency o aliased signals is the dierence between and sum o the sampling requency S and signal being sampled, F. These aliased signals repeat around each integer multiple o the sampling requency. A L = and = + S F S F = 1.5 A L A H S S F Nyquist Frequency Hz

18 Digital to Analog Converter (DAC) Terminology Number o Bits, N: A DAC with N bits provides 2 N discrete output steps. Resolution, V: Also known as the step size, represents the minimum change in output voltage. Output Range: Dierence between the maximum and minimum output voltages, usually (2 N 1) V. Dynamic Range: Output Range divided by Resolution or Noise Voltage (whichever gives the smaller dynamic range). I noise is smaller than V, then dynamic range is 2 N 1.

19 In-Class Exercise A 10-bit DAC is set up to output a DC voltage rom -12V to +12V. Determine the resolution. The 10 bits produce a total o 2 10 = 1024 steps. The range is +12V ( 12V) = +24V. Thereore the resolution is 24V/1023 = V. 23.5mV/step!

20 One Approach to DAC: R-2R Ladder Circuit Vout 1kohm 1kohm 1kohm 2kohm 2kohm 2kohm 2kohm 2kohm V re Key = D Key = C Key = B Key = A 5V V = 5V out A B C D 2 4 What is V max? V max =V re *15/16=4.69V V min =0

21 2 nd Approach to DAC: Scaled Summing Junction DAC 50kohm Vout 1V 10kohm 20kohm 40kohm 80kohm Key = D Key = C Key = B Key = A This approach is the one we will implement in lab. V out A 50kΩ B 50kΩ C 50kΩ D 50kΩ = 1V kΩ 40kΩ 20kΩ 10kΩ A B C D = V What is Range? V max =0, V min =-10V*15/16=-9.38V Range=9.38V

22 Analog to Digital Converter (ADC) Terminology Number o Bits: An ADC with N bits divides the input range into 2 N discrete steps. For example, an 8 bit ADC can produce a total o 256 dierent output codes. Full Scale Input Range Dierence between the minimum and maximum input voltage that can be measured. Resolution: Quantization, also known as the step size, is the change in input voltage represented by each increment o the output. Oten reerred to as LSB (least signiicant bit) Dynamic Range: Input Range divided by resolution or noise. Typically equals 2 N 1, i noise is less than LSB.

23 ADC Accuracy QUANTIZATION ERROR Inherent accuracy (±1/2LSB, least signiicant bit) INTEGRAL NON-LINEARITY (INL) is a measure o the deviation o each individual code rom a line drawn rom zero scale or negative ull scale (1 2 LSB below the irst code transition) through positive ull scale (1 2 LSB above the last code transition). The deviation o any given code rom this straight line is measured rom the center o that code value. DIFFERENTIAL NON-LINEARITY (DNL) is the measure o the maximum deviation rom the ideal step size o 1 LSB. DNL is commonly measured at the rated clock requency with a ramp input. MISSING CODES are output codes that are skipped or never appear at the ADC outputs. These codes cannot be reached by any input value. OFFSET ERROR is the dierence between the ideal and actual LSB transition point. FULL SCALE ERROR is how ar the last code transition is rom the ideal 1.5 LSB below positive V_re (V_re is 2 N times step size) GAIN ERROR is number o LSB gained rom conversion rom lowest to highest output. It is a measure o the deviation o the ADC rom linear (gain = 1) conversion. See igure 9.44 in H&H page 615

24 Ideal ADC: Quantization Error Quantization Error FULL SCALE ERROR LSB 6 5 QUANTIZATION ERROR LSB Quantization error is the inherent deviation o the output rom a straight line. -Note last transition is 1.5 LSB rom V re (used to measure ull scale error)

25 Sampled System Errors - INL INL Error Integral Non-Linearity is the deviation o the output rom a straight line.

26 Sampled System Errors - DNL DNL Error DNL= LSB Dierential Non-Linearity is the maximum dierence between the expected stepsize (1 LSB) and that steps actually produced by the DAC.

27 Sampled System Errors - Oset Oset Error Oset Error is measured at

28 Sampled System Errors - Gain Gain Error Gain Error is measured at The oset error must be known to compute this value. (y=mx+b)

29 Sampled System Errors - Gain Gain Error LSB oset Gain Error is measured at The oset error must be known to compute this value. (y=mx+b)

30 Reerences 1. Paul Horowitz and Winield Hill (1989). The Art o Electronics, 2 nd Ed., Cambridge 2. Analog Devices, Fundamentals o Sampled Data Systems, accessed MAR Eunda, Engineering Fundamentals web site; accessed MAR National Semiconductor: accessed MAR