Analog Frequency Synthesizers: A Short Tutorial. IEEE Distinguished Lecture SSCS, Dallas Chapter

Transcription

1 Analog Frequency Synthesizers: A Short Tutorial IEEE Distinguished Lecture SSCS, Dallas Chapter Michael H. Perrott April 2013 Copyright 2013 by Michael H. Perrott All rights reserved.

2 What is a Phase-Locked Loop (PLL)? r r out(t) out(t) v(t) v(t) r Phase Detect Analog v(t) out(t) Loop Filter VCO de Bellescize Onde Electr, 1932 Voltage Controlled Oscillator (VCO): variable requency PLL: synchronizes VCO requency to input reerence VCO requency precisely tracks the reerence requency Virtually all communication and computation systems require PLLs 2

3 Analog Phase Detection r out(t) 1 reset 1 D Q D Q Reg error(t) phase error r out(t) error(t) r Phase Detect Analog Loop Filter out(t) VCO Pulse width is ormed according to phase dierence between two signals Average o pulsed waveorm is applied to VCO input 3

4 Phase Detector Characteristic r out(t) error(t) Phase Detector Signals Average o error(t) Phase Detector Characteristic phase error r Phase Detect Analog Loop Filter out(t) VCO Analog loop ilter extracts the average o the pulsed PD - Resulting PD characteristic is a linear unction o phase error 4

5 Integer-N Frequency Synthesizers r div(t) v(t) F out = N F re r div(t) Phase Detect Analog v(t) out(t) Loop Filter Divider VCO Sepe and Johnston US Patent (1968) Use digital counter structure to divide VCO requency - Constraint: must divide by integer values Use PLL to synchronize reerence and divider output Output requency is digitally controlled N 5

6 Fractional-N Frequency Synthesizers r div(t) v(t) F out = M.F F re r div(t) Phase Detect Analog v(t) out(t) Loop Filter Divider VCO N sd [k] Σ Δ Modulator N[k] M.F Dither divide value to achieve ractional divide values - PLL loop ilter smooths the resulting variations Very high requency resolution is achieved 6

7 The Issue o Quantization Noise r div(t) v(t) F out = M.F F re r div(t) Phase Detect Analog v(t) out(t) Loop Filter Divider VCO N sd [k] Σ Δ Modulator N[k] Dithering can be perormed such that noise is highpass shaped - Noise is attenuated by PLL iltering M.F Σ Δ Quantization Noise 7

8 Outline o Talk Integer-N synthesizers - Modeling o PLL blocks - System Level Modeling Transer unction analysis Phase Detect Analog Loop Filter Divider VCO Nonlinear behavior N Type I versus Type II - Noise Analysis Fractional-N synthesizers - Sigma-Delta Concepts - Noise Analysis - Quantization noise cancellation Phase Detect Σ Δ Modulator Analog Loop Filter Divider 8

9 Popular VCO Structures VCO Amp LC oscillator V out -R amp V in C L R p Ring oscillator V out V in -1 LC Oscillator: low phase noise, large area Ring Oscillator: easy to integrate, higher phase noise 9

10 Model or Voltage to Frequency Mapping o VCO VCO Amp LC oscillator V out -R amp V in C L R p F vco Ring oscillator V in -1 V out VCO Frequency c F out slope=k v v V bias Input Voltage v in 10

11 Model or Voltage to Phase Mapping o VCO Time-domain requency relationship (rom previous slide) Time-domain phase relationship Intuition o integral relationship between requency and phase: out(t) 1/F vco = α out(t) 1/F vco = α+ε 11

12 Frequency-Domain Model or VCO Time-domain relationship (rom previous slide) Corresponding requency-domain model Laplace-Domain Frequency-Domain v(t) out(t) v(t) 2πKv s Φ out (t) v(t) Kv j Φ out (t) VCO VCO VCO 12

13 Divider Implementation Counter N out(t) count value out div(t) out(t) div(t) Time-domain model - Frequency: N = 6 - Phase: 13

14 Frequency-Domain Model o Divider Time-domain relationship between VCO phase and divider output phase (rom previous slide) Corresponding requency-domain model (same as Laplace-domain) out(t) Divider div(t) Φ out (t) 1 N Φ div (t) Divider 14

15 Phase Detector (PD) XOR structure - Average value o error pulses corresponds to phase error - Loop ilter extracts the average value and eeds to VCO r div(t) r div(t)

16 XOR Phase Detector Characteristic π < Φ re Φ div < 0 0 < Φ re Φ div < π T/2 T/2 r r div(t) div(t) 1-1 W 1-1 W W = - Φ re Φ div π T/2 W = Φ re Φ div π T/2 avg{} gain = -2/π 1 gain = 2/π π π/2 0 π/2 π Φ re - Φ div -1 phase detector range = π 16

17 Frequency-Domain Model o XOR Phase Detector Assume phase dierence conined within 0 to radians - Phase detector characteristic looks like a constant gain element avg{} gain = -2/π 1 gain = 2/π π π/2 0 π/2 π Φ re - Φ div -1 Corresponding requency-domain model r PD Φ re (t) 2 π div(t) Φ div (t) PD gain 17

18 Loop Filter Consists o a lowpass ilter to extract average o phase detector error pulses Frequency-domain model Laplace-Domain Frequency-Domain Loop Filter v(t) H(s) VCO v(t) H(s) H() VCO v(t) First order example R 1 v(t) C 1 18

19 Overall Linearized PLL Frequency-Domain Model Combine models o individual components Laplace-Domain Model Φ re (t) XOR PD 2 π Loop Filter H(s) v(t) VCO 2πKv s Φ out (t) Φ div (t) Divider 1 N Frequency-Domain Model Φ re (t) XOR PD 2 π Loop Filter H() v(t) VCO Kv j Φ out (t) Φ div (t) Divider 1 N 19

20 Response o PLL to Divide Value Changes Φ re (t) XOR PD 2 π Loop Filter H() v(t) VCO Kv j Φ out (t) Φ div (t) Divider 1 N N+1 N t Change in output requency achieved by changing the divide value Classical approach provides no direct model o impact o divide value variations - Treat divide value variation as a perturbation to a linear system PLL responds according to closed loop transer unction 20

21 Response o an Actual PLL to Divide Value Change Example: Change divide value by one Synthesizer Response To Divider Step N (Divide Value) Output Frequency (GHz) Time (microseconds) - PLL behaves according to expected closed loop response! 21

22 What Happens with Large Divide Value Variations? PLL temporarily loses requency lock (cycle slipping occurs) N (Divide Value) Synthesizer Response To Divider Step Output Frequency (GHz) Time (microseconds) - Why does this happen? 22

23 Recall Phase Detector Characteristic avg{} gain = -2/π 1 gain = 2/π π π/2 0 π/2 π Φ re - Φ div -1 To simpliy modeling, we assumed that we always operated in a conined phase range (0 to ) - Led to a simple PD model Large perturbations knock us out o that conined phase range - PD behavior varies depending on the phase range it happens to be in 23

24 Cycle Slipping Consider the case where there is a requency oset between divider output and reerence - We know that phase dierence will accumulate r div(t) Resulting ramp in phase causes PD characteristic to be swept across its dierent regions (cycle slipping) avg{} gain = -2/π 1 gain = 2/π π π/2 0 π/2 π Φ re - Φ div -1 24

25 Impact o Cycle Slipping Loop ilter averages out phase detector output Severe cycle slipping causes phase detector to alternate between regions very quickly - Average value o XOR characteristic can be close to zero - PLL requency oscillates according to cycle slipping - In severe cases, PLL will not re-lock PLL has inite requency lock-in range! XOR DC characteristic 1 cycle slipping π π 3π nπ (n+2)π -1 Φ re - Φ div 25

26 Back to PLL Response Shown Previously PLL output requency indeed oscillates - Eventually locks when requency dierence is small enough N (Divide Value) Synthesizer Response To Divider Step Output Frequency (GHz) Time (microseconds) - How do we extend the requency lock-in range? 26

27 Phase Frequency Detectors (PFD) Example: Tristate PFD 1 D Q up(t) r Q R div(t) 1 R D Q Q down(t) R Div(t) Up(t) Down(t) E(t)

28 Tristate PFD Characteristic Calculate using similar approach as used or XOR phase detector 1 gain = 1/(2π) avg{} 2π 2π Φ re - Φ div 1 phase detector range = 4π Note that phase error characteristic is asymmetric about zero phase - Key attribute or enabling requency detection 28

29 PFD Enables PLL to Always Regain Frequency Lock Asymmetric phase error characteristic allows positive requency dierences to be distinguished rom negative requency dierences - Average value is now positive or negative according to sign o requency oset - PLL always relocks assuming reasonable loop ilter gain Tristate DC characteristic 1 cycle slipping 2π 0 2π 4π 2nπ Φ re - Φ div lock -1 29

30 Another PFD Structure XOR-based PFD D Q r D Q Q re/2(t) Q R div(t) D Q Q div/2(t) D S Q Q Divide-by-2 Phase Detector Frequency Detector r div(t) re/2(t) div/2(t)

31 XOR-based PFD Characteristic Calculate using similar approach as used or XOR phase detector avg{} gain = 1/π 1 3π 2π 0 π 2π 4π 5π Φ re - Φ div 1 phase detector range = 2π Phase error characteristic asymmetric about zero phase - Average value o phase error is positive or negative during cycle slipping depending on sign o requency error 31

32 Linearized PLL Model With PFD Structures Assume that when PLL in lock, phase variations are within the linear range o PFD - Simulate impact o cycle slipping i desired (do not include its eect in model) Same requency-domain PLL model as beore, but PFD gain depends on topology used Φ re (t) PFD Tristate: α=1 XOR-based: α=2 α 2π Loop Filter H() v(t) VCO Kv j Φ out (t) Φ div (t) Divider 1 N 32

33 Type I versus Type II PLL Implementations Type I: one integrator in PLL open loop transer unction - VCO adds one integrator - Loop ilter, H(), has no integrators Type II: two integrators in PLL open loop transer unction - Loop ilter, H(), has one integrator Φ re (t) PFD Tristate: α=1 XOR-based: α=2 α 2π Loop Filter H() v(t) VCO Kv j Φ out (t) Φ div (t) Divider 1 N 33

34 VCO Input Range Issue or Type I PLL Implementations Issue: DC gain o Type I loop ilter oten small and PFD output range is limited - Loop ilter output ails to cover ull input range o VCO - Need additional circuits to achieve ull VCO range - Adds power consumption and area No Integrator V DD Gnd Output Range o Loop Filter r PFD Loop Filter v(t) out(t) VCO Divider N[k] 34

35 Key Beneits o Type II PLL Structures Integrator within loop ilter leads to high DC gain - Steady-state error,, becomes zero - Full range o VCO is easily achieved Includes Integrator V DD Gnd Output Range o Loop Filter r PFD Loop Filter v(t) out(t) VCO Divider N[k] 35

36 Common Loop Filter or Type II PLL Implementation Use a charge pump to create the integrator - Current onto a capacitor orms integrator - Add extra pole/zero using resistor and capacitor Gain o loop ilter can be adjusted according to the value o the charge pump current Example: lead/lag network Charge Pump i(t) v(t) R 1 C 1 C 2 36

37 Charge Pump Implementations Switch currents in and out: Single-Ended Dierential up(t) I cp I out (t) I cp I cp I out (t) down(t) I cp 2I cp 37

38 Modeling o Loop Filter/Charge Pump Charge pump is gain element Loop ilter orms transer unction Charge Pump I cp Loop Filter H(s) v(t) Example: lead/lag network rom previous slide 38

39 Charge Pump PLL Design with Lead/Lag Filter Overall PLL block diagram Φ re (t) PFD Tristate: α=1 XOR-based: α=2 α 2π Charge Pump I cp Loop Filter H() v(t) VCO K v j Φ out (t) Φ div (t) Divider 1 N Loop ilter Set open loop gain to achieve desired PLL bandwidth - Set z lower than and p higher than PLL bandwidth 39

40 Design Loop Filter Using Classical Feedback Concepts Open loop gain increased 20log A() Evaluation o Phase Margin C Closed Loop Pole Locations o G() Im{s} B Dominant pole pair 0 db 120 o -140 o angle(a()) z p C B A PM = 54 o or B PM = 53 o or A PM = 55 o or C Non-dominant pole A B C A A Re{s} o B -180 o C Choose loop ilter or adequate phase margin - Phase margin > 60º or robust stability 40

41 Frequency Synthesizer Noise in Wireless Systems From Antenna and Bandpass Filter Z in PC board Mixer trace RF in IF out Z Package o LNA To Filter Interace Reerence Frequency Frequency Synthesizer VCO LO signal Phase Noise o Synthesizer noise has a negative impact on system - Receiver lower sensitivity, poorer blocking perormance - Transmitter increased spectral emissions (output spectrum must meet a mask requirement) Noise is characterized in requency domain 41

42 Phase Noise Versus Spurious Noise Phase noise is non-periodic S out () dbc/hz - o o S Φout () - Described as a spectral density relative to carrier power Units are dbc/hz 1 Spurious noise is periodic S out () dbc - Described as tone power relative to carrier power Units are dbc 1 - o o spur 1 d spur 2 2 spur 42

43 Sources o Noise in Frequency Synthesizers Reerence Jitter Reerence Feedthrough Charge Pump Noise VCO Noise -20 db/dec T 1/T r PFD Charge Pump Loop Filter v(t) VCO div(t) Divider Jitter Divider N VCO noise Reerence/divider jitter and reerence eedthrough Charge pump noise 43

44 Modeling the Impact o Noise on Output Phase o PLL Divider/Reerence Jitter S Φjit () Reerence Feedthrough S Espur () Charge Pump Noise S Ιcpn () VCO Noise S Φvn () -20 db/dec 0 0 1/T 0 0 Φ jit [k] e spur (t) Ι cpn (t) Φ vn (t) Φ re [k] Φ div [k] α π PFD I cp Charge Pump 1 N H() Loop Filter v(t) K V j VCO Φ out (t) Divider Determine impact on output phase by deriving transer unction rom each noise source to PLL output phase - There are a lot o transer unctions to keep track o! 44

45 Simpliied Noise Model PFD-reerred Noise S En () VCO-reerred Noise S Φvn () -20 db/dec 0 1/T 0 e n (t) Φ vn (t) Φ re [k] Φ div [k] α π PFD I cp Charge Pump 1 N H() Loop Filter v(t) K V j VCO Φ out (t) Divider Reer all PLL noise sources (other than the VCO) to the PFD output - PFD-reerred noise corresponds to the sum o these noise sources reerred to the PFD output 45

46 Impact o PFD-reerred Noise on Synthesizer Output PFD-reerred Noise S En () VCO-reerred Noise S Φvn () -20 db/dec 0 1/T 0 e n (t) Φ vn (t) Φ re [k] Φ div [k] α π PFD I cp Charge Pump 1 N H() Loop Filter v(t) K V j VCO Φ out (t) Divider Transer unction derived using Black s ormula 46

47 Impact o VCO-reerred Noise on Synthesizer Output PFD-reerred Noise S En () VCO-reerred Noise S Φvn () -20 db/dec 0 1/T 0 e n (t) Φ vn (t) Φ re [k] Φ div [k] α π PFD I cp Charge Pump 1 N H() Loop Filter v(t) K V j VCO Φ out (t) Divider Transer unction again derived rom Black s ormula 47

48 A Simpler Parameterization or PLL Transer Functions PFD-reerred Noise S En () VCO-reerred Noise S Φvn () -20 db/dec 0 1/T 0 e n (t) Φ vn (t) Φ re [k] Φ div [k] α π PFD I cp Charge Pump 1 N H() Loop Filter v(t) K V j VCO Φ out (t) Divider Deine G() as Always has a gain o one at DC - A() is the open loop transer unction o the PLL 48

49 Parameterize Noise Transer Functions in Terms o G() PFD-reerred noise VCO-reerred noise 49

50 Parameterized PLL Noise Model PFD-reerred Noise S En () VCO-reerred Noise S Φvn () -20 db/dec 0 e n (t) 1/T 0 Φ vn (t) o α π N G() o 1-G() Φ npd (t) Divider Control o Frequency Setting (assume noiseless or now) Φ c (t) Φ n (t) Φ nvco (t) Φ out (t) PFD-reerred noise is lowpass iltered VCO-reerred noise is highpass iltered Both ilters have the same transition requency values - Deined as o 50

51 Impact o PLL Parameters on Noise Scaling PFD-reerred Noise S En () 0 e n (t) 1/T VCO-reerred Noise S Φvn () -20 db/dec 0 Φ vn (t) Radians 2 /Hz 0 α π N 2 S en () S Φvn () o α π N G() o 1-G() Φ npd (t) Divider Control o Frequency Setting (assume noiseless or now) Φ c (t) Φ n (t) Φ nvco (t) Φ out (t) PFD-reerred noise is scaled and lowpass iltered - High divide values lead to large multiplication o this noise VCO-reerred noise is not scaled and highpass iltered 51

52 Optimal Bandwidth Setting or Minimum Noise PFD-reerred Noise S En () 0 e n (t) 1/T VCO-reerred Noise S Φvn () -20 db/dec 0 Φ vn (t) Radians 2 /Hz 0 ( o ) opt α π N 2 S en () S Φvn () o α π N G() o 1-G() Φ npd (t) Divider Control o Frequency Setting (assume noiseless or now) Φ c (t) Φ n (t) Φ nvco (t) Φ out (t) Optimal bandwidth is where scaled noise sources meet - Higher bandwidth will pass more PFD-reerred noise - Lower bandwidth will pass more VCO-reerred noise 52

53 Resulting Output Noise with Optimal Bandwidth PFD-reerred Noise S En () 0 e n (t) 1/T VCO-reerred Noise S Φvn () -20 db/dec 0 Φ vn (t) Radians 2 /Hz 0 ( o ) opt α π N 2 S en () S Φvn () o Φ npd (t) Divider Control o Frequency Setting (assume noiseless or now) Φ c (t) α π N G() Φ n (t) o 1-G() Φ nvco (t) Φ out (t) Radians 2 /Hz 0 S Φnpd () ( o ) opt S Φnvco () PFD-reerred noise dominates at low requencies - Corresponds to close-in phase noise o synthesizer VCO-reerred noise dominates at high requencies - Corresponds to ar-away phase noise o synthesizer 53

54 Fractional-N Frequency Synthesizers F re F out = M.F F re r N sd [k] div(t) PFD Dithering Modulator Charge Pump N[k] Divider Loop Filter M+1 M v(t) VCO out(t) Kingsord-Smith US Patent 3,928, (iling date) M.F Divide value is dithered between integer values Fractional divide values can be realized! Very high requency resolution 54

55 Sigma-Delta Modulation Time Domain M-bit Input Digital Σ Δ Modulator 1-bit D/A Analog Output Digital Input Spectrum Quantization Noise Frequency Domain Analog Output Spectrum Input Σ Δ Sigma-Delta dithers in a manner such that resulting quantization noise is shaped to high requencies 55

56 Linearized Model o Sigma-Delta Modulator r[k] S r (e j2πt )= NTF z=e j2πt STF q[k] x[k] y[k] x[k] y[k] H Σ Δ s (z) z=e j2πt H n (z) S q (e j2πt )= H n (e j2πt ) Composed o two transer unctions relating input and noise to output - Signal transer unction (STF) Filters input (generally undesirable) - Noise transer unction (NTF) Filters (i.e., shapes) noise that is assumed to be white 56

57 Example: Cutler Sigma-Delta Topology x[k] u[k] y[k] H(z) - 1 e[k] Output is quantized in a multi-level ashion Error signal, e[k], represents the quantization error Filtered version o quantization error is ed back to input - H(z) is typically a highpass ilter whose irst tap value is 1 i.e., H(z) = 1 + a 1 z -1 + a 2 z -2 - H(z) 1 thereore has a irst tap value o 0 Feedback needs to have delay to be realizable 57

58 Linearized Model o Cutler Topology x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Represent quantizer block as a summing junction in which r[k] represents quantization error - Note: It is assumed that r[k] has statistics similar to white noise - This is a key assumption or modeling oten not true! 58

59 Calculation o Signal and Noise Transer Functions x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Calculate using Z-transorm o signals in linearized model - NTF: H n (z) = H(z) - STF: H s (z) = 1 59

60 A Common Choice or H(z) 8 7 m = 3 6 Magnitude m = 2 m = Frequency (Hz) 1/(2T) 60

61 Example: First Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot o output in time and requency domains with input o 1 Amplitude Magnitude (db) 0 0 Sample Number Frequency (Hz) 1/(2T) 61

62 Example: Second Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot o output in time and requency domains with input o 2 Amplitude 1 0 Magnitude (db) -1 0 Sample Number Frequency (Hz) 1/(2T) 62

63 Example: Third Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot o output in time and requency domains with input o 4 3 Amplitude Magnitude (db) Sample Number Frequency (Hz) 1/(2T) 63

64 Observations Low order Sigma-Delta modulators do not appear to produce shaped noise very well - Reason: low order eedback does not properly scramble relationship between input and quantization noise Quantization noise, r[k], ails to be white Higher order Sigma-Delta modulators provide much better noise shaping with ewer spurs - Reason: higher order eedback ilter provides a much more complex interaction between input and quantization noise 64

65 Warning: Higher Order Modulators May Still Have Tones Quantization noise, r[k], is best whitened when a suiciently exciting input is applied to the modulator - Varying input and high order helps to scramble interaction between input and quantization noise Worst input or tone generation are DC signals that are rational with a low valued denominator - Examples (third order modulator with no dithering): x[k] = 0.1 x[k] = /1024 Magnitude (db) Magnitude (db) 0 Frequency (Hz) 1/(2T) 0 Frequency (Hz) 1/(2T) 65

66 Fractional Spurs Can Be Theoretically Eliminated See: - M. Kozak, I. Kale, Rigorous Analysis o Delta-Sigma Modulators or Fractional-N PLL Frequency Synthesis, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 51, no. 6, pp S. Pamarti, I. Galton, "LSB Dithering in MASH Delta Sigma D/A Converters", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp , April

67 Noise Analysis or Sigma-Delta Frequency Synthesizers F re F out = M.F F re r div(t) N sd [m] PFD Σ Δ Modulator Charge Pump N[m] Divider Loop Filter M+1 M Σ Δ Quantization Noise out(t) High resolution o great beneit to RF transceivers - Fine requency tuning, crystal requency compensation v(t) VCO Riley et. al., JSSC, May 1993 How does quantization noise impact the PLL? 67

68 The Need or A Better PLL Model PFD-reerred Noise S En () VCO-reerred Noise S Φvn () -20 db/dec 0 e n (t) 1/T 0 Φ vn (t) Φ re [k] Φ div [k] α π PFD I cp Charge Pump Divider 1 N H() Loop Filter v(t) K V j VCO Φ out (t) Classical PLL model - Predicts impact o PFD and VCO reerred noise sources - Does not allow straightorward modeling o impact due to divide value variations N[k] This is a problem when using ractional-n approach 68

69 Fractional-N PLL Model PFD-reerred Noise S En () VCO-reerred Noise S Φvn () -20 db/dec Φ re [k] PFD Tristate: α=1 XOR: α=2 α T 2π 0 e n (t) 1/T C.P. I cp Loop Filter H() v(t) VCO K V j 0 Φ vn (t) Φ out (t) Φ div [k] Σ Δ Quantization Noise S q (e j2πt ) 0 n[k] 1 N nom Φ d [k] Divider 2π z-1 z=e j2πt 1 - z-1 Closed loop dynamics parameterized by 1 T Perrott et. al. JSSC, Aug

70 Parameterized PLL Noise Model PFD-reerred Noise S En () VCO-reerred Noise S Φvn () -20 db/dec Σ Δ Quantization Noise 0 E n (t) 1/T 0 Φ vn (t) S q (e j2πt ) o 2π α Nnom G() o 1-G() 0 n[k] 2π z z -1 Φ n [k] z=e j2πt T G() o Φ div (t) Φ tn,pll (t) Φ out (t) Design revolves around choice o and G() 70

71 A Well Designed Sigma-Delta Synthesizer -60 o = 84 khz Spectral Density (dbc/hz) PFD-reerred noise S Φout,En () Σ Δ noise S Φout,ΔΣ () VCO-reerred noise S Φout,vn () khz 100 khz 1 MHz 10 MHz Frequency 0 1/T Order o G() is set to equal to the Sigma-Delta order - Sigma-Delta noise alls at -20 db/dec above G() bandwidth Bandwidth o G() is set low enough such that synthesizer noise is dominated by PFD and VCO noise 71

72 Impact o Increased PLL Bandwidth o = 84 khz o = 160 khz Spectral Density (dbc/hz) PFD-reerred noise S Φout,En () Σ Δ noise S Φout,ΔΣ () VCO-reerred noise S Φout,vn () Spectral Density (dbc/hz) PFD-reerred noise S Φout,En () VCO-reerred noise S Φout,vn () Σ Δ noise S Φout,ΔΣ () khz 100 khz 1 MHz 10 MHz Frequency 0 1/T khz 100 khz 1 MHz 10 MHz Frequency 0 1/T Allows more PFD noise to pass through Allows more Sigma-Delta noise to pass through Increases low requency suppression o VCO noise 72

73 Impact o Increased Sigma-Delta Order m = 2 m = Spectral Density (dbc/hz) PFD-reerred noise S Φout,En () Σ Δ noise S Φout,ΔΣ () VCO-reerred noise S Φout,vn () Spectral Density (dbc/hz) PFD-reerred noise S Φout,En () Σ Δ noise S Φout,ΔΣ () VCO-reerred noise S Φout,vn () khz 100 khz 1 MHz 10 MHz Frequency 0 1/T khz 100 khz 1 MHz 10 MHz Frequency 0 1/T PFD and VCO noise unaected Sigma-Delta noise takes on a dierent shape - Impacts PLL only at high oset requencies now Extra loop ilter pole can provide urther attenuation 73

74 PLL Design Assistant ( Provides a straightorward design approach or PLLs Free download 74

75 CppSim System Simulator ( 75

76 A Closer Look at Fractional-N Quantization Noise Re PFD Loop Filter Out Div N/N+1 Frequency Selection M-bit Σ Δ Modulator 1-bit Quantization Noise Spectrum Output Spectrum Noise Frequency Selection F out Σ Δ PLL dynamics Higher PLL bandwidth leads to less quantization noise suppression Tradeo: Noise perormance vs PLL bandwidth 76

77 A Cancellation Method or Reducing Quantization Noise r N sd [k] div(t) PFD Modulator Charge Pump q[k] N[k] DAC out(t) Key idea: quantization noise can be predicted within the digital modulator structure Issue: cancellation is limited by analog matching - Achieves < 20 db cancellation in practice r(t) Loop Filter Divider Pamarti et. al., TCAS II, Nov 2003 v(t) VCO Quantization Noise Suppression 77

78 Improved Cancellation Through Continuous Calibration r N sd [k] div(t) PFD Modulator Charge Pump q[k] gain DAC r(t) Loop Filter N[k] Divider v(t) VCO out(t) Quantization Noise Suppression Gupta et. al., ISSCC, Feb 2006 LMS Algorithm Gain o DAC is adjusted in an adaptive manner using LMS algorithm - > 30 db noise cancellation achieved 78

79 Improved Cancellation Through Inherent Matching r N sd [k] div(t) PFD/DAC Modulator q[k] N[k] r(t) Loop Filter Divider v(t) VCO out(t) Quantization Noise Suppression Meninger et. al., TCAS II, Nov 2003 Combined PFD/DAC structure achieves inherent matching between error and cancellation signal - > 29 db quantization noise cancellation achieved 79

80 A 1 MHz BW Fractional-N Frequency Synthesizer IC r PFD/DAC r(t) Loop Filter v(t) VCO out(t) div(t) Divider N sd [k] Σ Δ Modulator q[k] N[k] Σ Δ Noise Suppression Meninger et. al., JSSC

81 CppSim Behavioral Model o 1MHz Synthesizer Freely downloadable at 81

82 Conclusion Analog requency synthesizers are a dominant component in wireless and processor systems today Analysis and design using classical control theory - Transer unction analysis or dynamics and noise - Cycle slipping is an issue or large transients Fractional-N requency synthesizers are now quite common due to their high resolution - Requires understanding o Sigma-Delta modulation - Additional model complexity or the PLL - Quantization noise cancellation improves perormance CAD tools such as CppSim are useul design aids Improving analog PLLs is an active area o research 82