Sigma-Delta Fractional-N Frequency Synthesis

Transcription

1 Sigma-Delta Fractional-N Frequency Synthesis Scott Meninger Michael Perrott Massachusetts Institute of Technology June 7, 2004 Copyright 2004 by Michael H. Perrott All rights reserved.

2 Note: Much of this material is taken from MITOpenCourseWare Course: 6.976

3 Outline Integer-N synthesis - Bandwidth constraints Fractional-N synthesis - Issue of fractional spurs Σ Fractional-N Synthesis - Quantization noise impact on the PLL Recent developments for lowering the impact of quantization noise Conclusions Q&A

4 Bandwidth Constraints for Integer-N Synthesizers 1/T Loop Filter Bandwidth << 1/T ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) Divider N[k] PFD output has a periodicity of 1/T - 1/T = reference frequency Loop filter must have a bandwidth << 1/T - PFD output pulses must be filtered out and average value extracted Closed loop PLL bandwidth often chosen to be a factor of ten lower than 1/T

5 Bandwidth Versus Frequency Resolution 1/T Loop Filter Bandwidth << 1/T ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) Divider N[k] N[k] S out (f) 1/T out(t) frequency resolution = 1/T GHz Frequency resolution set by reference frequency (1/T) - Higher resolution achieved by lowering 1/T

6 Increasing Resolution in Integer-N Synthesizers 1/T Loop Filter Bandwidth << 1/T 20 MHz 100 ref(t) (1/T = 200 khz) PFD Loop Filter out(t) Divider N[k] 9001 N[k] 9000 out(t) frequency resolution = 1/T S out (f) 1/T GHz Use a reference divider to achieve lower 1/T - Leads to a low PLL bandwidth ( < 20 khz here )

7 The Issue of Noise 1/T Loop Filter Bandwidth << 1/T 20 MHz 100 ref(t) (1/T = 200 khz) PFD Loop Filter out(t) Divider N[k] 9001 N[k] 9000 out(t) frequency resolution = 1/T S out (f) 1/T GHz Lower 1/T leads to higher divide value - Increases PFD noise at synthesizer output

8 Background: Classical Linearized PLL Model PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec 0 e n (t) 1/T f 0 Φ vn (t) f Φ ref [k] Φ div [k] α π PFD e(t) I cp Charge Pump Divider 1 N H(f) Loop Filter v(t) K V jf VCO Φ out (t) N[k] Classical PLL model - Predicts impact of PFD and VCO referred noise sources - Does not allow straightforward modeling of impact due to dynamic divide value variations More on this shortly

9 Background: Classical Linearized PLL Model PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec 0 e n (t) 1/T f 0 Φ vn (t) f Φ ref [k] Φ div [k] α π PFD e(t) I cp Charge Pump Divider 1 N H(f) Loop Filter v(t) K V jf VCO Φ out (t) N[k] Parameterizing in terms of G(f) helps visualize the nature (high-pass or low-pass) and gain of the noise transfer functions

10 Parameterized Version of Classical Model PFD-referred Noise S En (f) e n (t) f o Φ npfd (t) Divider Control of Frequency Setting (assume noiseless for now) 0 1/T 2π N α Φ c (t) f G(f) VCO-referred Noise S Φvn (f) -20 db/dec 0 Φ vn (t) f o f 1-G(f) Φ nvco (t) Φ n (t) Φ out (t) G(f) represents the PLL closed loop dynamics G(f) is low-pass Nature of noise transfer very easily seen from the parameterized model

11 Modeling PFD Noise Multiplication PFD-referred Noise S En (f) 0 e n (t) 1/T f VCO-referred Noise S Φvn (f) -20 db/dec 0 Φ vn (t) f Radians 2 /Hz 0 (f o ) opt α π N 2 S en (f) S Φvn (f) f f o Φ npfd (t) Divider Control of Frequency Setting (assume noiseless for now) Φ c (t) α π N G(f) Φ n (t) f o Φ nvco (t) 1-G(f) Φ out (t) PFD spectral density multiplied by N 2 before influencing PLL output phase noise Radians 2 /Hz S Φnpfd (f) (f o ) opt S Φnvco (f) High divide values high phase noise at low frequencies 0 f

12 Fractional-N Frequency Synthesizers ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) 91 N sd [k] 90 Dithering Modulator N[k] Divider N sd [k] out(t) S out (f) 1/T frequency resolution << 1/T GHz Break constraint that divide value be integer - Dither divide value dynamically to achieve fractional values - Frequency resolution is now arbitrary regardless of 1/T Want high 1/T to allow a high PLL bandwidth

13 Classical Fractional-N Synthesizer Architecture ref(t) PFD e(t) Loop Filter out(t) div(t) N/N+1 frac[k] Accumulator 1-bit carry_out[k] N sd [k] = N + frac[k] Use an accumulator to perform dithering operation - Fractional input value fed into accumulator - Carry out bit of accumulator fed into divider

14 Accumulator Operation clk(t) frac[k] M-bit Accumulator M-bit 1-bit residue[k] carry_out[k] residue[k] frac[k] =.25 carry_out[k] Carry out bit is asserted when accumulator residue reaches or surpasses its full scale value - Accumulator residue increments by input fractional value each clock cycle

15 Fractional-N Synthesizer Signals with N = 4.25 carry_out(t) out(t) div(t) ref(t) e(t) phase error(t) Divide value set at N = 4 most of the time - Resulting frequency offset causes phase error to accumulate - Reset phase error by swallowing a VCO cycle Achieved by dividing by 5 every 4 reference cycles

16 The Issue of Spurious Tones ref(t) PFD e(t) Loop Filter out(t) div(t) N/N+1 frac[k] Accumulator 1-bit carry_out[k] N sd [k] = N + frac[k] PFD error is periodic - Note that actual PFD waveform is series of pulses the sawtooth waveform represents pulse width values over time Periodic error signal creates spurious tones in synthesizer output - Ruins noise performance of synthesizer

17 The Phase Interpolation Technique ref(t) PFD e(t) Loop Filter out(t) div(t) α N/N+1 D/A frac[k] M-bit Accumulator M-bit residue[k] 1-bit carry_out[k] Phase error due to fractional technique is predicted by the instantaneous residue of the accumulator - Cancel out phase error based on accumulator residue

18 The Problem With Phase Interpolation ref(t) PFD e(t) Loop Filter out(t) div(t) α N/N+1 D/A frac[k] M-bit Accumulator M-bit residue[k] 1-bit carry_out[k] Gain matching between PFD error and scaled D/A output must be extremely precise - Any mismatch will lead to spurious tones at PLL output

19 Is There a Better Way?

20 A Better Dithering Method: Sigma-Delta Modulation Time Domain M-bit Input Digital Σ Modulator 1-bit D/A Analog Output Digital Input Spectrum Quantization Noise Frequency Domain Analog Output Spectrum Input Σ Sigma-Delta dithers in a manner such that resulting quantization noise is shaped to high frequencies

21 Linearized Model of Sigma-Delta Modulator r[k] S r (e j2πft )= NTF z=e j2πft STF q[k] x[k] y[k] x[k] y[k] H Σ s (z) z=e j2πft H n (z) S q (e j2πft )= 1 H n (e j2πft ) 2 12 Composed of two transfer functions relating input and noise to output - Signal transfer function (STF) Filters input (generally undesirable) - Noise transfer function (NTF) Filters (i.e., shapes) noise that is assumed to be white

22 Example: Cutler Sigma-Delta Topology x[k] u[k] y[k] H(z) - 1 e[k] Output is quantized in a multi-level fashion Error signal, e[k], represents the quantization error Filtered version of quantization error is fed back to input - H(z) is typically a highpass filter whose first tap value is 1 i.e., H(z) = 1 + a 1 z -1 + a 2 z H(z) 1 therefore has a first tap value of 0 Feedback needs to have delay to be realizable

23 Linearized Model of Cutler Topology x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Represent quantizer block as a summing junction in which r[k] represents quantization error - Note: It is assumed that r[k] has statistics similar to white noise - This is a key assumption for modeling often not true!

24 Calculation of Signal and Noise Transfer Functions x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Calculate using Z-transform of signals in linearized model - NTF: H n (z) = H(z) - STF: H s (z) = 1

25 Choice of H(z) 8 7 m = 3 6 Magnitude m = 2 m = Frequency (Hz) 1/(2T)

26 Example: First Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 1 Amplitude Magnitude (db) 0 0 Sample Number Frequency (Hz) 1/(2T)

27 Example: Second Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 2 Amplitude 1 0 Magnitude (db) -1 0 Sample Number Frequency (Hz) 1/(2T)

28 Example: Third Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of Amplitude Magnitude (db) Sample Number Frequency (Hz) 1/(2T)

29 Observations Low order Sigma-Delta modulators do not appear to produce shaped noise very well - Reason: low order feedback does not properly scramble relationship between input and quantization noise Quantization noise, r[k], fails to be white Higher order Sigma-Delta modulators provide much better noise shaping with fewer spurs - Reason: higher order feedback filter provides a much more complex interaction between input and quantization noise

30 Warning: Higher Order Modulators May Still Have Tones Quantization noise, r[k], is best whitened when a sufficiently exciting input is applied to the modulator - Varying input and high order helps to scramble interaction between input and quantization noise Worst input for tone generation are DC signals that are rational with a low valued denominator - Examples (third order modulator): x[k] = 0.1 x[k] = /1024 Magnitude (db) Magnitude (db) 0 Frequency (Hz) 1/(2T) 0 Frequency (Hz) 1/(2T)

31 Dither The sigma-delta noise shaping analysis assumes a white quantization noise spectrum In order to make the input look sufficiently exciting a dither signal can be added to it Dithering methods are directly taken from sigma-delta ADC and DAC design - This makes sense since the synthesizer is really a DAC (digital to phase) - Most common method is to add a random sequence to the LSB s of the input

32 Cascaded Sigma-Delta Modulator Topologies x[k] Σ M 1 [k] q 1 [k] Σ M 2 [k] q 2 [k] Σ M 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] Digital Cancellation Logic y[k] Multibit output Achieve higher order shaping by cascading low order sections and properly combining their outputs Advantage over single loop approach - Allows pipelining to be applied to implementation High speed or low power applications benefit Disadvantages - Relies on precise matching requirements when combining outputs (not a problem for digital implementations) - Requires multi-bit quantizer for orders > 1 (single loop does not)

33 MASH topology x[k] Σ M 1 [k] r 1 [k] Σ M 2 [k] r 2 [k] Σ M 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Cascade first order sections Combine their outputs after they have passed through digital differentiators

34 Calculation of STF and NTF for MASH topology x[k] Σ M 1 [k] r 1 [k] Σ M 2 [k] r 2 [k] Σ M 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Individual output signals of each first order modulator Addition of filtered outputs

35 Calculation of STF and NTF for MASH topology x[k] Σ M 1 [k] r 1 [k] Σ M 2 [k] r 2 [k] Σ M 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Overall modulator behavior - STF: H s (z) = 1 - NTF: H n (z) = (1 z -1 ) 3

36 Sigma-Delta Frequency Synthesizers F ref F out = M.F F ref ref(t) div(t) N sd [m] PFD e(t) Σ Modulator Charge Pump N[m] Divider Loop Filter M+1 M Σ Quantization Noise v(t) VCO f out(t) Riley et. al., JSSC, May 1993 Use Sigma-Delta modulator rather than accumulator to perform dithering operation - Achieves much better spurious performance than classical fractional-n approach

37 Background: The Need for A Better PLL Model PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec 0 e n (t) 1/T f 0 Φ vn (t) f Φ ref [k] Φ div [k] α π PFD e(t) I cp Charge Pump Divider 1 N H(f) Loop Filter v(t) K V jf VCO Φ out (t) Classical PLL model - Predicts impact of PFD and VCO referred noise sources - Does not allow straightforward modeling of impact due to divide value variations N[k] This is a problem when using fractional-n approach

38 A PLL Model Accommodating Divide Value Variations PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec Φ ref [k] PFD Tristate: α=1 XOR: α=2 α T 2π 0 e n (t) 1/T e(t) f C.P. I cp Loop Filter H(f) v(t) VCO K V jf 0 Φ vn (t) f Φ out (t) Φ div [k] 1 N nom Φ d [k] Divider 1 T n[k] 2π z-1 z=e j2πft 1 - z-1 See derivation in Perrott et. al., A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers, JSSC, Aug 2002

39 Parameterized Version of New Model Noise Φ jit [k] e spur (t) α T π PFD-referred Noise S En (f) 0 e n (t) 1/T f VCO-referred Noise S Φvn (f) -20 db/dec 0 Φ vn (t) f Ι cpn (t) 1 Ι f o π α Nnom G(f) f o 1-G(f) Φ npfd (t) Φ nvco (t) Divide value variation n[k] n[k] 2π z z -1 G(f) Φ d (t) z=e j2πft F c (t) T G(f) f o Alternate Representation f o 1 jf Φ c (t) Φ c (t) Φ n (t) Φ out (t) D/A and Filter Freq. Phase

40 Divider Impact For Classical Vs Fractional-N Approaches Classical Synthesizer 1 1/T n(t) 1 T n[k] G(f) f o F out (t) D/A and Filter Fractional-N Synthesizer 1 1/T n sd (t) 1 T n sd [k] Dithering Modulator n[k] G(f) f o D/A and Filter F out (t) Note: 1/T block represents sampler (to go from CT to DT)

41 Focus on Sigma-Delta Frequency Synthesizer n[k] F out (t) n sd [k] 1 1/T n sd (t) 1 T n sd [k] Σ n[k] G(f) f o F out (t) freq=1/t D/A and Filter Divide value can take on fractional values - Virtually arbitrary resolution is possible PLL dynamics act like lowpass filter to remove much of the quantization noise

42 Quantifying the Quantization Noise Impact PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec n sd [k] S r (e j2πft )= 1 12 NTF STF H s (z) r[k] Σ H n (z) q[k] n[k] z=e j2πft Σ Quantization Noise S q (e j2πft ) 0 2π z z -1 f Φ n [k] z=e j2πft 0 E n (t) f o Φ vn (t) T G(f) Φ tn,pll (t) Φ div (t) Φ out (t) f o 1/T f π α Nnom G(f) 0 f o f 1-G(f) Calculate by simply attaching Sigma-Delta model - We see that quantization noise is integrated and then low-pass filtered before impacting PLL output

43 Summary: Sources of Phase Noise in Σ Synthesis -60 f o = 84 khz In Digital Σ N[k] Σ Noise Parasitic Pole Synth Output Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) Charge-pump / Phase Detector / Reference fc khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T - Low-pass filtered by PLL, dominant at low offset frequencies VCO - High-pass filtered by PLL, dominant at high offset frequencies Σ dithered quantization noise - Low-pass filtered by PLL, noise/bandwidth tradeoff exists

44 A quick note on the linearized model Parasitic Pole In Digital Σ N[k] Σ Noise Synth Output Non-linearities break the assumptions of the linear model - The shaped noise can be folded down to lower frequencies due to non-linearities in the synthesizer PFD/Charge-pump design This process is best seen through behavioral simulation fc

45 A Well Designed Sigma-Delta Synthesizer -60 f o = 84 khz Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T Order of G(f) is set to equal to the Sigma-Delta order - Sigma-Delta noise falls at -20 db/dec above G(f) bandwidth Bandwidth of G(f) is set low enough such that synthesizer noise is dominated by intrinsic PFD and VCO noise

46 Impact of Increased Sigma-Delta Order m = 2 m = 3 Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz f Frequency 0 1/T PFD and VCO noise unaffected Sigma-Delta noise no longer attenuated by G(f) such that a -20 db/dec slope is achieved above its bandwidth

47 Impact of Increased PLL Bandwidth f o = 84 khz f o = 160 khz Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) VCO-referred noise S Φout,vn (f) Σ noise S Φout, Σ (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T khz 100 khz 1 MHz 10 MHz f Frequency 0 1/T Allows more PFD noise to pass through Allows more Sigma-Delta noise to pass through Increases suppression of VCO noise

48 Can the Quantization Noise Impact be reduced?

49 Impact of Increasing the PLL Bandwidth Ref PFD Loop Filter Out Div N/N+1 Frequency Selection M-bit Σ Modulator 1-bit Quantization Noise Spectrum Output Spectrum Noise Frequency Selection F out Σ PLL dynamics Higher PLL bandwidth leads to less quantization noise suppression - There is a direct trade-off between PLL bandwidth and jitter

50 Method 1 of Reducing Quantization Noise ref(t) PFD e(t) Charge Pump Loop Filter v(t) VCO out(t) N phases div(t) Divider Phase Shifting Logic N sd [m] Σ Modulator N[m] Lower quantization step size by switching between multiple phases of the VCO output - Generate phases by using a ring oscillator or delay locked loop Issue: noise induced by mismatch between phases

51 Method 2 of Reducing Quantization Noise ref(t) PFD e(t) Charge Pump D/A Loop Filter v(t) VCO out(t) div(t) Divider N sd [m] Accumulator Residue Carry Out Use classical fractional-n approach of phase interpolation to cancel out quantization noise - Use a D/A converter matched to PFD/Charge Pump output Issue: limited by mismatch between gain of D/A and PFD/Charge Pump output and nonlinearity in D/A

52 Comparison of Approaches Phase shifting - Vertical approach dq = 4 4 I chp T vco Vertical Slicing with B = I chp T vco 2 4 I chp T vco 1 4 I chp T vco 0 4 I chp T vco Charge Pump Output Phase interpolation Charge Pump Output I chp - Horizontal approach dq = 0 I chp 0 T vco T vco T vco T vco 4 4 I chp T vco Horizontal Slicing with B = I chp T vco 2 4 I chp T vco 1 4 I chp T vco T vco T vco T vco T vco T vco 0 4 I chp T vco T vco ε = 0 4 ε = 1 4 ε = 2 4 ε = 3 4 ε = 4 4 dq = Charge Transferred In Dashed Box

53 Comparison of Approaches Phase shifting - Limited by number of phases that can be generated and their mismatch - Ring oscillators have poor phase noise Phase interpolation - Limited by ability to match DAC output to that of the PFD/Charge pump - High spurious noise can result due to DAC nonlinearity Key observation - Phase interpolation allows us to take advantage of advances in DAC design over the last 20 years We can now largely overcome the above limitations!

54 Two Recent Phase Interpolation Methods A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL With 1-Mb/s In-Loop Modulation, Sudhakar Pamarti and Ian Galton, JSSC, Nov Impact of DAC mismatch mitigated by using Σ- modulator rather than accumulator to perform dithering - Impact of DAC nonlinearity mitigated by using mismatch noise shaping techniques - Overall: reliably achieves 20 db noise suppression A Fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure, Scott Meninger and M.H. Perrott, TCAS II, Nov Utilizes a mismatch compensated PFD/DAC structure - Simulations show that 40 db noise suppression is achievable!

55 Key Element: A PFD/DAC Structure PFD PFD PFD PFD T vco T vco Leverages application of selective delays of parallel PFD outputs to realize the D/A function - No explicit D/A required - Delay of one VCO cycle can be easily achieved using registers clocked by the VCO Illustrate the idea through animation

56 Apply Phase Shift to Two out of the Four PFD s PFD PFD PFD PFD T vco T vco Net horizontal level shifts to halfway point

57 Apply Phase Shift to Three out of the Four PFD s PFD PFD PFD PFD T vco T vco Net horizontal point shifts up DAC function is self-aligned in gain to PFD output!

58 Actual PFD/DAC Implementation Ref Div VCO Register Based Delay Timing Mismatch Compensation and Re-synchronization Φ0 Φ1 PFD0 PFD1 Charge Pump To Loop Filter Swap From Σ B DAC Mismatch Shaping 2 B 2 B Current Sources A current DAC is used, but is self-aligned to PFD output using the phase shifting method just discussed Nonlinearity of the DAC is removed using mismatch noise shaping techniques Note: approach overcomes mismatch limitations of prior art: Y. Dufour, Fractional Division Charge Compensation, US Patent 6,130,561

59 A quick note on simulation Our group has developed some CAD tools for PLL design PLL Design Assistant - GUI tool which returns required open loop PLL parameters for a desired closed loop response - Also performs noise transfer analysis CppSim - A C++ behavioral level simulator - Has a GUI and schematic capture tool for design and simulation of systems URL: -

60 PLL Design Assistant

61 CppSim A Fast Behavioral Simulator

62 Goal: Wide bandwidth, low noise synthesizer! Plots below compare classical Σ synth vs. phase interpolation with a 6 bit DAC 36dB Σ noise reduction! BW=1MHz, = 1 BW=1MHz, = 1/64 - Left: Calculated Performance with =1 (classical synth) - Right: Calculated Performance with =1/64

63 Goal: Wide bandwidth, low noise synthesizer! Behavioral simulations verify this is possible (CppSim) 80 Simulated Phase Noise of Freq. Synth Σ Noise Total Noise L(f) (dbc/hz) Frequency Offset from Carrier (Hz) BW=1MHz, = 1/64 BW=1MHz, = 1/64 - Left: Calculated Performance (PLL Design Assistant) - Right: Simulated Performance (CppSim Behavioral)

64 Other Issues to Consider Additional non-idealities must be dealt with - Timing mismatch - Impact of shape of horizontal cancellation waveforms - Impact of both DAC element and timing mismatch sources on achievable spurious performance Note: detailed analytical examination of the above items is difficult - CppSim is an invaluable tool for exploring such issues More details in the paper: A Fractional-N Frequency Synthesizer Architecture Utilizing a Mismatch Compensated PFD/DAC Structure, Scott Meninger, Michael Perrott, TCASII, Nov 2003

65 Conclusions Sigma-Delta Fractional-N Synthesis overcomes the bandwidth limitations of Integer-N synthesis and the spurious limitations of Fractional-N synthesis - Cost is management of the shaped quantization noise Also have to be cautious of tones with the sigma-delta - Can use higher order modulators - Can use dithered input Recent work demonstrates that it is possible to reduce the level of the phase quantization noise using multiphase or multilevel cancellation approach

66 Appendix A sampling of references on Fractional-N, Sigmadelta Fractional-N, and general PLL design - Frequency Synthesis by Phase lock Egan, W.F. - The Design of CMOS Radio Frequency Integrated Circuits Lee, T.H. - Phase Locking in High-Performance Systems edited by Razavi, B. - Monolithic Phase-locked loops and clock recovery circuits edited by Razavi, B. - Delta-Sigma Data Converters edited by Norsworthy, S.R. et. al. Book does not explicitly cover synthesizers, but is a good reference for sigma-delta concepts