Integrated Circuit Design for High-Speed Frequency Synthesis

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1 Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com

2 Preface XI CHAPTER 1 Introduction Introduction to Frequency Synthesis Frequency Synthesis for Telecommunications Systems Frequency Synthesis for Digital Circuit Applications Frequency Synthesis for Clock and Data Recovery Frequency Synthesis for Modulation and Waveform Generation Overview 13 References 14 CHAPTER 2 Synthesizer Architectures Introduction yj 2.2 Integer-N PLL Synthesizers Fractional-N PLL Frequency Synthesizers Fractional-N Synthesizer with Dual-Modulus Prescaler An Accumulator with Programmable Size Fractional-N Synthesizer with Multimodulus Divider Fractional-N Spurious Components Delay-Locked Loops Clock and Data Recovery (CDR) PLLs Direct Digital Synthesizers Direct Digital Synthesizer with Read-Only Memory Lookup Table ROM-Less Direct Digital Synthesizer Direct Analog Frequency Synthesizers Hybrid Frequency Synthesizers 34 References 3 g CHAPTER3 System-Level Overview of PLL-Based Frequency Synthesis Introduction PLLs (Example of a Feedback System) PLL Components VCOs and Dividers Phase Detectors 4g The Loop Filter 51

3 Contents 3.4 Continuous-Time Analysis for PLL Synthesizers Simplified Loop Equations PLL System Frequency Response and Bandwidth Complete Loop Transfer Function, Including C Discrete-Time Analysis for PLL Synthesizers Transient Behavior of PLLs Linear Transient Behavior Nonlinear Transient Behavior Phase Noise and Timing Jitter in PLL Synthesis Various Noise Sources in PLL Synthesizers In-Band and Out-of-Band Phase Noise in PLL Synthesis 78 References 83 CHAPTER 4 Introduction to Digital IC Design Digital Design Methodology and Flow VerilogHDL Verilog Program Structure Verilog Data Formats Verilog Operators Verilog Control Constructs Blocking and Nonblocking Assignments Tasks and Functions Behavioral and Structural Modeling Combinational Digital Circuit Design Sequential Digital Circuit Design Digital Design Example I: A Multimodulus Divider Digital Design Example II: A Programmable MASH A2 Modulator MASH SA Modulator Top-Level Structure Fractional Accumulator with Programmable Size and Seed- Loading Capability Reset Synchronization Simulated Results 117 References 118 CHAPTER 5 CMOS Logic and Current Mode Logic Introduction CMOS Logic Circuits Large-Signal Behavior of Bipolar and CMOS Differential Pairs Effect of Capacitance on Slew Rate Trade-Off Between Power Consumption and Speed CML Combinational Circuits CML Sequential Circuits Master-Slave D-Flip-Flop CML Circuit-Delay Analysis 142

4 Contents VII 5.10 Low-Power CML Circuits CML Biasing Circuits Driver Circuits 150 References 152 CHAPTER 6 Dividers and Phase-Frequency Detectors Introduction Dividers A Static Divide-by-Two Circuit Programmable Divide-by-Two or Divide-by-Three Circuit A 50% Duty Cycle, High-Speed, Divide-by-Three Circuit A Multimodulus Divider A Generic MMD Architecture Pulse-Swallow Dividers Multipliers Phase Detectors Basic Types of Phase Detectors Circuit Implementations of PFDs Dead Zone in PFDs Lock-Detection Circuits A Modified PFD with Aligned UP and DN Pulses PFDs for CDR Applications 191 References 196 CHAPTER 7 Charge Pumps and Loop Filters Introduction Charge Pumps A Basic Charge Pump Saturation Voltage Current Source Output Impedance Reference Feedthrough Transistor Gain Considerations Charge Pump Noise Charge Sharing Improving Matching Between Ip and I n Charge Pumps Compatible with CML/ECL A Differential Charge Pump Common-Mode Feedback for a Differential Charge Pump Another Differential Charge Pump Programmable Bias Schemes Loop Filters Passive Loop Filters Active Loop Filters LC Loop Filters 224 References 230

5 VIII Contents CHAPTER 8 Voltage-Controlled Oscillators Introduction Specification of Oscillator Properties LC-Based VCOs Inductors Varactors for Oscillator Frequency Control Oscillator Analysis Colpitts Oscillator Analysis Negative Resistance of -G m Oscillator Amplitude of a Negative G m Oscillator Several Refinements to the -G m Topology Injection-Locked Oscillators Phase Shift of Injection-Locked Oscillator Quadrature LC Oscillators Using Injection Locking Parallel Coupled Quadrature LC Oscillators Series Coupled Quadrature Oscillators Other Quadrature-Generation Techniques Other Techniques to Generate Quadrature Signals Phase Noise in LC Oscillators Linear or Additive Phase Noise and Leeson's Formula Switching Phase Noise in Cross-Coupled Pairs Low-Frequency Phase Noise Upconversion Reduction Techniques Bank Switching g m Matching and Waveform Symmetry Differential Varactors and Differential Tuning Ring Oscillators Common Inverter Circuits Method for Designing a Two-Stage Ring Oscillator Phase Noise and Jitter in Ring Oscillators Crystal Oscillators Summary: Comparison of Oscillator Performance 298 References 299 CHAPTER 9 SA Modulation for Fractional-N Synthesis Introduction Basic Concepts Quantization Noise and Oversampling Effects Noise-Shaping Effect An Overview of SA Modulators First-Order SA Modulators Second-Order SA Modulators High-Order SA Modulators 312

6 IX 9.3 SA Modulation in Fractional-N Frequency Synthesis A First-Order SA Modulator for Fractional-N Frequency Synthesis MASH SA Modulator Single-Stage SA Modulators with Multiple Feedback Paths Single-Stage SA Modulators with a Single Feedback Path A Generic High-Order SA Modulator Topology Modified SA Modulator with Improved High-Frequency Response Phase Noise Due to SA Converters Randomization by Noise-Shaped Dithering Spur Reduction Using Precalculated Seeds Dynamic Range Maximal Loop Bandwidth Optimal Parameters Performance Comparison 355 References 356 CHARTER 10 Direct Digital Synthesis Introduction DDS Theory of Operation DDS Spectral Purity Phase Noise Due to Clock Jitter Spurs Due to Discrete Phase Accumulation Spurs and Quantization Noise Due to Phase Truncation Quantization Noise Due to Finite Number of Amplitude Bits DAC Nonlinearities and Aliased Images Oversampling Effect SA Noise Shaping in DDS DDS Using Phase Domain SA Noise Shaping DDS Using Frequency Domain SA Noise Shaping ROM Size Reduction Using SA Noise Shaping High-Speed ROM-Less DDS Pipelined Accumulator Accumulator with CLA Adders Sine-Weighted Nonlinear DACs Nonlinear DAC Segmentations Nonlinear Coarse DAC Comparison of ROM-Less DDS Performance 394 References 395 CHAPTER11 Direct Modulation in Frequency Synthesizers Introduction Direct Modulation in PLL Frequency Synthesizers 398

7 X Contents 11.3 Direct Digital Modulation and Waveform Generation in a DDS Phase Modulation Phase Shift Keying Frequency Modulation Minimum Shift Keying Step Frequency Chirp Waveforms Amplitude Modulation Quadrature Amplitude Modulation Waveform Generation 414 References 415 APPENDIX A A Review of Basic Control Theory 417 A.l Introduction 417 A.2 The Continuous-Time Laplace Transform 418 A.3 The Laplace Transform and Sampling 418 A.4 System Modeling with Frequency Response 423 A.4.1 Frequency Response of Continuous Systems 423 A.4.2 Frequency Response of Sampled Systems 428 A.5 Response in the Time Domain 431 A.6 Feedback Systems 436 A.7 Steady-State Error and the System Type 440 A.8 Stability 441 A.9 Root Locus 442 References 445 APPENDIX B A Review of Transistor Models 447 B.l Introduction 447 B.2 The Basics of CMOS Transistors 447 B.2.1 Basic DC Biasing Characteristics 447 B.2.2 Basic CMOS Square Law Equations 449 B.2.3 The Body Effect 450 B.2.4 High-Frequency Effects 450 B.2.5 Thermal Noise 451 B.2.6 Shot Noise 452 B.2.7 IIf Noise 452 B.2.8 Gate Noise 452 B.2.9 CMOS Small-Signal Model, Including Noise 453 B.3 Bipolar Transistors 453 References 457 About the Authors 459 Index 461

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