Integrated Circuit Design for High-Speed Frequency Synthesis
|
|
- Samson Long
- 5 years ago
- Views:
Transcription
1 Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com
2 Preface XI CHAPTER 1 Introduction Introduction to Frequency Synthesis Frequency Synthesis for Telecommunications Systems Frequency Synthesis for Digital Circuit Applications Frequency Synthesis for Clock and Data Recovery Frequency Synthesis for Modulation and Waveform Generation Overview 13 References 14 CHAPTER 2 Synthesizer Architectures Introduction yj 2.2 Integer-N PLL Synthesizers Fractional-N PLL Frequency Synthesizers Fractional-N Synthesizer with Dual-Modulus Prescaler An Accumulator with Programmable Size Fractional-N Synthesizer with Multimodulus Divider Fractional-N Spurious Components Delay-Locked Loops Clock and Data Recovery (CDR) PLLs Direct Digital Synthesizers Direct Digital Synthesizer with Read-Only Memory Lookup Table ROM-Less Direct Digital Synthesizer Direct Analog Frequency Synthesizers Hybrid Frequency Synthesizers 34 References 3 g CHAPTER3 System-Level Overview of PLL-Based Frequency Synthesis Introduction PLLs (Example of a Feedback System) PLL Components VCOs and Dividers Phase Detectors 4g The Loop Filter 51
3 Contents 3.4 Continuous-Time Analysis for PLL Synthesizers Simplified Loop Equations PLL System Frequency Response and Bandwidth Complete Loop Transfer Function, Including C Discrete-Time Analysis for PLL Synthesizers Transient Behavior of PLLs Linear Transient Behavior Nonlinear Transient Behavior Phase Noise and Timing Jitter in PLL Synthesis Various Noise Sources in PLL Synthesizers In-Band and Out-of-Band Phase Noise in PLL Synthesis 78 References 83 CHAPTER 4 Introduction to Digital IC Design Digital Design Methodology and Flow VerilogHDL Verilog Program Structure Verilog Data Formats Verilog Operators Verilog Control Constructs Blocking and Nonblocking Assignments Tasks and Functions Behavioral and Structural Modeling Combinational Digital Circuit Design Sequential Digital Circuit Design Digital Design Example I: A Multimodulus Divider Digital Design Example II: A Programmable MASH A2 Modulator MASH SA Modulator Top-Level Structure Fractional Accumulator with Programmable Size and Seed- Loading Capability Reset Synchronization Simulated Results 117 References 118 CHAPTER 5 CMOS Logic and Current Mode Logic Introduction CMOS Logic Circuits Large-Signal Behavior of Bipolar and CMOS Differential Pairs Effect of Capacitance on Slew Rate Trade-Off Between Power Consumption and Speed CML Combinational Circuits CML Sequential Circuits Master-Slave D-Flip-Flop CML Circuit-Delay Analysis 142
4 Contents VII 5.10 Low-Power CML Circuits CML Biasing Circuits Driver Circuits 150 References 152 CHAPTER 6 Dividers and Phase-Frequency Detectors Introduction Dividers A Static Divide-by-Two Circuit Programmable Divide-by-Two or Divide-by-Three Circuit A 50% Duty Cycle, High-Speed, Divide-by-Three Circuit A Multimodulus Divider A Generic MMD Architecture Pulse-Swallow Dividers Multipliers Phase Detectors Basic Types of Phase Detectors Circuit Implementations of PFDs Dead Zone in PFDs Lock-Detection Circuits A Modified PFD with Aligned UP and DN Pulses PFDs for CDR Applications 191 References 196 CHAPTER 7 Charge Pumps and Loop Filters Introduction Charge Pumps A Basic Charge Pump Saturation Voltage Current Source Output Impedance Reference Feedthrough Transistor Gain Considerations Charge Pump Noise Charge Sharing Improving Matching Between Ip and I n Charge Pumps Compatible with CML/ECL A Differential Charge Pump Common-Mode Feedback for a Differential Charge Pump Another Differential Charge Pump Programmable Bias Schemes Loop Filters Passive Loop Filters Active Loop Filters LC Loop Filters 224 References 230
5 VIII Contents CHAPTER 8 Voltage-Controlled Oscillators Introduction Specification of Oscillator Properties LC-Based VCOs Inductors Varactors for Oscillator Frequency Control Oscillator Analysis Colpitts Oscillator Analysis Negative Resistance of -G m Oscillator Amplitude of a Negative G m Oscillator Several Refinements to the -G m Topology Injection-Locked Oscillators Phase Shift of Injection-Locked Oscillator Quadrature LC Oscillators Using Injection Locking Parallel Coupled Quadrature LC Oscillators Series Coupled Quadrature Oscillators Other Quadrature-Generation Techniques Other Techniques to Generate Quadrature Signals Phase Noise in LC Oscillators Linear or Additive Phase Noise and Leeson's Formula Switching Phase Noise in Cross-Coupled Pairs Low-Frequency Phase Noise Upconversion Reduction Techniques Bank Switching g m Matching and Waveform Symmetry Differential Varactors and Differential Tuning Ring Oscillators Common Inverter Circuits Method for Designing a Two-Stage Ring Oscillator Phase Noise and Jitter in Ring Oscillators Crystal Oscillators Summary: Comparison of Oscillator Performance 298 References 299 CHAPTER 9 SA Modulation for Fractional-N Synthesis Introduction Basic Concepts Quantization Noise and Oversampling Effects Noise-Shaping Effect An Overview of SA Modulators First-Order SA Modulators Second-Order SA Modulators High-Order SA Modulators 312
6 IX 9.3 SA Modulation in Fractional-N Frequency Synthesis A First-Order SA Modulator for Fractional-N Frequency Synthesis MASH SA Modulator Single-Stage SA Modulators with Multiple Feedback Paths Single-Stage SA Modulators with a Single Feedback Path A Generic High-Order SA Modulator Topology Modified SA Modulator with Improved High-Frequency Response Phase Noise Due to SA Converters Randomization by Noise-Shaped Dithering Spur Reduction Using Precalculated Seeds Dynamic Range Maximal Loop Bandwidth Optimal Parameters Performance Comparison 355 References 356 CHARTER 10 Direct Digital Synthesis Introduction DDS Theory of Operation DDS Spectral Purity Phase Noise Due to Clock Jitter Spurs Due to Discrete Phase Accumulation Spurs and Quantization Noise Due to Phase Truncation Quantization Noise Due to Finite Number of Amplitude Bits DAC Nonlinearities and Aliased Images Oversampling Effect SA Noise Shaping in DDS DDS Using Phase Domain SA Noise Shaping DDS Using Frequency Domain SA Noise Shaping ROM Size Reduction Using SA Noise Shaping High-Speed ROM-Less DDS Pipelined Accumulator Accumulator with CLA Adders Sine-Weighted Nonlinear DACs Nonlinear DAC Segmentations Nonlinear Coarse DAC Comparison of ROM-Less DDS Performance 394 References 395 CHAPTER11 Direct Modulation in Frequency Synthesizers Introduction Direct Modulation in PLL Frequency Synthesizers 398
7 X Contents 11.3 Direct Digital Modulation and Waveform Generation in a DDS Phase Modulation Phase Shift Keying Frequency Modulation Minimum Shift Keying Step Frequency Chirp Waveforms Amplitude Modulation Quadrature Amplitude Modulation Waveform Generation 414 References 415 APPENDIX A A Review of Basic Control Theory 417 A.l Introduction 417 A.2 The Continuous-Time Laplace Transform 418 A.3 The Laplace Transform and Sampling 418 A.4 System Modeling with Frequency Response 423 A.4.1 Frequency Response of Continuous Systems 423 A.4.2 Frequency Response of Sampled Systems 428 A.5 Response in the Time Domain 431 A.6 Feedback Systems 436 A.7 Steady-State Error and the System Type 440 A.8 Stability 441 A.9 Root Locus 442 References 445 APPENDIX B A Review of Transistor Models 447 B.l Introduction 447 B.2 The Basics of CMOS Transistors 447 B.2.1 Basic DC Biasing Characteristics 447 B.2.2 Basic CMOS Square Law Equations 449 B.2.3 The Body Effect 450 B.2.4 High-Frequency Effects 450 B.2.5 Thermal Noise 451 B.2.6 Shot Noise 452 B.2.7 IIf Noise 452 B.2.8 Gate Noise 452 B.2.9 CMOS Small-Signal Model, Including Noise 453 B.3 Bipolar Transistors 453 References 457 About the Authors 459 Index 461
Phase-Locked Loop Engineering Handbook for Integrated Circuits
Phase-Locked Loop Engineering Handbook for Integrated Circuits Stanley Goldman ARTECH H O U S E BOSTON LONDON artechhouse.com Preface Acknowledgments xiii xxi CHAPTER 1 Cetting Started with PLLs 1 1.1
More informationALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS
ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS ROBERT BOGDAN STASZEWSKI Texas Instruments PORAS T. BALSARA University of Texas at Dallas WILEY- INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION
More informationPhase-Locked Loops. Roland E. Best. Me Graw Hill. Sixth Edition. Design, Simulation, and Applications
Phase-Locked Loops Design, Simulation, and Applications Roland E. Best Sixth Edition Me Graw Hill New York Chicago San Francisco Lisbon London Madrid Mexico City Milan New Delhi San Juan Seoul Singapore
More informationLecture 7: Components of Phase Locked Loop (PLL)
Lecture 7: Components of Phase Locked Loop (PLL) CSCE 6933/5933 Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages,
More informationTaheri: A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop
Engineering, Technology & Applied Science Research Vol. 7, No. 2, 2017, 1473-1477 1473 A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop Hamidreza Esmaeili Taheri Department of Electronics
More informationf o Fig ECE 6440 Frequency Synthesizers P.E. Allen Frequency Magnitude Spectral impurity Frequency Fig010-03
Lecture 010 Introduction to Synthesizers (5/5/03) Page 010-1 LECTURE 010 INTRODUCTION TO FREQUENCY SYNTHESIZERS (References: [1,5,9,10]) What is a Synthesizer? A frequency synthesizer is the means by which
More informationAnalysis and Design of Autonomous Microwave Circuits
Analysis and Design of Autonomous Microwave Circuits ALMUDENA SUAREZ IEEE PRESS WILEY A JOHN WILEY & SONS, INC., PUBLICATION Contents Preface xiii 1 Oscillator Dynamics 1 1.1 Introduction 1 1.2 Operational
More informationPHASELOCK TECHNIQUES INTERSCIENCE. Third Edition. FLOYD M. GARDNER Consulting Engineer Palo Alto, California A JOHN WILEY & SONS, INC.
PHASELOCK TECHNIQUES Third Edition FLOYD M. GARDNER Consulting Engineer Palo Alto, California INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS PREFACE NOTATION xvii xix 1 INTRODUCTION 1 1.1
More informationDesign of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits Behzad Razavi Professor of Electrical Engineering University of California, Los Angeles H Boston Burr Ridge, IL Dubuque, IA Madison, WI New York San Francisco
More informationChapter 2 Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL
Chapter 2 Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL 2.1 Background High performance phase locked-loops (PLL) are widely used in wireless communication systems to provide
More informationRF and Baseband Techniques for Software Defined Radio
RF and Baseband Techniques for Software Defined Radio Peter B. Kenington ARTECH HOUSE BOSTON LONDON artechhouse.com Contents Preface Scope of This Book Organisation of the Text xi xi xi Acknowledgements
More informationECEN620: Network Theory Broadband Circuit Design Fall 2012
ECEN620: Network Theory Broadband Circuit Design Fall 2012 Lecture 20: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam 2 is on Friday Nov. 9 One double-sided 8.5x11
More informationDesign of a Frequency Synthesizer for WiMAX Applications
Design of a Frequency Synthesizer for WiMAX Applications Samarth S. Pai Department of Telecommunication R. V. College of Engineering Bangalore, India Abstract Implementation of frequency synthesizers based
More informationMicroelectronic Circuits
SECOND EDITION ISHBWHBI \ ' -' Microelectronic Circuits Adel S. Sedra University of Toronto Kenneth С Smith University of Toronto HOLT, RINEHART AND WINSTON HOLT, RINEHART AND WINSTON, INC. New York Chicago
More informationAnalog Filter and. Circuit Design Handbook. Arthur B. Williams. Singapore Sydney Toronto. Mc Graw Hill Education
Analog Filter and Circuit Design Handbook Arthur B. Williams Mc Graw Hill Education New York Chicago San Francisco Athens London Madrid Mexico City Milan New Delhi Singapore Sydney Toronto Contents Preface
More informationData Converters. Springer FRANCO MALOBERTI. Pavia University, Italy
Data Converters by FRANCO MALOBERTI Pavia University, Italy Springer Contents Dedicat ion Preface 1. BACKGROUND ELEMENTS 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 The Ideal Data Converter Sampling 1.2.1 Undersampling
More informationRF AND MICROWAVE CIRCUIT DESIGN FOR WIRELESS COMMUNICATIONS. Lawrence E. Larson editor. Artech House Boston London
RF AND MICROWAVE CIRCUIT DESIGN FOR WIRELESS COMMUNICATIONS Lawrence E. Larson editor Artech House Boston London CONTENTS Preface xi Chapter 1 An Overview 1 1.1 Introduction 1 1.2 Markets and Frequencies
More informationSection 1. Fundamentals of DDS Technology
Section 1. Fundamentals of DDS Technology Overview Direct digital synthesis (DDS) is a technique for using digital data processing blocks as a means to generate a frequency- and phase-tunable output signal
More informationPreface... Chapter 1. Nonlinear Two-terminal Devices... 1
Preface........................................... xi Chapter 1. Nonlinear Two-terminal Devices.................... 1 1.1. Introduction..................................... 1 1.2. Example of a nonlinear
More informationDedication. To Mum and Dad
Dedication To Mum and Dad Acknowledgment Table of Contents List of Tables List of Figures A B A B 0 1 B A List of Abbreviations Abstract Chapter1 1 Introduction 1.1. Motivation Figure 1. 1 The relative
More informationA 5 GHz DIGITALLY CONTROLLED SYNTHESIZER IN 90NM CMOS
A 5 GHz DIGITALLY CONTROLLED SYNTHESIZER IN 90NM CMOS By Bill Hamon A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING WASHINGTON
More informationDESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS
DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS by Yves Geerts Alcatel Microelectronics, Belgium Michiel Steyaert KU Leuven, Belgium and Willy Sansen KU Leuven,
More informationDirect Digital Synthesis Primer
Direct Digital Synthesis Primer Ken Gentile, Systems Engineer ken.gentile@analog.com David Brandon, Applications Engineer David.Brandon@analog.com Ted Harris, Applications Engineer Ted.Harris@analog.com
More informationPhase Locked Loop Analysis and Design
Phase Locked Loop Analysis and Design Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis
More information/$ IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006 1205 A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for
More informationDesign of an Efficient Phase Frequency Detector for a Digital Phase Locked Loop
Design of an Efficient Phase Frequency Detector for a Digital Phase Locked Loop Shaik. Yezazul Nishath School Of Electronics Engineering (SENSE) VIT University Chennai, India Abstract This paper outlines
More informationModeling And Implementation of All-Digital Phase-Locked Loop Based on Vernier Gated Ring Oscillator Time-to-Digital Converter
Master s Thesis Modeling And Implementation of All-Digital Phase-Locked Loop Based on Vernier Gated Ring Oscillator Time-to-Digital Converter Ji Wang Department of Electrical and Information Technology,
More informationA 5GHz, 32mW CMOS Frequency Synthesizer with an Injection Locked Frequency Divider. Hamid Rategh, Hirad Samavati, Thomas Lee
A 5GHz, 32mW CMOS Frequency Synthesizer with an Injection Locked Frequency Divider Hamid Rategh, Hirad Samavati, Thomas Lee OUTLINE motivation introduction synthesizer architecture synthesizer building
More informationDesign Challenges In Multi-GHz PLL Frequency Synthesizers
Design Challenges In Multi-GHz PLL Frequency Synthesizers Adrian Maxim Senior RF Design Engineer Silicon Laboratories Austin, TX, USA Email: acmaxim@yahoo.com OUTLINE PLL basics PLL second order effects
More informationMultiple Reference Clock Generator
A White Paper Presented by IPextreme Multiple Reference Clock Generator Digitial IP for Clock Synthesis August 2007 IPextreme, Inc. This paper explains the concept behind the Multiple Reference Clock Generator
More informationAnalysis and Design of a Low-Power Low-Noise CMOS Phase-Locked Loop
Analysis and Design of a Low-Power Low-Noise CMOS Phase-Locked Loop by Cheng Zhang B.A.Sc., Simon Fraser University, 2009 Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Master
More informationMinimizing Spurious Tones in Digital Delta-Sigma Modulators
Minimizing Spurious Tones in Digital Delta-Sigma Modulators ANALOG CIRCUITS AND SIGNAL PROCESSING Series Editors: Mohammed Ismail Mohamad Sawan For other titles published in this series, go to http://www.springer.com/series/7381
More informationFractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter
J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September
More informationPhysical electronics, various electronics devices, ICs form the core of Electronics and Telecommunication branch. This part includes
Paper-1 Syllabus for Electronics & Telecommunication Engineering: This part is for both objective and conventional type papers: 1) Materials and Components Materials and Components are the vertebral column
More informationLecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1
Lecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1 LECTURE 160 CDR EXAMPLES INTRODUCTION Objective The objective of this presentation is: 1.) Show two examples of clock and data recovery
More informationIntroductory Electronics for Scientists and Engineers
Introductory Electronics for Scientists and Engineers Second Edition ROBERT E. SIMPSON University of New Hampshire Allyn and Bacon, Inc. Boston London Sydney Toronto Contents Preface xiü 1 Direct Current
More informationBehavior Model of Noise Phase in a Phase Locked Loop Employing Sigma Delta Modulator
Behavior Model of Noise Phase in a Phase Locked Loop Employing Sigma Delta Modulator Tayebeh Ghanavati Nejad 1 and Ebrahim Farshidi 2 1,2 Electrical Department, Faculty of Engineering, Shahid Chamran University
More informationDESIGN OF HIGH FREQUENCY CMOS FRACTIONAL-N FREQUENCY DIVIDER
12 JAVA Journal of Electrical and Electronics Engineering, Vol. 1, No. 1, April 2003 DESIGN OF HIGH FREQUENCY CMOS FRACTIONAL-N FREQUENCY DIVIDER Totok Mujiono Dept. of Electrical Engineering, FTI ITS
More informationA FREQUENCY SYNTHESIZER STRUCTURE BASED ON COINCIDENCE MIXER
3 A FREQUENCY SYNTHESIZER STRUCTURE BASED ON COINCIDENCE MIXER Milan STORK University of West Bohemia UWB, P.O. Box 314, 30614 Plzen, Czech Republic stork@kae.zcu.cz Keywords: Coincidence, Frequency mixer,
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 010 Lecture 7: PLL Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project Preliminary Report
More informationA Flying-Adder Architecture of Frequency and Phase Synthesis With Scalability
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 5, OCTOBER 2002 637 A Flying-Adder Architecture of Frequency and Phase Synthesis With Scalability Liming Xiu, Member, IEEE,
More informationTHE serial advanced technology attachment (SATA) is becoming
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54, NO. 11, NOVEMBER 2007 979 A Low-Jitter Spread Spectrum Clock Generator Using FDMP Ding-Shiuan Shen and Shen-Iuan Liu, Senior Member,
More informationAssociate In Applied Science In Electronics Engineering Technology Expiration Date:
PROGRESS RECORD Study your lessons in the order listed below. Associate In Applied Science In Electronics Engineering Technology Expiration Date: 1 2330A Current and Voltage 2 2330B Controlling Current
More informationDESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT
DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore
More informationDesigning Nano Scale CMOS Adaptive PLL to Deal, Process Variability and Leakage Current for Better Circuit Performance
International Journal of Innovative Research in Electronics and Communications (IJIREC) Volume 1, Issue 3, June 2014, PP 18-30 ISSN 2349-4042 (Print) & ISSN 2349-4050 (Online) www.arcjournals.org Designing
More informationPhase interpolation technique based on high-speed SERDES chip CDR Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li
5th International Conference on Computer Sciences and Automation Engineering (ICCSAE 2015) Phase interpolation technique based on high-speed SERDES chip CDR Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li
More information6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers
6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Bandwidth Constraints
More informationChapter 1 Semiconductors and the p-n Junction Diode 1
Preface xiv Chapter 1 Semiconductors and the p-n Junction Diode 1 1-1 Semiconductors 2 1-2 Impure Semiconductors 5 1-3 Conduction Processes in Semiconductors 7 1-4 Thep-nJunction 9' 1-5 The Meta1-Semiconductor
More informationA LOW POWER SINGLE PHASE CLOCK DISTRIBUTION USING 4/5 PRESCALER TECHNIQUE
A LOW POWER SINGLE PHASE CLOCK DISTRIBUTION USING 4/5 PRESCALER TECHNIQUE MS. V.NIVEDITHA 1,D.MARUTHI KUMAR 2 1 PG Scholar in M.Tech, 2 Assistant Professor, Dept. of E.C.E,Srinivasa Ramanujan Institute
More informationHigh Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers
High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers Michael H. Perrott March 19, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 High Speed Frequency
More informationECE1352. Term Paper Low Voltage Phase-Locked Loop Design Technique
ECE1352 Term Paper Low Voltage Phase-Locked Loop Design Technique Name: Eric Hu Student Number: 982123400 Date: Nov. 14, 2002 Table of Contents Abstract pg. 04 Chapter 1 Introduction.. pg. 04 Chapter 2
More informationA Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization
A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization 유병민 High-Speed Circuits & Systems Lab. 1/19 Content 1. Introduction 2. PLL jitter analysis 3. Design examples 4. Experimental results
More informationINF4420 Phase locked loops
INF4420 Phase locked loops Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline "Linear" PLLs Linear analysis (phase domain) Charge pump PLLs Delay locked loops (DLLs) Applications Introduction
More informationA SiGe 6 Modulus Prescaler for a 60 GHz Frequency Synthesizer
A SiGe 6 Modulus Prescaler for a 6 GHz Frequency Synthesizer Noorfazila Kamal,YingboZhu, Said F. Al-Sarawi, Neil H.E. Weste,, and Derek Abbott The School of Electrical & Electronic Engineering, University
More informationSelf-Biased PLL/DLL. ECG minute Final Project Presentation. Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas
Self-Biased PLL/DLL ECG721 60-minute Final Project Presentation Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas Outline Motivation Self-Biasing Technique Differential Buffer
More informationACTIVE SWITCHED-CAPACITOR LOOP FILTER. A Dissertation JOOHWAN PARK
FRACTIONAL-N PLL WITH 90 o PHASE SHIFT LOCK AND ACTIVE SWITCHED-CAPACITOR LOOP FILTER A Dissertation by JOOHWAN PARK Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment
More informationCHAPTER. delta-sigma modulators 1.0
CHAPTER 1 CHAPTER Conventional delta-sigma modulators 1.0 This Chapter presents the traditional first- and second-order DSM. The main sources for non-ideal operation are described together with some commonly
More informationA Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter
University of Pennsylvania ScholarlyCommons epartmental Papers (ESE) epartment of Electrical & Systems Engineering 7-1-2003 A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and
More informationThe steeper the phase shift as a function of frequency φ(ω) the more stable the frequency of oscillation
It should be noted that the frequency of oscillation ω o is determined by the phase characteristics of the feedback loop. the loop oscillates at the frequency for which the phase is zero The steeper the
More informationA Wide Tuning Range (1 GHz-to-15 GHz) Fractional-N All-Digital PLL in 45nm SOI
7- A Wide Tuning Range ( GHz-to-5 GHz) Fractional-N All-Digital PLL in 45nm SOI Alexander Rylyakov, Jose Tierno, George English 2, Michael Sperling 2, Daniel Friedman IBM T. J. Watson Research Center Yorktown
More informationTHE UNIVERSITY OF NAIROBI
THE UNIVERSITY OF NAIROBI ELECTRICAL AND INFORMATION ENGINEERING DEPARTMENT FINAL YEAR PROJECT. PROJECT NO. 085. TITLE: A PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER BY: TUNDULI W. MICHAEL F17/2143/2004. SUPERVISOR:
More informationA Wide-Bandwidth 2.4GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation. Outline
A Wide-Bandwidth 2.4GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation Ashok Swaminathan,2, Kevin J. Wang, Ian Galton University of California, San Diego, CA 2 NextWave Broadband, San
More informationDesign of CMOS Phase Locked Loop
2018 IJSRST Volume 4 Issue 2 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology Design of CMOS Phase Locked Loop Kaviyadharshini Sivaraman PG Scholar, Department of Electrical
More informationLESSON PLAN. SUBJECT: LINEAR IC S AND APPLICATION NO OF HOURS: 52 FACULTY NAME: Mr. Lokesh.L, Hema. B DEPT: ECE. Portions to be covered
LESSON PLAN SUBJECT: LINEAR IC S AND APPLICATION SUB CODE: 15EC46 NO OF HOURS: 52 FACULTY NAME: Mr. Lokesh.L, Hema. B DEPT: ECE Class# Chapter title/reference literature Portions to be covered MODULE I
More informationPLL Building Blocks. Presented by: Dean Banerjee, Wireless Applications Engineer
PLL Building Blocks Presented by: Dean Banerjee, Wireless Applications Engineer Phased-Locked Loop Building Blocks Basic PLL Operation VCO Dividers R Counter Divider Relation to Crystal Reference Frequency
More informationChapter 2 Architectures for Frequency Synthesizers
Chapter 2 Architectures for Frequency Synthesizers 2.1 Overview This chapter starts with an overview of the conventional frequency synthesis techniques as well as the hybrid architectures that can be used
More informationFrequency Synthesizers for RF Transceivers. Domine Leenaerts Philips Research Labs.
Frequency Synthesizers for RF Transceivers Domine Leenaerts Philips Research Labs. Purpose Overview of synthesizer architectures for RF transceivers Discuss the most challenging RF building blocks Technology
More informationPhase Locked Loops, Report Writing, Layout Tuesday, April 5th, 9:15 11:00
Phase Locked Loops, Report Writing, Layout Tuesday, April 5th, 9:15 11:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Last time and today, Tuesday 5th
More informationTen-Tec Orion Synthesizer - Design Summary. Abstract
Ten-Tec Orion Synthesizer - Design Summary Lee Jones 7/21/04 Abstract Design details of the low phase noise, synthesized, 1 st local oscillator of the Ten-Tec model 565 Orion transceiver are presented.
More informationDesign Technique of Phase-Locked Loop Frequency Synthesizer in CMOS Technology: A Review
Design Technique of Phase-Locked Loop Frequency Synthesizer in CMOS Technology: A Review Purushottamkumar T. Singh, Devendra S. Chaudhari Department of Electronics and Telecommunication Engineering Government
More informationLOW-VOLTAGE GHZ-RANGE FREQUENCY SYNTHESIZER
LOW-VOLTAGE GHZ-RANGE FREQUENCY SYNTHESIZER SUN YUAN SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING 2008 LOW-VOLTAGE GHZ-RANGE FREQUENCY SYNTHESIZER Sun Yuan School of Electrical and Electronic Engineering
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 7: Phase Detector Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda HW2 is due Oct 6 Exam
More informationA VCO-based analog-to-digital converter with secondorder sigma-delta noise shaping
A VCO-based analog-to-digital converter with secondorder sigma-delta noise shaping The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters.
More information6.976 High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators
6.976 High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott VCO Design for Wireless
More informationFPGA IMPLEMENTATION OF POWER EFFICIENT ALL DIGITAL PHASE LOCKED LOOP
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) ISSN 0976
More informationTHE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL
THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL IN CMOS TECHNOLOGY L. Majer, M. Tomáška,V. Stopjaková, V. Nagy, and P. Malošek Department of Microelectronics, Slovak Technical University, Ilkovičova 3, Bratislava,
More informationHong Kong University of Science and Technology. A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers
Hong Kong University of Science and Technology A -V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers A thesis submitted to The Hong Kong University of Science and Technology in
More informationDESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS
DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS Aman Chaudhary, Md. Imtiyaz Chowdhary, Rajib Kar Department of Electronics and Communication Engg. National Institute of Technology,
More informationChapter 13 Oscillators and Data Converters
Chapter 13 Oscillators and Data Converters 13.1 General Considerations 13.2 Ring Oscillators 13.3 LC Oscillators 13.4 Phase Shift Oscillator 13.5 Wien-Bridge Oscillator 13.6 Crystal Oscillators 13.7 Chapter
More informationLow Power Phase Locked Loop Design with Minimum Jitter
Low Power Phase Locked Loop Design with Minimum Jitter Krishna B. Makwana, Prof. Naresh Patel PG Student (VLSI Technology), Dept. of ECE, Vishwakarma Engineering College, Chandkheda, Gujarat, India Assistant
More informationCHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC
138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit
More informationLow distortion signal generator based on direct digital synthesis for ADC characterization
ACTA IMEKO July 2012, Volume 1, Number 1, 59 64 www.imeko.org Low distortion signal generator based on direct digital synthesis for ADC characterization Walter F. Adad, Ricardo J. Iuzzolino Instituto Nacional
More informationDESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS Nilesh D. Patel 1, Gunjankumar R. Modi 2, Priyesh P. Gandhi 3, Amisha P. Naik 4 1 Research Scholar, Institute of Technology, Nirma University,
More informationA 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS
A 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS Diary R. Sulaiman e-mail: diariy@gmail.com Salahaddin University, Engineering College, Electrical Engineering Department Erbil, Iraq Key
More informationPackage and Pin Assignment SSOP-6 (0.64mm pitch) OSCIN OSCOUT TXEN 3 VSS 4 TXOUT 5 VSS 6 7 MODIN 8 HiMARK SW DO RES RESB VREFP VSS Symbol
Low Power ASK Transmitter IC HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior
More informationDesign of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology
Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology Master thesis performed in Electronic Devices Author: Golnaz Ebrahimi Mehr Report number: LiTH-ISY-EX--13/4657--SE Linköping,
More informationA CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver. Hamid Rategh
A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver Hamid Rategh Center for Integrated Systems Stanford University OUTLINE Motivation Introduction
More informationEnergy Efficient and High Speed Charge-Pump Phase Locked Loop
Energy Efficient and High Speed Charge-Pump Phase Locked Loop Sherin Mary Enosh M.Tech Student, Dept of Electronics and Communication, St. Joseph's College of Engineering and Technology, Palai, India.
More informationAn Fpga Implementation Of N/N+1 Prescaler For A Low Power Single Phase Clock Distribution System
An Fpga Implementation Of N/N+1 Prescaler For A Low Power Single Phase Clock Distribution System V Satya Deepthi 1, SnehaSuprakash 2, USBK MahaLakshmi 3 1 M.Tech student, 2 Assistant Professor, 3 Assistant
More informationUnderstanding Delta-Sigma Data Converters
Understanding Delta-Sigma Data Converters Richard Schreier Analog Devices, Inc. Gabor C. Temes Oregon State University OlEEE IEEE Press iwiley- INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION Foreword
More informationAnalysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition
Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition P. K. Rout, B. P. Panda, D. P. Acharya and G. Panda 1 Department of Electronics and Communication Engineering, School of Electrical
More informationElectronic Warfare Receivers. and Receiving Systems. Richard A. Poisel ARTECH HOUSE BOSTON LONDON. artechhouse.com
Electronic Warfare Receivers and Receiving Systems Richard A. Poisel ARTECH HOUSE BOSTON LONDON artechhouse.com Table of Contents Preface Chapter 1 Receiving Systems and Receiving System Architectures
More informationElectronic Circuits EE359A
Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.
More informationWIRELESS TRANSCEIVER DESIGN
WIRELESS TRANSCEIVER DESIGN Mastering the Design of Modern Wireiess Equipment and Systems Ariel Luzzatto and Gadi Shirazi BICINTINHIAl ;I807J \ WILEY \ J2O07! ül,,, r BICINTINNIAL John Wiley & Sons, Ltd
More informationChapter 6. FM Circuits
Chapter 6 FM Circuits Topics Covered 6-1: Frequency Modulators 6-2: Frequency Demodulators Objectives You should be able to: Explain the operation of an FM modulators and demodulators. Compare and contrast;
More informationResearch on Self-biased PLL Technique for High Speed SERDES Chips
3rd International Conference on Machinery, Materials and Information Technology Applications (ICMMITA 2015) Research on Self-biased PLL Technique for High Speed SERDES Chips Meidong Lin a, Zhiping Wen
More informationMULTI-BIT DELTA-SIGMA MODULATION TECHNIQUE FOR FRACTIONAL-N FREQUENCY SYNTHESIZERS WOOGEUN RHEE
MULTI-BIT DELTA-SIGMA MODULATION TECHNIQUE FOR FRACTIONAL-N FREQUENCY SYNTHESIZERS BY WOOGEUN RHEE B.S., Seoul National University, 1991 M.S., University of California at Los Angeles, 1993 THESIS Submitted
More informationI. INTRODUCTION. Architecture of PLL-based integer-n frequency synthesizer. TABLE I DIVISION RATIO AND FREQUENCY OF ALL CHANNELS, N =16, P =16
320 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 56, NO. 2, FEBRUARY 2009 A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors
More information6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators
6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators Massachusetts Institute of Technology March 29, 2005 Copyright 2005 by Michael H. Perrott VCO Design for Narrowband
More informationML12202 MECL PLL Components Serial Input PLL Frequency Synthesizer
MECL PLL Components Serial Input PLL Frequency Synthesizer Legacy Device: Motorola MC12202 The ML12202 is a 1.1 GHz Bipolar monolithic serial input phase locked loop (PLL) synthesizer with pulse swallow
More information