An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Transcription

1 Analog Integr Circ Sig Process (2006) 48: DOI /s An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer Xiaojian Mao Huazhong Yang Hui Wang Received: 9 November 2005 / Revised: 17 February 2006 / Accepted: 21 February 2006 / Published online: 12 June 2006 C Science + Business Media, LLC 2006 Abstract Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta fractional-n frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch in sigma-delta fractional-n PLL frequency synthesizer. Most importantly, this model discloses that 6 db reduction of in-band phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical topologies of sigmadelta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design. Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the inband phase noise reduction of the sigma-delta frequency synthesizer. Keywords Charge pump. Fractional-N frequency synthesizer. Phase locked loop. Phase noise. Sigma-delta modulator X. Mao ( ) H. Yang H. Wang Department of Electronic Engineering, Tsinghua University, Beijing , P.R. China maoxj00@mails.tsinghua.edu.cn H. Yang yanghz@tsinghua.edu.cn H. Wang wangh@tsinghua.edu.cn 1. Introduction The sigma-delta fractional-n phase locked loop (PLL) frequency synthesizers [1, 2] are widely used in all kinds of circuits (Fig. 1). Any jitter or phase noise in the output of the PLL used in those applications generally degrades the performance margins of the system in which it resides. Therefore, it is of great concern to designers of such systems. A lot of methods have been carried out to analyze the phase noise and jitter from system level to circuit level in phase domain [3, 4] and voltage domain [5]. Though the fact that charge pump mismatch can induce spurious tone in the output of PLL has been studied [6] and known to a lot of designers, less attention has been paid to the analysis of in-band phase noise due to sigma-delta modulators (SDM). Assuming the timing error at the input of phase-frequency detector (PFD) is uniformly distributed, Riley et al. [7] presented the calculation of noise due to charge pump nonlinearities. However, as pointed out in [7], for higher order SDMs, the distribution of timing error at the input of PFD is Gaussian. Hence, an improved noise model is need. In [8], A simple analytical expression shows the level of SDM sequence noise caused by static charge-pump current mismatch through time-domain simulation. In this paper, we focus on this kind of noise and study it in frequency domain. An analytical, concise, and accurate model is proposed to predict the phase noise due to this mismatch. And numerical simulations [5, 9] are carried out to verify the accuracy and efficiency of this model. In Section 2, we analyze the in-band phase noise due to mismatch, and then model it by an analytical equation. The simulation results are presented in Section 3 and design considerations of sigma-delta fractional-n PLL are discussed in

2 224 Analog Integr Circ Sig Process (2006) 48: Fig. 1 Sigma-delta fractional-n frequency synthesizer Section 4. The conclusions, in Section 5, present a summary of our results and some recommendations to PLL designers. 2. Analysis of phase noise due to charge pump mismatch in sigma-delta PLL frequency synthesizer 2.1. Phase noise due to charge pump mismatch In a charge pump PLL shown in Fig. 1, the PFD converts the phase error presented to it into a voltage, and the charge pump converts this voltage into a correction current. Fig. 2(a) illustrates the equivalent circuit of the charge pump. I up and I dn are source and sink currents, respectively. In integral-n frequency synthesizer, when the PFD and charge pump are both ideal, the locked loop does not have any steady state phase error. In order to cancel the dead-zone due to the non-zero turn-on time of the charge pump, the PFD is designed to turn on I up and I dn at the same time for a short period, t, labeled in Fig. 2(b). If the sink and source currents of the charge pump are not properly matched, the sink or source currents should be turned on for an extra slice of time, t 1, labeled in Fig. 2(b). In the case shown in Fig. 2(b), (I up I dn )/I dn = t 1 / t should be held to eliminate the dead-zone pieces. However, the dead-zone cancellation generates spurs at the output of PLL. This has been studied in [6]. Consider the sigma-delta fractional-n frequency synthesizer. The output current in fractional-n frequency synthesizer changes in a range larger than that in integral-n frequency synthesizer because of the changing of the divider ratio controlled by SDM. The output current pattern of the charge pump is shown in Fig. 2(c), which can be divided into three parts as shown in Fig. 2(d) (f). The first part, shown in Fig. 2(d), has the same shape as the integral-n PLL and fulfills the dead-zone cancellation requirement. The second part, shown in Fig. 2(e), is the pattern of current in ideal charge pump, which is the average current of the real charge pump. And the third part, shown in Fig. 2(f), is the error (or mismatch) current. We assume the amplitudes of the up and down currents are I CP (1 + ρ e ) and I CP (1 ρ e ), respectively. Then the amplitudes of these patterns have an average Fig. 2 (a) Charge-pump model, (b) Current pattern in integral-n frequency synthesizer, (c) Current pattern in fractional-n frequency synthesizer, (d) Current pattern for dead-zone cancellation, (e) Ideal charge pump current for SDM, and (f) Mismatch charge pump current for SDM current of I CP and an error current of I CP ρ e. Here we call ρ e mismatch ratio. The first part of the pattern is similar to that in integral-n frequency synthesizer, which is related to the spur in the output. The second part is the ideal current pattern, which is only related to the SDM. The third part is a phase modulated noise with Gaussian distribution, which comes from the joint effect of charge pump mismatch and SDM quantization noise. This is the main topic discussed in the following sections Simple model of charge pump with mismatch Fig. 3 shows a phase domain model of PLL proposed in [10]. Because the spur due to charge pump mismatch has been well

3 Analog Integr Circ Sig Process (2006) 48: Fig. 4 Spectrum of SDM after absolute converter Fig. 3 Linear model of PLL frequency synthesizer studied, we pay attention to the third part of current pattern in this paper. The charge pump model with this mismatch is marked by dot-filled blocks in Fig. 3. The error current due to mismatch can be expressed in the following equation, N cp sdm (t) = ρ e I CP φ (t) The absolute value operation to φ(t) is a non-linear system and can not be expressed as a transfer function in neither Laplace nor Fourier forms. It is really hard to get an exact phase noise distribution at its output. Because the mean value of φ(t) is a fixed value, it can be compensated by turning on the up or down current source of the charge pump for a fixed time interval. This kind of interval can be considered as a pulse to compensate a fixed leakage of charge pump, and this is the out-of-band spur generated at offset frequency with n (n = 1, 2, 3, 4,...). This kind of spur is studied in [6]. Therefore, we ignore all the other high-order momentum, and only consider the effect of standard deviation of φ(t). In this paper, we use numerical simulation to find a bridge between the output and input of an absolute-value system. The numerical approximation is made by MATLAB. When we input the system data stream of N sdm (Fig. 3)ofPLL loop with MASH SDM [2], the output is a nearly white noise. We are especially interested in low frequency segment, for the spectrum is horizontal in this segment, in contrast to high frequency segment where noise is fitered out by the loop filter. One simulation result is shown in Fig. 4. The amplitude of power spectrum density of the output of absolute system is related to the SDM used in the PLL, and it varies slightly with the data width and input level of SMD. The simulation is carried out for different SMDs in some published papers [1, 11 17]. The width of these SDMs is set to be 16, 20, 24, 28, and 32 bits, respectively. The sample input levels are randomly selected to be 0.016, 0.235, 0.418, 0.529, 0.708, and 0.951, (1) respectively. σ ( N sdm ), the standard deviation of these SDMs, changes less than 10% and the average is listed in Table 1. Now we return to the transfer function of the PLL system. The forward gain is G ( f ) = I CP Z LF ( j f ) K VCO j f The feedback transfer function can be expressed as H( f ) = 1 N + α where N is the integral part of divider ratio and α is the fractional part. The first order open loop gain is T ( f ) = G ( f ) H ( f ) (4) Then, omitting the noise from other modules, we have the following relationship φ PLL ( f ) = G( f ) 1 + T ( f ) φ ref ( f ) + G( f ) / ICP 1 + T ( f ) N cp sdm( f ) Table 1 (2) (3) T ( f ) 1 + T ( f ) N sdm ( f ) (5) Standard deviation of N sdm and N sdm in SDMs No Architecture σ (N sdm ) σ ( N sdm ) 1 MASH [11] MASH-2-1 [12] MASH-1-2 [13] Single-stage multiple feedback [14] 5 Proposed by Riley [1] Proposed by Muer [15] &Rhee[16] 7 Notch-Filter SDM [17]

4 226 Analog Integr Circ Sig Process (2006) 48: where N cp sdm ( f ) is the noise due to charge pump mismatch, and N sdm ( f ) is due to the quantization noise of SDM. When we refer to a MASH SDM, the quantization noise transfer function is Q N (z) = (1 z 1 ) 3 (6) and 1 N sdm ( f ) = 12 ( Q N (z) z 1 ) 1 z z=e 1 j f (7) Then, we pay attention to the delta phase of phase-frequency detector, and it can be expressed as ( φ ( f ) = T ( f ) ) φ ref ( f ) G ( f )/ I CP 1 + T ( f ) H ( f ) N cp sdm ( f ) + H ( f ) 1 + T ( f ) N sdm ( f ) T ( f ) 1 + T ( f ) ρ e φ ( f ) + H ( f ) 1+ T ( f ) N sdm ( f ) (rad/hz) where φ ( f ) is frequency domain representation of φ (t). On the right side of the equation, since φ ref ( f ) is usually almost clean, the first term can be omitted. Also, since the charge pump mismatch ρ e is usually at the grade of 10 2, and σ ( φ ) is always less than σ ( φ), ρ e φ ( f ), compared to φ ( f ), can also be omitted. The power spectrum density of N sdm congregates to high frequency part, and (8) can be approximated as: φ ( f ) H ( f ) 1 + T ( f ) N sdm ( f ) H ( f ) N sdm ( f ) = 1 N + α N sdm ( f )(rad/hz) From (9), we can get the next two equations, σ ( φ) = 1 N + α σ (N sdm) (10) and σ ( φ ) = 1 N + α σ ( N sdm ) (11) Now we return to the noise in charge pump N cp sdm.its power spectrum density can be expressed as S cp sdm ( f ) = ρ e I CP 2 (σ ( φ )) 2 1 (A 2 /Hz) (8) (9) (12) Referring to (5), we get the phase spectrum of output noise due to charge pump mismatch, S PLL,cp sdm ( f ) = G ( f ) 1 + T ( f ) ρ 2 e (σ ( φ )) 2 1 T ( f ) 1 + T ( f ) ρ 2 e (σ ( N sdm )) 2 1 (rad 2 /Hz) (13) Because T ( f ) / (1 + T ( f )) is a low pass filter, its in-band gain equals to 1. The output phase noise due to charge pump mismatch is determined by σ ( N sdm ), relative mismatch ratio ρ e, and reference frequency. From Eq. (13), we can see that if σ ( N sdm ) and ρ e can be reduced, the phase noise due to the charge pump can be reduced, too. So when the reference frequency is selected, correct selection of SDM architecture and optimization of charge pump are important in PLL output phase noise cancellation. From another perspective, increasing reference frequency can also reduce this kind of noise. 3. Simulation experiments Using the behavioral model proposed in [5, 9], we carry out simulations to verify the equations derived in the former section. The simulation is based on a sigma-delta PLL frequency synthesizer with and f out of 12 MHz and MHz, respectively. First, we set the loop bandwidth f LBW to 0.1 MHz and the charge pump mismatch ratio ρ e to 2%. Other noises are omitted. In this simulation, the SDM is of a MASH structure proposed in [11], and the standard deviation of N sdm is The output phase noise is shown in Fig. 5. The simulation result matches the results calculated from equations in the former section for both low offset frequency region and higher frequency region. The former one is the contribution due to charge pump mismatch, and the latter is due to the SDM. In the second simulation, we keep the parameters the same as in the first one but replace the SDM with the SDM proposed by Rhee et al. in [16]. The simulated phase noise is shown in Fig. 6. The phase noise in high frequency offset is higher than that in the first simulation because of the difference of quantization noise. In the lower offset frequency, the difference of phase noise is due to σ ( N sdm ). Changing the charge pump mismatch ratio to 1% but keeping other parameters unchanged, in the third simulation, we are convinced that halved mismatch ratio makes 6 db reduction in the amplitude of mismatch produced phase noise in low frequency offset, which agrees with Eq. (13). In the fourth simulation, we change the bandwidth of the phase locked loop to 0.05 MHz, 50% of the bandwidth in the first

5 Analog Integr Circ Sig Process (2006) 48: Fig. 5 MASH [11], f LBW = 0.1 MHz, ρ e = 2% Fig. 6. SDM is proposed by Rhee [16], f LBW = 0.1 MHz, ρ e = 2% simulation by modifying the parameters of low filter. This does not affect the phase noise level in lower frequency offset, but obviously reduces the high frequency offset phase noise due to the quantization noise of the SDM. PLL loop bandwidth can be changed by varying voltage controlled oscillator (VCO) frequency gain (K VCO ), charge pump current (I CP ), and loop filter poles and zeros. Also we change the loop bandwidth in other two ways, varying K VCO and I CP, and the simulation results are the same as the first one. What we should pay attention to is that when K VCO or I CP is modified, the other parameters are also recalculated by means of the method mentioned in [6]. Based on the fourth simulation result, the reference frequency is changed to 6 MHz in the fifth simulation. One can easily conclude that the in-band phase noise to charge pump mismatch is doubled when the reference frequency is halved. It is the result that we expected in Eq. (13). The figures for the last three experiments are omitted to compress the manuscript length. noise. The charge pump should be carefully designed. Besides, the topology of SDM and the loop bandwidth of PLL are also important to get a low phase noise frequency synthesizer. When we design fractional-n frequency synthesizers with SDMs, loop bandwidth should be optimized according to the topology of SDMs to suppress the quantization noise at higher frequency. The quantization noises shaped by different SDMs are different. Fig. 7 shows the noise transfer function of some typical SDMs proposed in literatures [1, 11 17]. Because the SDM proposed by Fahim in [17] has a wider low-noise region, wider loop bandwidth can be allowed to achieve faster locking and better phase noise due to SDM itself. On the other hand, as summarized in Table 1, σ ( N sdm ) of SDMs proposed by Riley et al. [1] is the minimum. So when the requirement for loop bandwidth is not so critical, the SDM proposed in [1] can be used to relax the matching requirement to charge pump. If otherwise, the SDM suitable for wideband applications should be used. The analytical model proposed in this paper discloses that the charge pump mismatch is an important factor to the in-band phase noise of PLL, thus it should be elaborately designed to make the source and sink currents fully matched. A design example is presented to demonstrate how to determine the requirement of charge pump matching. The frequency synthesizer has a loop bandwidth of 0.05 MHz, of 12 MHz, and f out of MHz. We also assume the phase noise of the reference oscillator and VCO are 137 dbc/hz@10 KHz and 100 dbc/hz@100 KHz, respectively. The charge pump mismatching is set to be 2%. With phase domain models in literature and this paper, the total output phase noise of PLL and phase noise due to all the major blocks in Fig. 3 are obtained and shown in Fig. 8. In the low frequency offset, the output phase noise is dominated by the reference oscillator, while the quantization noise of SDM is the dominant one at high frequency offset. However, at the in-band frequency offset, no one noise source can significantly dominate others. As is shown in [7], there are five major sources of in-band phase noise, and the phase noise due to charge-pump mis- 4. Design example From the analysis above, we can see that the charge pump mismatch is the dominant factor to reduce the in-band phase Fig. 7 Quantization noise shaping by different SDMs

6 228 Analog Integr Circ Sig Process (2006) 48: Fig. 8 A design instance for fractional-n frequency synthesizer match is an important one. Our analytical model can be applied to estimating in-band noise due to charge-pump mismatch. 5. Conclusion In this paper, we have analyzed the in-band phase noise due to the charge pump mismatch in sigma-delta fractional-n frequency synthesizer. A simple model has been proposed to express the relation between in-band phase noise and charge pump mismatch, and the behavioral simulation is carried out to verify it. Our model shows that the output phase noise due to charge pump mismatch is determined by σ ( N sdm ), relative mismatch ratio ρ e, and reference frequency.ifσ( N sdm ) and ρ e can be reduced, the phase noise due to the charge pump can be reduced, too. So when the reference frequency is selected, correct selection of SDM architecture and optimization of charge pump are important in PLL output phase noise cancellation. From another angle, increasing reference frequency can also reduce this kind of noise. A design example is presented to show how to balance the charge pump and other functional blocks. References 1. T.A.D. Riley, M.A. Copeland, and T.A. Kwasniewski, Deltasigma modulation in fractional-n frequency synthesis. IEEE J. Solid-State Circuits, vol. 28, no. 5, pp , May B. Miller and R.J. Conley, A multiple modulator fractional divider. IEEE Trans. Instrum. Meas., vol. 40, no. 3, pp , Mar M.H. Perrott, M.D. Trott, and C.G. Sodini, A modeling approach for fractional-n frequency synthesizers allowing straightforward noise analysis. IEEE J. Solid-State Circuits, vol. 37, no. 8, pp , B. De Muer and M.S.J. Steyaert, On the analysis of fractional- N frequency synthesizers for high-spectral purity. IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, vol. 50, no. 11, pp , Nov K. Kundert, Predicting the phase noise and jitter of PLL-based frequency synthesizers. Availabe from D. Banerjee, PLL performance, simulation and design. Availabe from T.A.D. Riley, N.M. Filiol, Q. Du, and J. Kostamovaara, Techniques for in-band phase noise reduction in synthesizers. IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, vol. 50, no. 11, pp , H. Arora, N. Klemmer, J.C. Morizio, and P.D. Wolf, Enhanced phase noise modeling of fractional-n frequency synthesizers. IEEE Trans. Circuits Syst. I: Reular papers, vol. 52, no. 2, pp , Feb X. Mao, H. Yang, and H. Wang, Behavioral modeling and simulation of jitter and phase noise in fractional-n PLL frequency synthesizer. In Proc. IEEE Behavioral Modeling and Simulation Conf., 2004, pp I. Galton, Delta-Sigma fractional-n phase locked loops. In B. Razavi Ed. Phase-Locking in High Performance Systems: From Devices to Architectures. Piscataway, N.J, 2003, pp T. Bourdi, A. Borjak, and I. Kale, A delta-sigma frequency synthesizer with enhanced phase noise performance. in Instrumentation and Measurement Technology Conference, IMTC/2002. Proceedings of the 19th IEEE, 2002, Vol.1, pp C.-H. Heng and B.-S. Song, A 1.8-GHz CMOS fractional-n frequency synthesizer with randomized multiphase VCO. IEEE J. Solid-State Circuits, vol. 38, no. 6, pp , L. Sun, T. Lepley, F. Nozahic, A. Bellissant, T. Kwasniewski, and B. Heim, Reduced complexity, high performance digital delta-sigma modulator for fractional-n frequency synthesis. In Circuits and Systems, ISCAS 99. Proceedings of the 1999 IEEE International Symposium on, 1999, Vol. 2, pp T. Musch, N. Rolfes, and B. Schiek, A highly linear frequency ramp generator based on a fractional divider phase-locked-loop. IEEE Trans. Instrum. Meas., vol. 48, no. 2, pp , Apr B. De Muer and M.S.J. Steyaert, A CMOS monolithic controlled fractional-n frequency synthesizer for DCS IEEE J. Solid-State Circuits, vol. 37, no. 7, pp , W. Rhee, B.S. Song, and A. Ali, A 1.1-GHz CMOS fractional-n frequency synthesizer with a 3-b third-order modulator. IEEE J. Solid-State Circuits, vol. 35, no. 10, pp , Oct A.M. Fahim and M.I. Elmasry, A wideband sigma-delta phaselocked-loop modulator for wireless applications. IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, vol. 50, no. 2, pp , Feb Xiaojian Mao was born in Jiangsu Province, China, in He received the B.S. degree in electronic engineering from Jilin University, Changchun, China, in He is currently pursuing the Ph.D. degree in circuits and systems at Department of Electronic Engineering of Tsinghua University, Beijing, China. His current research includes frequency synthesizers and phase-locking and clock recovery for high-speed data communications. And His PhD thesis title is Design and Analysis of Sigma-Delta Fractional-N PLL Frequency Synthesizer.

7 Analog Integr Circ Sig Process (2006) 48: Huazhong Yang received BS, MS, and PhD Degrees in electronics engineering from Tsinghua University, Beijing, in 1989, 1993, and 1998, respectively. He is a Professor and Head of the Circuits and Systems Division in the Department of Electronic Engineering at Tsinghua University, Beijing. His research interests include CMOS radio-frequency integrated circuits, VLSI system structure for digital communications and media processing, low-voltage and low-power circuits, and computer-aided design methodologies for system integration. He has authored and co-authored 6 books and more than 100 journals and conference papers. He was the winner of Chinas National Palmary Young Researcher Award in Hui Wang received the B.S. degree from Department of Radio Electronics, from Tsinghua University, Beijing, China. She was a visiting scholar at Stanford University, CA, USA from February 1991 to September Currently she is a Professor of the Circuits and Systems Division in the Department of Electronic Engineering and the deputy dean of academic affairs office at Tsinghua University, Beijing, China. Her research interests include modeling and simulation of radio-frequency CMOS integrated circuits, automatic design methodology for low voltage and low-power integrated circuits, and interconnect modeling and synthesis for deep submicron system-on-a-chip. She has authored and co-authored 4 books and over 70 papers. She was a primary research of TADS-C4 which gained a third-grade prize for the national progress in science and technology in China in 1993.