6.776 High Speed Communication Circuits Lecture 23. Design of Fractional-N Frequency Synthesizers and Bandwidth Extension Techniques

Transcription

1 6.776 High Speed Communication Circuits Lecture 23 Design of Fractional-N Frequency Synthesizers and Bandwidth Extension Techniques Michael Perrott Massachusetts Institute of Technology May, 2005 Copyright 2005 by Michael H. Perrott

2 Outline of PLL Lectures Integer-N Synthesizers - Basic blocks, modeling, and design - Frequency detection, PLL Type Noise in Integer-N and Fractional-N Synthesizers - Noise analysis of integer-n structure - Sigma-Delta modulators applied to fractional-n structures - Noise analysis of fractional-n structure Design of Fractional-N Frequency Synthesizers and Bandwidth Extension Techniques - PLL Design Assistant Software - Quantization noise reduction for improved bandwidth and noise 2

3 Design of Frequency Synthesizers Focus on fractional-n architecture since it is essentially a super set of other PLL synthesizers - If we can design this structure, we can also design classical integer-n systems ref(t) PFD e(t) Charge Pump Loop Filter v(t) out(t) VCO div(t) Divider N sd [m] Σ Modulator N[m] 3

4 Frequency-domain Model Φ ref [k] PFD Tristate: α=1 XOR: α=2 α T 2π e(t) C.P. I cp Loop Filter H(f) v(t) VCO K V jf Φ out (t) Φ div [k] 1 N nom Φ d [k] Divider 1 T n[k] 2π z-1 z=e j2πft 1 - z-1 Perrott et. al. JSSC, Aug Closed loop dynamics parameterized by

5 Review of Classical Design Approach Given the desired closed-loop bandwidth, order, and system type: 1. Choose an appropriate topology for H(f) Depends on order, type 2. Choose pole/zero values for H(f) as appropriate for the required bandwidth 3. Adjust the open-loop gain to achieve the required bandwidth while maintaining stability Plot gain and phase bode plots of A(f) Use phase (or gain) margin criterion to infer stability 5

6 Example: First Order, Type I with Parasitic Poles Open loop gain increased 0 db -90 o -165 o -180 o 20log A(f) \A(f) Evaluation of Phase Margin f p f p2 f p3 C B A f PM = 72 o for A PM = 51 o for B PM = -12 o for C Closed Loop Pole Locations of G(f) Non-dominant poles Dominant pole pair A A B B Im(s) 0 C Re(s) -20 o -315 o C 6

7 First Order, Type I: Frequency and Step Responses Closed Loop Frequency Response Closed Loop Step Response 0 db B C 2 C A B 1 A 0 Frequency Time 7

8 Limitations of Open Loop Design Approach Constrained for applications which require precise filter response Complicated once parasitic poles are taken into account Poor control over filter shape Inadequate for systems with third order rolloff - Phase margin criterion based on second order systems Closed loop design approach: Directly design G(f) by specifying dominant pole and zero locations on the s-plane (pole-zero diagram) 8

9 Closed Loop Design Approach: Overview G(f) completely describes the closed loop dynamics - Design of this function is the ultimate goal Performance Specifications {type, f o,...} Open Loop Design Approach A(f) \A(f) {K, f za, f pa,...} G(f) = A(f) = A(f) 1+A(f) G(f) 1-G(f) G(f) {f z, f p,...} Closed Loop Design Approach Instead of indirectly designing G(f) using plots of A(f), solve for G(f) directly as a function of specification parameters Solve for A(f) that will achieve desired G(f) Account for the impact of parasitic poles/zeros 9

10 Closed Loop Design Approach: Implementation Download PLL Design Assistant Software at Read accompanying manual Algorithm described by C.Y. Lau et. al. in Fractional-N Frequency Synthesizer Design at the Transfer Function Level Using a Direct Closed Loop Realization Algorithm, Design Automation Conference,

11 PLL Design Assistant 11

12 Definition of Bandwidth, Order, and Shape for G(f) 0 G(f) (db) f o f rolloff = -20n db/decade Bandwidth f o - Defined in asymptotic manner as shown Order n - Defined according to the rolloff characteristic of G(f) Shape - Defined according to standard filter design methodologies Butterworth, Bessel, Chebyshev, etc. 12

13 Definition of Type Type I: one integrator in PLL open loop transfer function - VCO adds on integrator - Loop filter, H(f), has no integrators Type II: two integrators in PLL open loop transfer function - Loop filter, H(f), has one integrator Φ ref (t) PFD Tristate: α=1 XOR-based: α=2 α 2π e(t) Loop Filter H(f) v(t) VCO Kv jf Φ out (t) Φ div (t) Divider 1 N 13

14 Loop Filter Transfer Function Vs Type and Order of G(f) H(s) Topology For Different Type and Orders of G(f) Order 1 Order 2 Order 3 Type I K LP K LP 1+s/w p K LP 1+s/(w p Q p )+(s/w p ) 2 K LP 1+s/w z s K LP Type II 1+s/w z s(1+s/w p ) K LP (1+s/w z ) s(1+s/(w p Q p )+(s/w p ) 2 ) where K LP = K N nom K v I cp α Practical PLL implementations limited to above - Prohibitive analog complexity for higher order, type Open loop gain, K, will be calculated by algorithm - Loop filter gain related to open loop gain as shown above Calculated from software 1

15 Passive Topologies to Realize a Second Order PLL Type I, Order 2 Type II, Order 2 DAC I dac I in V out I in V out R 1 C 1 C 2 C 1 R 1 V out R 1 = I in 1+sR 1 C 1 V out 1 = I in s(c 1 +C 2 ) 1+sR 1 C 2 1+sR 1 C DAC is used for Type I implementation to coarsely tune VCO - Allows full range of VCO to be achieved 15

16 Passive Topologies to Realize a Third Order PLL Type I, Order 3 Type II, Order 3 DAC I dac I in L 1 V out I in L 1 V out R 1 C 1 C 2 C 1 R 1 V out R 1 = I in 1+sR 1 C 1 +s 2 L 1 C 1 V out 1 = I in s(c 1 +C 2 ) 1+sR 1 C 2 1+sR 1 C +s 2 L 1 C where C = C 1 C 2 /(C 1 +C 2 ) Inductor is necessary to create a complex pole pair - Must be implemented off-chip due to its large value 16

17 Problem with Passive Loop Filter Implementations Large voltage swing required at charge pump output - Must support full range of VCO input Non-ideal behavior of inductors (for third order G(f) implementations) - Hard to realize large inductor values - Self resonance of inductor reduces high frequency attenuation C p L 1 L 1 Alternative: active loop filter implementation 17

18 Guidelines for Active Loop Filter Design Use topologies with unity gain feedback in the opamp - Minimizes influence of opamp noise R 1 R 2 Perform level shifting in feedback of opamp - Fixes voltage at charge pump output Use current to achieve level shift Level Shift Element 2 V noise,in V out Set nominal voltage to V ref V out V ref Prevent fast edges from directly reaching opamp inputs - Will otherwise cause opamp to be driven into nonlinear region of operation 18

19 Active Topologies To Realize a Second Order PLL Type I, Order 2 Type II, Order 2 DAC I dac R 2 I in C 2 C 3 V out V ref I in I in V out R 1 C 1 R 1 C 1 V ref V ref V out R 1 = I in 1+sR 1 C 1 V out 1+sR 1 (C 1 +C 2 +C 3 ) = I in sc 2 (1+sR 1 C 1 ) Follows guidelines from previous slide Charge pump output is terminated directly with a high Q capacitor - Smooths fast edges from charge pump before they reach the opamp input(s) 19

20 Active Topologies To Realize a Third Order PLL Type I, Order 3 Type II, Order 3 C 2 C 2 R 1 R 2 C 3 R 1 R 2 DAC I dac C 1 I in C 1 I in V out V out V ref V ref V out -R 2 = I in 1+s(R 1 +R 2 )C 2 +s 2 R 1 R 2 C 1 C 2 V out -1 = I in s(c 1 +C 2 ) 1+sR 2 C 3 1+sC (R 1 (1+C 1 /C 3 )+R 2 )+s 2 R 1 R 2 C 1 C where C = C 2 C 3 /(C 2 +C 3 ) Follows active implementation guidelines from a few slides ago 20

21 Example Design Type II, 3 rd order, Butterworth, f o = 300kHz, f z /f o = No parasitic poles Required loop filter transfer function can be found from table: 21

22 Use PLL Design Assistant to Calculate Parameters 22

23 Resulting Step Response and Pole/Zero Diagram 23

24 Impact of Open Loop Parameter Variations Open loop parameter variations can be directly entered into tool 2

25 Resulting Step Responses and Pole/Zero Diagrams Impact of variations on the loop dynamics can be visualized instantly and taken into account at early stage of design 25

26 Design with Parasitic Pole Include a parasitic pole at nominal value f p1 = 1.2MHz K, f p and Q p are adjusted to obtain the same dominant pole locations 26

27 Noise Estimation Phase noise plots can be easily obtained - Jitter calculated by integrating over frequency range 27

28 Calculated Versus Simulated Phase Noise Spectrum Without parasitic pole: Output Phase Noise of Synthesizer SD Noise Detector Noise VCO Noise Total Noise Simulated Noise Simulated Phase Noise of SD Freq. Synth. L(f) (dbc/hz) L(f) (dbc/hz) Frequency Offset (Hz) RMS jitter = ps Frequency Offset (Hz) 28

29 Calculated Versus Simulated Phase Noise Spectrum With parasitic pole at 1.2 MHz: Output Phase Noise of Synthesizer SD Noise Detector Noise VCO Noise Total Noise Simulated Noise Simulated Phase Noise of SD Freq. Synth. L(f) (dbc/hz) L(f) (dbc/hz) Frequency Offset (Hz) RMS jitter = 1.057ps Frequency Offset from Carrier (Hz) 29

30 Noise under Open Loop Parameter Variations Output Phase Noise of Synthesizer SD Noise Detector Noise VCO Noise Total Noise L(f) (dbc/hz) Frequency Offset (Hz) RMS jitter = ps (min), ps (max) Impact of open loop parameter variations on phase noise and jitter can be visualized immediately 30

31 Conclusion New closed loop design approach facilitates: - Accurate control of closed loop dynamics Bandwidth, Order, Shape, Type - Straightforward design of higher order PLL s - Direct assessment of impact of parasitic poles/zeros Techniques implemented in a GUI-based CAD tool Beginners can quickly come up to speed in designing PLL s Experienced designers can quickly evaluate the performance of different PLL configurations 31

32 Bandwidth Extension of Fractional-N Frequency Synthesizers

33 Impact of Σ Quantization Noise on Synth. Output Ref PFD Loop Filter Out Div N/N+1 Frequency Selection M-bit Σ Modulator 1-bit Quantization Noise Spectrum Output Spectrum Noise Frequency Selection F out Σ PLL dynamics Lowpass action of PLL dynamics suppresses the shaped Σ- quantization noise 33

34 Impact of Increasing the PLL Bandwidth Ref PFD Loop Filter Out Div N/N+1 Frequency Selection M-bit Σ Modulator 1-bit Quantization Noise Spectrum Output Spectrum Noise Frequency Selection F out Σ PLL dynamics Higher PLL bandwidth leads to less quantization noise suppression Tradeoff: Noise performance vs PLL bandwidth 3

35 Recent Approaches to Bandwidth Extension [1] C. Park, O. Kim, and B. Kim, A 1.8GHz Self- Calibrated Phase-Locked Loop with Precise I/Q Matching, IEEE JSSC, May [2] K. Lee, et. al., A Single Chip 2.GHz Direct- Conversion CMOS Receiver for Wireless Local Loop Using Multiphase Reduced Frequency Conversion Technique, IEEE JSSC, May [3] S. Pamarti, L. Jansson, and I. Galton, A Wideband 2.GHz Delta-Sigma Fractional-N PLL With 1Mb/s In- Loop Modulation, IEEE JSSC, Jan 200 [] E. Temporiti, et. al., A 700kHz Bandwidth Σ Fractional-N Frequency Synthesizer with Spurs Compensation and Linearization Techniques for WCDMA Applications, IEEE JSSC, Sept 200 We will focus on our own approach in this talk 35

36 Examine Classical Fractional-N Signals ref(t) div(t) e(t) S e (f) Fractional Spurs 0 F ref f Goal: eliminate the fractional spurs 36

37 Method 1: Vertical Compensation ref(t) div(t) e(t) e(t) S e (f) 0 F ref f Fill in pulses so that they are constant area - Fractional spurs are eliminated! 37

38 38 Method 2: Horizontal Compensation Use constant width pulses of varying height to achieve constant area pulses - Largely eliminates fractional spurs e(t) f 0 F ref S e (f) e(t) div(t) ref(t) e(t)

39 Implementation of Horizontal Cancellation We begin with the basic fractional-n structure ref(t) PFD e 2 (t) Loop Filter out(t) div(t) ref(t) div(t) e 2 (t) Reg Divider N[k] 39

40 Add a Second PFD with Delayed Divider Signal ref(t) delayed div(t) ref(t) e 1 (t) delayed div(t) PFD PFD e 1 (t) e 2 (t) Loop Filter out(t) div(t) ref(t) div(t) e 2 (t) Reg Reg Divider N[k] 0

41 Scale Error Pulses According to Accumulator Residue ref(t) delayed div(t) ref(t) delayed div(t) div(t) ε[k]e 1 (t) PFD PFD ref(t) ε[k] 1-ε[k] ε[k]e 1 (t) Loop Filter (1-ε[k])e 2 (t) out(t) div(t) (1-ε[k])e 2 (t) Reg Reg Divider frac[k] Accum residue[k] = ε[k] 1

42 A Closer Look at Adding the Scaled Error Pulses ref(t) delayed div(t) PFD ε[k] ε[k]e 1 (t) e(t) PFD div(t) (1-ε[k])e 2 (t) ε[k]e 1 (t) e(t) 1-ε[k] (1-ε[k])e 2 (t) Goal keep area constant for each pulse - It s easier to see this from a slightly different viewpoint 2

43 Alternate Viewpoint The sum of scaled pulses can now be viewed as horizontal cancellation ref(t) delayed div(t) PFD ε[k] ε[k]e 1 (t) e(t) PFD div(t) (1-ε[k])e 2 (t) ε[k]e 1 (t) e(t) 1-ε[k] (1-ε[k])e 2 (t) e(t)

44 Implementation of Pulse Scaling Operation Direct output of a differential current DAC into two charge pumps ref(t) delayed div(t) div(t) PFD PFD Charge Pump ε[k] Charge Pump ε[k]e 1 (t) Loop Filter (1-ε[k])e 2 (t) 1-ε[k] Residue[k] 2 n Y. Dufour US Patent 6,130, (filing date) Issue: practical non-idealities kill performance

45 Primary Non-idealities of Concern Delay mismatch T vco + ref(t) delayed div(t) PFD Charge Pump ε[k] Incomplete Fractional Spur Suppression e(t) Residue[k] div(t) PFD 1-ε[k] Charge Pump S e (f) 0 F ref f 2 n DAC current element mismatch Proposed approach: dramatically reduce impact of these non-idealities using mixed-signal processing techniques 5

46 Eliminate Impact of DAC Current Element Mismatch Apply standard DAC noise shaping techniques to shape mismatch noise to high frequencies - See Baird and Fiez, TCAS II, Dec 1995 Residue[k] n+1 DAC Mismatch Shaping ε[k] 2 n ref(t) delayed div(t) div(t) PFD PFD ε[k] 1-ε[k] Charge Pump Charge Pump ε[k]e 1 (t) Loop Filter (1-ε[k])e 2 (t) Allows up to 5% mismatch between unit elements without degrading our desired performance targets 6

47 Eliminate Impact of Timing Mismatch Swap paths between divider outputs in a pseudorandom fashion - Need to also swap ε[k] and 1-ε[k] sequence T vco + Residue[k] delayed div(t) vco_out(t) div(t) ref(t) Timing Mismatch Compensation and Re-synchronization ε[k] PFD PFD Charge Pump ε[k] Charge Pump 1-ε[k] ε[k]e 1 (t) Loop Filter (1-ε[k])e 2 (t) n+1 DAC Mismatch Shaping 2 n Allows up to 5 ps mismatch without degrading our desired performance targets 7

48 Improve Horizontal Cancellation Performance Sampling circuit accumulates error pulses before passing their information to the loop filter - A common analog trick used for decades delayed div(t) div(t) Residue[k] vco_out(t) n+1 Timing Mismatch Compensation and Re-synchronization DAC Mismatch Shaping ε[k] 2 n ref(t) PFD PFD Charge Pump ε[k] 1-ε[k] Charge Pump Sampler S e (f) Loop Filter 0 F ref f Eliminates issue of having non-square error pulse shapes 8

49 For More Details on This Approach Theory and simulations presented in TCAS II paper - Meninger and Perrott, TCASII, Nov 2003 delayed div(t) div(t) vco_out(t) Timing Mismatch Compensation and Re-synchronization ref(t) PFD PFD Charge Pump ε[k] Charge Pump Sampler Loop Filter Residue[k] ε[k] 1-ε[k] S e (f) n+1 DAC Mismatch Shaping 2 n 0 F ref f 9

50 Design and Simulation of PFD/DAC Synthesizer ref(t) div(t) PFD/DAC Loop Filter out(t) Reg Reg Divider frac[k] Accum residue[k] = ε[k] Step 1: Derive analytical model Step 2: Design at system level Step 3: Simulate at system level (CppSim) Step : Simulate at transistor level (SPICE) Iterate between all of these steps in practice 50

51 Analytical Model of PFD/DAC Fractional-N PLL PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec Φ ref [k] PFD Tristate: α=1 T α 2π 0 e n (t) 1/T e(t) f C.P. I cp Loop Filter H(f) v(t) VCO K V jf 0 Φ vn (t) f Φ out (t) Φ div [k] Σ Quantization Noise S q (e j2πft ) 0 : 1 (1/2) n n[k] f 1 N nom Φ d [k] Divider 2π z-1 z=e j2πft 1 - z-1 1 T Based on: Perrott et. al., JSSC, Aug n-bit PFD/DAC is reduced from 1 to (1/2) n 51

52 Parameterized PLL Model Σ Quantization Noise S q (e j2πft ) PFD-referred Noise S En (f) 0 1/T E n (t) f VCO-referred Noise S Φvn (f) 0 Φ vn (t) -20 db/dec f f o 2π α Nnom G(f) f o 1-G(f) 0 : 1 (1/2) n n[k] f 2π z z -1 Φ n [k] z=e j2πft T G(f) f o Φ div (t) Φ tn,pll (t) Φ out (t) 52

53 Application: A 1 MHz Bandwidth Fractional-N Frequency Synthesizer Implementation

54 Design Goals Output frequency: 3.6 GHz - Allows dual-band output (1.8 GHz and 900 MHz) Reference frequency: 50 MHz - Allows low cost crystal reference Bandwidth: 1 MHz - Allows fast settling time and ~1 Mbit/s modulation rate Noise: < -150 dbc/hz at 20 MHz offset (3.6 GHz carrier) - Phase noise at the 20 MHz frequency offset is very challenging for GSM and DCS transmitters GSM: -162 dbc/hz at 20 MHz offset (900 MHz carrier) DCS: -151 dbc/hz at 20 MHz offset (1.8 GHz carrier) Simultaneous achievement of the above bandwidth and noise targets is very challenging 5

55 Evaluate Noise Performance with 1 MHz PLL BW G(f) parameters - 1 MHz BW, Type II, 2 nd order rolloff, extra pole at 2.5 MHz Required PLL noise parameters (with a few db of margin) - Output-referred charge pump noise: -105 dbc/hz - VCO noise: -155 dbc/hz at 20 MHz offset (3.6 GHz carrier) 55

56 Calculated Phase Noise for Classical Fractional-N 2 nd Order Σ -132 dbc/hz at 20 MHz 3 rd Order Σ These do NOT meet our target of -150 dbc/hz at 20 MHz (3.6 GHz carrier freq.) -126 dbc/hz at 20 MHz 56

57 Calculated Phase Noise for 7-bit PFD/DAC Synth 7-bit PFD/DAC -155 dbc/hz at 20 MHz! 57

58 Simulation of PFD/DAC Synthesizer using CppSim Phase noise plots to follow: 0e6 time steps in 10 min 58

59 Intrinsic PLL Noise Performance ref(t) div(t) PFD/DAC Loop Filter out(t) Reg Reg Divider frac[k] = 0 Accum residue[k] = 0 Set fractional portion of divide value to zero - Leads to residue variation of zero No quantization noise! Need to calculate and simulate impact of detector and VCO noise In essence, operate as integer-n synthesizer 59

60 Calculate Intrinsic PLL Noise Sources Estimate detector noise (dominated by charge pump) - From SPICE Simulation, S Icp (f) = Duty*3e-22 A 2 /Hz - Output-referred PLL noise due to above noise: Estimate VCO noise - For off-chip VCO, examine data sheet: In this case, S Φvco = -155 dbc/hz at 20 MHz offset - For on-chip VCO, use Spectre RF or other CAD tool 60

61 Calculate PLL Noise Due to Intrinsic Noise Sources We will see that we will need to include: - Reference noise - 1/f noise 61

62 Simulated Phase Noise due to Intrinsic Noise Sources CppSim Simulated Phase Noise for Cell: wb_synth, Lib: WBSynth_Example, Sim: test_int_n.par Reference Spur -50 dbc at 50 MHz freqfilt L(f) (dbc/hz) Spurs (dbc) Detector Noise VCO Noise Total Noise Frequency Offset from Carrier (MHz) PLL Design Assistant accurately models simulated noise! 62

63 2 nd Order Σ Fractional-N Performance ref(t) div(t) PFD/DAC Loop Filter out(t) Reg Reg Divider frac[k] 2nd order Σ residue[k] = 0 Replace accumulator with second order Σ modulator Set residue into PFD/DAC equal to zero 63

64 Calculate PLL Noise for 2 nd Order Σ Synthesizer 2 nd order Σ - Click on 2 nd order S-D quantization noise in tool 6

65 Simulated Phase Noise of 2 nd Order Σ Synthesizer CppSim Simulated Phase Noise for Cell: wb_synth_sd2, Lib: WBSynth_Example, Sim: test.par -80 freqfilt L(f) (dbc/hz) SD Noise Detector Noise VCO Noise Total Noise Spurs (dbc) PLL Design Assistant accurately models simulated noise! Frequency Offset from Carrier (MHz) 65

66 7-bit PFD/DAC Synthesizer Performance Delay mismatch T vco + delayed div(t) vco_out(t) div(t) ref(t) Timing Mismatch Compensation and Re-synchronization PFD PFD Charge Pump ε[k] Charge Pump Sampler Loop Filter Residue[k] n+1 DAC Mismatch Shaping ε[k] 2 n 1-ε[k] DAC current element mismatch Application of proposed noise scrambling/shaping techniques leads to broadband noise from delay and DAC current mismatch 66

67 Impact on PLL Noise due to Non-idealities of PFD/DAC Impact of DAC mismatch - Lowers achievable quantization noise suppression - Negligible in this case Impact of delay mismatch - Model as white reference noise uniformly distributed from 0 to t Calculation for t = 5 ps: 67

68 Calculate PLL Noise for 7-bit PFD/DAC Synthesizer PFD/DAC - Adjust S-D Quant. Noise Delay mismatch - Adjust Detector noise 68

69 Simulated PLL Phase Noise of 7-bit PFD/DAC PLL Design Assistant accurately models simulated noise! 69

70 Summary of Design/Simulation Results The PLL Design Assistant can be used to model the impact of - Intrinsic PLL noise sources - Quantization noise due to Σ dithering of divide value - Suppression of quantization noise by n-bit PFD/DAC - Impact of delay and current mismatch on PLL phase noise CppSim simulations confirm the accuracy of the above analysis How do PLL Design Assistant calculations compare to measured results? 70

71 A 1 MHz BW Fractional-N Frequency Synthesizer IC Scott Meninger Implements proposed 7-bit PFD/DAC structure u CMOS - Circuit details to be published in the future Funded by MARCO C2S2 Fabricated by National Semiconductor

72 Measured vs Calculated Phase Noise (Integer-N) Calculated noise is way off! - Issue: we did not consider reference jitter and 1/f noise 72

73 Adjustment of Calculations to Fit Measured Result Calculated noise now assumes: - Detector noise is -107 dbc/hz with 1/f corner of 130 khz 73

74 Back Extraction of Reference Jitter Assuming G(f) = 1: Accounts for PFD structure with reduced i up Assuming N nom = 73, T = 1/50MHz, i up /i down = 1/5 t jitt = 3.08ps 7

75 7-bit PFD/DAC Synthesizer Vs Integer-N Configuration Left: Phase swapping enabled - Timing mismatch converted into broadband noise Right: Phase swapping disabled - More fractional spurs, lower broadband noise 75

76 Adjustment of Calculations to fit Measured Results Calculated noise now assumes: - Detector noise is -100 dbc/hz with 1/f corner of 20 khz 76

77 Back Extraction of Timing Mismatch Using the Model Assuming G(f) = 1: Assuming N nom = 73, T = 1/50MHz t2 = 10.7 ps 77

78 Measured Noise Suppression Comparison of 7-bit PFD/DAC synthesizer with 2 nd order Σ Synthesizer Low freq noise ~2dB worse because of phase swapping 29dB quantization noise suppression measured at 10MHz! 78

79 Measured Noise Suppression: No Swapping Demonstrates that timing mismatch is degrading our maximum suppression by 2 db (when swapping) Spurs occur due to gain error from timing mismatch 79

80 Summary of Calculation/Measured Results Comparison Comparison of PLL Design Assistant results to measured data allow back extraction of key parameters: - Intrinsic noise Detector and VCO noise - PFD/DAC nonidealities Delay mismatch value Future work: better low frequency noise accuracy 80

81 Conclusions Fractional-N frequency synthesizers are about to undergo dramatic improvement in achieving high PLL bandwidth with excellent noise performance - The PFD/DAC approach presented here is only one of many possibilities to achieve this goal Design and simulation methodologies are starting to emerge - Analytical modeling of noise can be quite accurate The PLL Design Assistant can be useful in this area - Behavioral simulation can be used to verify analytical models CppSim offers a convenient and fast framework for this Research into High Bandwidth PLL Architectures is at an Exciting Crossroads 81