Low Power, Wide Bandwidth Phase Locked Loop Design

Transcription

1 Low Power, Wide Bandwidth Phase Locked Loop Design Hariprasath Venkatram and Taehwan Oh Abstract A low power wide bandwidth phase locked loop is presented in the paper. The phase frequency detector, charge pump, voltage controlled oscillator and high speed divider are described in detail. A split-tuned voltage controlled oscillator technique was implemented for improved K vco linearity. Index Terms Phase frequency detector, charge pump, voltage controlled oscillator, phase noise, loop-gain, bandwidth, phase margin, reference spurs, locking range and hold-in range. I. TODUTION The wide-bandwidth phase locked loop design specification is given in Table.. Table Design Specification Design Specification Technology.8 m MOS Supply Voltage <.8 V Operating Frequency 5 MHz-5 MHz Fixed divider ratio 4 Absolute Jitter.% of the period(r.m.s) Power onsumption Minimum The following sections describe the design choices at a system level implementation of PLL such as choice of bandwidth, phase margin and circuit parameters. The design of individual building blocks is considered in section III. Simulation results and performance summary is presented in section IV. Section V provides conclusion and future work. II. SYSTEM LEVEL DESIGN A type-, third order PLL architecture was chosen for the design. This architecture was chosen considering the widebandwidth requirement and low power consumption, as shown in Fig. The linear model for the type- PLL is shown in Fig.. The reference frequency range is from 5 MHz 375 MHz for the given divider ratio of 4. Noise analysis was performed to decide loop bandwidth and phase margin. The loop parameters were calculated using the above specifications. A. Noise Analysis The absolute jitter specification is.% of the period (r.m.s). The absolute jitter consists of random jitter and deterministic jitter. The design was carried out for a random jitter contribution of.5% of the period. This allows room for optimizing deterministic jitter. EF ref + v + - PFD P VO N Figure PLL Architecture I cp s z s ( s ) p3 N Figure Linear Model K vco s The above mentioned design choice of.5% for random jitter and.5% for deterministic jitter was arrived at after simulating voltage controlled oscillator phase noise and frequency tuning range. This choice provided us with total power consumption of less than mw at GHz. The noise contribution of various components to the PLL output is shown in Fig.3. The phase noise contribution at the PLL output is dominated by voltage controlled oscillator (VO) []. Therefore, a larger closed loop bandwidth results in higher suppression of VO noise. Therefore, the maximum PLL closed loop bandwidth for a reference frequency of 5 MHz is approximately.5 MHz; this is derived from the linear approximation model. Since the phase noise of VO is a weak function of loop phase margin, the phase margin was chosen to be 6 for a closed loop response of third order Butterworth filter. The simulated noise performance of VO, charge pump and loop-filter resistor is shown in Fig 3. The simulated overall random jitter was.45%. The random jitter contribution of VO, charge pump and resistor was.%,.% and.5% respectively. To linearize the K vco, split-tuned current starved inverter architecture was used.

2 Phase in degree Magnitude in db, dbc/hz Low power, Wide bandwidth Phase Locked Loop Design B. Loop Parameters Given the unity gain bandwidth and phase margin, the following equations were used for deriving the circuit parameters for the PLL. Kc ( tan M tanm tan M ) ugb z,, z K c I cp p3 ugb ugb Kvco z ugb Phase Noise c icp vr vco total omponent VO P esistor Total ontribution (%) Figure 3 Phase noise contribution The calculated value of circuit parameters are shown in Table. The simulated loop-gain and phase margin for the above design is shown in Fig. 4. The overall designed PLL performance is summarized in Table.3. The power consumption at 5 MHz and GHz for various blocks is shown in the Fig. 5. Table Loop Parameters Parameter Value 4 k.83 pf vco.98 pf K.5 GHz/V I 7 A cp Table 3 Performance Summary Design Specification Technology.8 m MOS Supply Voltage.8 V Operating Frequency 5 MHz-5 MHz Fixed divider ratio 4 Absolute Jitter (random).4% of the period(r.m.s)(random jitter) Absolute Jitter.4% of the period(r.m.s) (random MHz.4% of the MHz Power onsumption.5 5 MHz.7 GHz Power 6% % 35% 49% Power % % 5% 7% PFD VO P DIV PFD VO P DIV Loop Gain and Phase Margin Figure 5 Power onsumption Frequency, rad/s Figure 4 Loop Gain and Phase Margin III. BUILDG BLOKS This section describes the design of various building blocks in the phase locked loop A. Phase Frequency Detector Fig. 6 shows the pass transistor PFD chosen for low power consumption. The transistors plays the role of slave reset. This transistor determines the reset time of the flip-flop and it was sized through simulations to achieve 4 ps reset time. The simulated transfer characteristic of the pass transistor PFD is shown in Fig. 7.

3 Icp, A UPb, DN, V Average PFD output, V Low power, Wide bandwidth Phase Locked Loop Design 3 V D (Pass-Tr) STB (Pass-Tr) X X M M 4X X 8X 8X Q UPB DN Even though the current mismatch can be minimized with the cascode devices in the current source, the difference of the parasitic capacitances of PMOS and NMOS devices results in different time constant for up and down current paths. This results in static phase offset between UPB and DN pulse in steady state. To alleviate this problem, we use the same size ratio of PMOS and NMOS devices. With this approach, we can minimize the current peaking as shown in Fig 9. Also to increase the operation speed, we use the minimum length in the cascode devices, M and M. The noise contribution from harge pump was approximately.%. This was calculated at GHz with PFD reset time of 5 ps. M4 X (Pass-Tr) STB Devices M,M, M4~ V (X) Size.8u/.8u.5u/.8u.u/.8u.u/.8u.u/.8u Figure 6 Phase Frequency Detector MS MS MS3 M BS M M4 BS BS3 ua MS6 MS7 BS4 UPB MS4 BS M8 M9 MS8 BS BS3 BS4 DN MS5 M M M MS9 IP Pass Transistor PFD and Ideal Tristate PFD haracteristic, 5 MHz Bias circuit Main charge pump Ideal Pass Transistor Devices MS~MS3, MS6~MS7 MS4~MS5, MS8~MS9 M~M, Size u/.8u 4u/.8u u/.5u.5/u Devices M4,M9,,M8,, M, M,M Size u/u 4u/.5u 9.8u/.8u p Figure 8 harge pump schematic - B. harge Pump Phase difference, s x -9 Figure 7 PFD haracteristic The charge pump is one of the most critical blocks to determine the PLL performance, especially the deterministic jitter. The control voltage ripple which affects the deterministic jitter directly is mainly generated from two sources. The On-time mismatch between PMOS and NMOS switches and current mismatch between up-current and downcurrent of charge pump. Although we can reduce the first error using transmission gate in the PFD, the current mismatch problem is difficult to handle. In our design, we choose the cascode type current source to minimize static current mismatch even with speed and supply headroom penalty as shown in Fig PFD, harge Pump Output at 5 MHz x x -7 4 x time, s x -7 Figure 9 harge Pump Performance at 5 MHz

4 K vco, Hz/V Low power, Wide bandwidth Phase Locked Loop Design 4. Voltage ontrolled Oscillator The voltage controlled oscillator is the most important block in PLL in terms of noise contribution. The three stage ring oscillator was chosen to obtain the necessary output frequency range at low power consumption. To minimize the flicker noise contribution the channel length of NMOS and PMOS in delay cell was chosen to be.5 m. The V-I converter was implemented using a simple sourcedegenerated transistor stage. To improve the linearity of the K vco, a current split control technique was utilized. The VO buffer was designed with a low threshold inverter to accommodate the swing variation in the VO. Since the duty cycle does not play any role in this architecture, the skewed inverter buffer provides a simple solution to the buffer stage of the VO. The VO schematic and simulated characterisitic are shown in Fig and respectively. The variation of UGB and PM with Kvco was negligible. The noise contribution of VO is.%. The VO was designed considering the random and deterministic jitter requirement x 9 x 9 VO haracteristic ontrol Voltage, V GHz/V GHz/V Figure VO haracteristic (TSP) (TSP) V M BS M M4 D D D D 3 LK M M M4 LK M8 M9 M M V-I conv. Y TSP Devices M~M,M M4~M Size.8u/.8u.u/.8u.4u/.8u Devices M, M M4 D Size 4u/u 6u/u u/u 6u/.5u 4u/.5u Devices D,,3 Size u/.8u u/.8u.75k, 6K,K p Figure Voltage ontrolled Oscillator D. TSP Divider The divider in the PLL is a high speed building block. True single phase divider was chosen for high speed and dynamic power consumption. Further, speed optimization of the high speed D-Flip Flop was carried out as described in []. The design choices for the DFF are shown in Fig. Figure TSP Divider IV. SIMULATION ESULTS AND SUMMAY This section presents the performance summary and simulation results of the PLL. Transient, PSS, Pnoise simulations were carried out in Spectre. The control voltage settling and frequency of VO is shown in Fig 3 and 4. The control voltage ripple is within 3 mv. The absolute jitter performance was.4% at 5 MHz and 5 MHz for random noise. The absolute jitter performance including deterministic jitter was.4% at 5 MHz and.4% at 5 MHz, respectively. The VO output spectrum was simulated for.5 GHz and the reference spurs were at -6 dbc/hz. The deterministic jitter performance was evaluated using eye diagram plot shown in Fig 5.

5 Amplitude ontrol Voltage, V VO Spectrum, db VO Frequency, MHz ontrol Voltage, V Low power, Wide bandwidth Phase Locked Loop Design ontrol Voltage and VO Frequency Vs Time time, ns time, ns Figure 3 ontrol Voltage and VO Frequency at 5 MHz V. ONLUSION AND FUTUE WOK A wide bandwidth, low power PLL was designed and simulated in.8 m MOS technology. urrent split tuned architecture was used for VO. The parasitic capacitance matching for the charge pump was one of the major design issues. The PLL was designed considering deterministic jitter performance. The optimization for noise and power contribution of VO is the most critical part of this project. The power consumption can be reduced by relaxing phase noise requirement on VO (presently.%). Bandwidth tracking and Delay line controlled proportional path can be implemented to decrease power consumption. - VO Output Spectrum ontrol Voltage, VO Frequency MHz, -6 db 65 GHz, -6 db x x x x x time, s x -7 Figure 4 ontrol Voltage and VO Frequency at GHz.8.6 Eye 5 MHz Figure 6 VO Output Spectrum VI. EFEENES x 9 [] Mozhgan Mansuri and hih-kong ken Yang,., "Jitter Optimization based on Phase- Locked loop Design Parameters.", IEEE Journal of Solid-State ircuits, November, Issue, Vol. 37. [] Qiuting Huang and obert ogenmoser., "Speed Optimization of Edge- Triggered MOS circuits for Gigahertz Single-Phase locks.", IEEE Journal of Solid-State ircuits, March 996, Issue 3, Vol X: 6.e- Y: ps x Time x - Figure 5 Eye Diagram