6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers

Transcription

1 6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott

2 Bandwidth Constraints for Integer-N Synthesizers 1/T Loop Filter Bandwidth << 1/T ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) Divider N[k] PFD output has a periodicity of 1/T - 1/T = reference frequency Loop filter must have a bandwidth << 1/T - PFD output pulses must be filtered out and average value extracted Closed loop PLL bandwidth often chosen to be a factor of ten lower than 1/T

3 Bandwidth Versus Frequency Resolution 1/T Loop Filter Bandwidth << 1/T ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) Divider N[k] N[k] out(t) S out (f) 1/T frequency resolution = 1/T GHz Frequency resolution set by reference frequency (1/T) - Higher resolution achieved by lowering 1/T

4 Increasing Resolution in Integer-N Synthesizers 1/T Loop Filter Bandwidth << 1/T 20 MHz 100 ref(t) (1/T = 200 khz) PFD Loop Filter out(t) Divider N[k] 9001 N[k] 9000 out(t) frequency resolution = 1/T S out (f) 1/T GHz Use a reference divider to achieve lower 1/T - Leads to a low PLL bandwidth ( < 20 khz here )

5 The Issue of Noise 1/T Loop Filter Bandwidth << 1/T 20 MHz 100 ref(t) (1/T = 200 khz) PFD Loop Filter out(t) Divider N[k] 9001 N[k] 9000 out(t) frequency resolution = 1/T S out (f) 1/T GHz Lower 1/T leads to higher divide value - Increases PFD noise at synthesizer output

6 Modeling PFD Noise Multiplication PFD-referred Noise S En (f) 0 f 1/T e n (t) VCO-referred Noise S Φvn (f) 0-20 db/dec f Φ vn (t) Radians 2 /Hz 0 (f o ) opt α π N 2 S en (f) S Φvn (f) f Influence of PFD noise seen in model from Lecture 16 - PFD spectral density multiplied by N 2 before influencing PLL output phase noise Φ npfd (t) Divider Control Φ c (t) of Frequency Setting (assume noiseless for now) f o α π N G(f) Φ n (t) f o Φ nvco (t) 1-G(f) Φ out (t) Radians 2 /Hz S Φnpfd (f) (f o ) opt S Φnvco (f) High divide values high phase noise at low frequencies 0 f

7 Dual-Loop Frequency Synthesizer ref 1 PFD Loop Filter Divider VCO cos(w 1 t) sin(w 1 t) out ref 2 PFD N Loop Filter Divider VCO cos(w 2 t) sin(w 2 t) Single-sideband Mixer Overall synthesizer output M From trigonometry: cos(a-b) = cosacosb+sinasinb

8 Advantage #1: Avoids Large Divide Values ref 1 PFD Loop Filter Divider VCO cos(w 1 t) sin(w 1 t) out ref 2 PFD N Loop Filter Divider VCO cos(w 2 t) sin(w 2 t) Single-sideband Mixer M Choose top synthesizer to provide coarse tuning and bottom synthesizer to provide fine tuning - Choose w 1 to be high in frequency Set ref 1 to be high to avoid large N low resolution - Choose w 2 to be low in frequency Allows ref 2 to be low without large M high resolution

9 Advantage #2: Provides Suppression of VCO Noise ref 1 PFD Loop Filter Divider VCO cos(w 1 t) sin(w 1 t) out ref 2 PFD N Loop Filter Divider VCO cos(w 2 t) sin(w 2 t) Single-sideband Mixer M Top VCO has much more phase noise than bottom VCO due to its much higher operating frequency - Suppress top VCO noise by choosing a high PLL bandwidth for top synthesizer High PLL bandwidth possible since ref 1 is high

10 Alternate Dual-Loop Architecture ref 1 PFD Loop Filter VCO cos(w 1 t) sin(w 1 t) out Divider y ref 2 PFD N Loop Filter Divider VCO cos(w 2 t) sin(w 2 t) Single-sideband Mixer Calculation of output frequency M

11 Advantage of Alternate Dual-Loop Architecture ref 1 PFD Loop Filter cos(w 1 t) sin(w 1 t) out VCO Divider y ref 2 PFD N Loop Filter cos(w 2 t) sin(w 2 t) VCO Divider Single-sideband Mixer M Issue: a practical single-sideband mixer implementation will produce a spur at frequency w 1 + w 2 PLL bandwidth of top synthesizer can be chosen low enough to suppress the single-sideband spur - Negative: lower suppression of top VCO noise

12 Direct Digital Synthesis (DDS) clk Counter ROM DAC LPF out Encode sine-wave values in a ROM Create sine-wave output by indexing through ROM and feeding its output to a DAC and lowpass filter - Speed at which you index through ROM sets frequency of output sine-wave Speed of indexing is set by increment value on counter (which is easily adjustable in a digital manner)

13 Pros and Cons of Direct Digital Synthesis clk Counter ROM DAC LPF out Advantages - Very fast adjustment of frequency - Very high resolution can be achieved - Highly digital approach Disadvantages - Difficult to achieve high frequencies - Difficult to achieve low noise - Power hungry and complex

14 Hybrid Approach clk Counter ROM DAC LPF ref PFD Loop Filter VCO out Divider Use DDS to create a finely adjustable reference frequency Use integer-n synthesizer to multiply the DDS output frequency to much higher values Issues - Noise of DDS is multiplied by N 2 - Complex and power hungry N

15 Fractional-N Frequency Synthesizers ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) N sd [k] Dithering Modulator N[k] Divider N sd [k] out(t) S out (f) 1/T frequency resolution << 1/T GHz Break constraint that divide value be integer - Dither divide value dynamically to achieve fractional values - Frequency resolution is now arbitrary regardless of 1/T Want high 1/T to allow a high PLL bandwidth

16 Classical Fractional-N Synthesizer Architecture ref(t) PFD e(t) Loop Filter out(t) div(t) N/N+1 frac[k] Accumulator 1-bit carry_out[k] N sd [k] = N + frac[k] Use an accumulator to perform dithering operation - Fractional input value fed into accumulator - Carry out bit of accumulator fed into divider

17 Accumulator Operation clk(t) frac[k] M-bit Accumulator M-bit 1-bit residue[k] carry_out[k] residue[k] frac[k] =.25 carry_out[k] Carry out bit is asserted when accumulator residue reaches or surpasses its full scale value - Accumulator residue increments by input fractional value each clock cycle

18 Fractional-N Synthesizer Signals with N = 4.25 carry_out(t) out(t) div(t) ref(t) e(t) phase error(t) Divide value set at N = 4 most of the time - Resulting frequency offset causes phase error to accumulate - Reset phase error by swallowing a VCO cycle Achieved by dividing by 5 every 4 reference cycles

19 The Issue of Spurious Tones ref(t) PFD e(t) Loop Filter out(t) div(t) N/N+1 frac[k] Accumulator 1-bit carry_out[k] PFD error is periodic - Note that actual PFD waveform is series of pulses the sawtooth waveform represents pulse width values over time Periodic error signal creates spurious tones in synthesizer output N sd [k] = N + frac[k] - Ruins noise performance of synthesizer

20 The Phase Interpolation Technique ref(t) PFD e(t) Loop Filter out(t) div(t) α N/N+1 D/A frac[k] M-bit Accumulator M-bit residue[k] 1-bit carry_out[k] Phase error due to fractional technique is predicted by the instantaneous residue of the accumulator - Cancel out phase error based on accumulator residue

21 The Problem With Phase Interpolation ref(t) PFD e(t) Loop Filter out(t) div(t) α N/N+1 D/A frac[k] M-bit Accumulator M-bit residue[k] 1-bit carry_out[k] Gain matching between PFD error and scaled D/A output must be extremely precise - Any mismatch will lead to spurious tones at PLL output

22 Is There a Better Way?

23 A Better Dithering Method: Sigma-Delta Modulation Time Domain M-bit Input Digital Σ Modulator 1-bit D/A Analog Output Digital Input Spectrum Quantization Noise Frequency Domain Analog Output Spectrum Input Σ Sigma-Delta dithers in a manner such that resulting quantization noise is shaped to high frequencies

24 Linearized Model of Sigma-Delta Modulator r[k] S r (e j2πft )= NTF z=e j2πft STF q[k] x[k] y[k] x[k] y[k] H Σ s (z) z=e j2πft H n (z) S q (e j2πft )= H n (e j2πft ) Composed of two transfer functions relating input and noise to output - Signal transfer function (STF) Filters input (generally undesirable) - Noise transfer function (NTF) Filters (i.e., shapes) noise that is assumed to be white

25 Example: Cutler Sigma-Delta Topology x[k] u[k] y[k] H(z) - 1 e[k] Output is quantized in a multi-level fashion Error signal, e[k], represents the quantization error Filtered version of quantization error is fed back to input - H(z) is typically a highpass filter whose first tap value is 1 i.e., H(z) = 1 + a 1 z -1 + a 2 z -2 L - H(z) 1 therefore has a first tap value of 0 Feedback needs to have delay to be realizable

26 Linearized Model of Cutler Topology x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Represent quantizer block as a summing junction in which r[k] represents quantization error - Note: It is assumed that r[k] has statistics similar to white noise - This is a key assumption for modeling often not true!

27 Calculation of Signal and Noise Transfer Functions x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Calculate using Z-transform of signals in linearized model - NTF: H n (z) = H(z) - STF: H s (z) = 1

28 A Common Choice for H(z) 8 7 m = 3 6 Magnitude m = 2 m = Frequency (Hz) 1/(2T)

29 Example: First Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 1 Amplitude Magnitude (db) 0 0 Sample Number Frequency (Hz) 1/(2T)

30 Example: Second Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 2 Amplitude 1 0 Magnitude (db) -1 0 Sample Number Frequency (Hz) 1/(2T)

31 Example: Third Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 4 3 Amplitude Magnitude (db) Sample Number Frequency (Hz) 1/(2T)

32 Observations Low order Sigma-Delta modulators do not appear to produce shaped noise very well - Reason: low order feedback does not properly scramble relationship between input and quantization noise Quantization noise, r[k], fails to be white Higher order Sigma-Delta modulators provide much better noise shaping with fewer spurs - Reason: higher order feedback filter provides a much more complex interaction between input and quantization noise

33 Warning: Higher Order Modulators May Still Have Tones Quantization noise, r[k], is best whitened when a sufficiently exciting input is applied to the modulator - Varying input and high order helps to scramble interaction between input and quantization noise Worst input for tone generation are DC signals that are rational with a low valued denominator - Examples (third order modulator): x[k] = 0.1 x[k] = /1024 Magnitude (db) Magnitude (db) 0 Frequency (Hz) 1/(2T) 0 Frequency (Hz) 1/(2T)

34 Cascaded Sigma-Delta Modulator Topologies x[k] Σ M 1 [k] q 1 [k] Σ M 2 [k] q 2 [k] Σ M 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] Digital Cancellation Logic y[k] Multibit output Achieve higher order shaping by cascading low order sections and properly combining their outputs Advantage over single loop approach - Allows pipelining to be applied to implementation High speed or low power applications benefit Disadvantages - Relies on precise matching requirements when combining outputs (not a problem for digital implementations) - Requires multi-bit quantizer (single loop does not)

35 MASH topology x[k] Σ M 1 [k] r 1 [k] Σ M 2 [k] r 2 [k] Σ M 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Cascade first order sections Combine their outputs after they have passed through digital differentiators

36 Calculation of STF and NTF for MASH topology (Step 1) x[k] Σ M 1 [k] r 1 [k] Σ M 2 [k] r 2 [k] Σ M 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Individual output signals of each first order modulator Addition of filtered outputs

37 Calculation of STF and NTF for MASH topology (Step 1) x[k] Σ M 1 [k] r 1 [k] Σ M 2 [k] r 2 [k] Σ M 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Overall modulator behavior - STF: H s (z) = 1 - NTF: H n (z) = (1 z -1 ) 3

38 Sigma-Delta Frequency Synthesizers F ref F out = M.F F ref ref(t) div(t) N sd [m] PFD e(t) Σ Modulator Charge Pump N[m] Divider Loop Filter M+1 M Σ Quantization Noise Use Sigma-Delta modulator rather than accumulator to perform dithering operation - Achieves much better spurious performance than classical fractional-n approach v(t) VCO f out(t) Riley et. al., JSSC, May 1993

39 Background: The Need for A Better PLL Model PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec 0 e n (t) 1/T f 0 Φ vn (t) f Φ ref [k] Φ div [k] α π PFD e(t) I cp Charge Pump Divider 1 N H(f) Loop Filter v(t) K V jf VCO Φ out (t) Classical PLL model - Predicts impact of PFD and VCO referred noise sources - Does not allow straightforward modeling of impact due to divide value variations N[k] This is a problem when using fractional-n approach

40 A PLL Model Accommodating Divide Value Variations PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec Φ ref [k] PFD Tristate: α=1 XOR: α=2 α T 2π 0 e n (t) 1/T e(t) f C.P. I cp Loop Filter H(f) v(t) VCO K V jf 0 Φ vn (t) f Φ out (t) Φ div [k] 1 N nom Φ d [k] Divider 1 T n[k] 2π z-1 z=e j2πft 1 - z-1 See derivation in Perrott et. al., A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers, JSSC, Aug 2002

41 Parameterized Version of New Model Noise Φ jit [k] e spur (t) α T π PFD-referred Noise S En (f) 0 e n (t) 1/T f VCO-referred Noise S Φvn (f) -20 db/dec 0 Φ vn (t) f Ι cpn (t) 1 Ι f o π α Nnom G(f) f o 1-G(f) Φ npfd (t) Φ nvco (t) Divide value variation n[k] n[k] 2π z z -1 G(f) Φ d (t) z=e j2πft F c (t) T G(f) f o Alternate Representation f o 1 jf Φ c (t) Φ c (t) Φ n (t) Φ out (t) D/A and Filter Freq. Phase

42 Spectral Density Calculations case (a): CT CT x(t) H(f) y(t) case (b): DT DT x[k] H(e j2πft ) y[k] case (c): DT CT x[k] H(f) y(t) Case (a): Case (b): Case (c):

43 Example: Calculate Impact of Ref/Divider Jitter (Step 1) Div(t) S Φjit (e j2πft ) T t ( t jit ) rms = β sec. π T 2 β 2 0 f t jit [k] π T Φ jit [k] Assume jitter is white - i.e., each jitter value independent of values at other time instants Calculate spectra for discrete-time input and output - Apply case (b) calculation

44 Example: Calculate Impact of Ref/Divider Jitter (Step 2) Div(t) S Φjit (e j2πft ) S Φn (f) T t ( t jit ) rms = β sec. π T 2 β 2 0 f 2 1 TN π T nom T 2 β2 0 f o f t jit [k] π T Φ jit [k] Φ jit [k] TN nom G(f) Φ n (t) f o Compute impact on output phase noise of synthesizer - We now apply case (c) calculation - Note that G(f) = 1 at DC

45 Now Consider Impact of Divide Value Variations Noise Φ jit [k] e spur (t) α T π PFD-referred Noise S En (f) 0 e n (t) 1/T f VCO-referred Noise S Φvn (f) -20 db/dec 0 Φ vn (t) f Ι cpn (t) 1 Ι f o π α Nnom G(f) f o 1-G(f) Φ npfd (t) Φ nvco (t) Divide value variation n[k] n[k] 2π z z -1 G(f) Φ d (t) z=e j2πft F c (t) T G(f) f o Alternate Representation f o 1 jf Φ c (t) Φ c (t) Φ n (t) Φ out (t) D/A and Filter Freq. Phase

46 Divider Impact For Classical Vs Fractional-N Approaches Classical Synthesizer 1 1/T n(t) 1 T n[k] G(f) f o F out (t) D/A and Filter Fractional-N Synthesizer 1 1/T n sd (t) 1 T n sd [k] Dithering Modulator n[k] G(f) f o D/A and Filter F out (t) Note: 1/T block represents sampler (to go from CT to DT)

47 Focus on Sigma-Delta Frequency Synthesizer n[k] F out (t) n sd [k] 1 1/T n sd (t) 1 T n sd [k] Σ n[k] G(f) f o F out (t) freq=1/t D/A and Filter Divide value can take on fractional values - Virtually arbitrary resolution is possible PLL dynamics act like lowpass filter to remove much of the quantization noise

48 Quantifying the Quantization Noise Impact PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec n sd [k] S r (e j2πft )= 1 12 NTF STF H s (z) r[k] Σ H n (z) q[k] n[k] z=e j2πft Σ Quantization Noise S q (e j2πft ) 0 2π z z -1 f Φ n [k] z=e j2πft 0 E n (t) f o Φ vn (t) T G(f) Φ tn,pll (t) Φ div (t) Φ out (t) f o 1/T f π α Nnom G(f) 0 f o f 1-G(f) Calculate by simply attaching Sigma-Delta model - We see that quantization noise is integrated and then lowpass filtered before impacting PLL output

49 A Well Designed Sigma-Delta Synthesizer -60 f o = 84 khz Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T Order of G(f) is set to equal to the Sigma-Delta order - Sigma-Delta noise falls at -20 db/dec above G(f) bandwidth Bandwidth of G(f) is set low enough such that synthesizer noise is dominated by intrinsic PFD and VCO noise

50 Impact of Increased PLL Bandwidth f o = 84 khz f o = 160 khz Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) VCO-referred noise S Φout,vn (f) Σ noise S Φout, Σ (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T khz 100 khz 1 MHz 10 MHz f Frequency 0 1/T Allows more PFD noise to pass through Allows more Sigma-Delta noise to pass through Increases suppression of VCO noise

51 Impact of Increased Sigma-Delta Order m = 2 m = 3 Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ noise S Φout, Σ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz f Frequency 0 1/T PFD and VCO noise unaffected Sigma-Delta noise no longer attenuated by G(f) such that a -20 db/dec slope is achieved above its bandwidth