The Case for Oversampling


 Ronald Gibson
 2 years ago
 Views:
Transcription
1 EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulsecount modulation Sigmadelta modulation 1Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ modulator Dynamic range Practical implementation Effect of various nonidealities on the ΣΔ performance EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 1 The Case for Oversampling Nyquist sampling: Signal f s B Freq narrow transition AAFilter f s >B +δ Sampler Nyquist ADC DSP Oversampling: Signal f s >> f N?? B Freq wide transition AAFilter f s Mf N Sampler Oversampled ADC DSP Nyquist rate f N B Oversampling rate M f s /f N >> 1 EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page
2 Nyquist v.s. Oversampled Converters Antialiasing X(f) Input Signal f B frequency Nyquist Sampling f B f s f S ~f B Antialiasing Filter f s Oversampling frequency f B f S >> f B f s frequency EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 3 Oversampling Benefits No stringent requirements imposed on analog building blocks Takes advantage of the availability of low cost, low power digital filtering Relaxed transition band requirements for analog antialiasing filters Reduced baseband quantization noise power Allows trading speed for resolution EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 4
3 ADC Converters Baseband Noise For a quantizer with step size Δ and sampling rate f s : Quantization noise power distributed uniformly across Nyquist bandwidth ( f s /) N e (f) N B f B f s / f s / f B Power spectral density: e Δ 1 N(f) e fs 1 fs Noise is aliased into the Nyquist band f s / to f s / EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 5 Oversampled Converters Baseband Noise fb fb Δ 1 SB N e( f )df df fb fb 1 fs N e (f) Δ fb 1 f N B s where for fb f s/ Δ SB0 f s / f B f B f s / 1 fb SB0 SB SB0 f s M fs where M oversampling ratio f B EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 6
4 Oversampled Converters Baseband Noise fb SB0 SB SB0 f s M fs where M oversampling ratio fb X increase in M 3dB reduction in S B ½ bit increase in resolution/octave oversampling To increase the improvement in resolution: Embed quantizer in a feedback loop Predictive (delta modulation) Noise shaping (sigma delta modulation) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 7 PulseCount Modulation V in (kt) Nyquist ADC 0 1 t/t V in (kt) Oversampled ADC, M t/t Mean of pulsecount signal approximates analog input! EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 8
5 PulseCount Spectrum Magnitude f Signal: low frequencies, f < B << f s Quantization error: high frequency, B f s / Separate with lowpass filter! EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 9 Oversampled ADC Predictive Coding v IN + _ ADC D OUT Predictor Quantize the difference signal rather than the signal itself Smaller input to ADC Buy dynamic range Only works if combined with oversampling 1Bit digital output Digital filter computes average NBit output EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 10
6 Oversampled ADC Signal B Freq wide transition Analog AAFilter f s Mf N Sampler E.g. PulseCount Modulator Modulator 1Bit Digital f s1 M f N Decimator narrow transition Digital AAFilter NBit Digital f s f N + δ DSP Decimator: Digital (lowpass) filter Removes quantization error for f > B Provides most antialias filtering Narrow transition band, highorder 1Bit input, NBit output (essentially computes average ) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 11 Modulator Objectives: Convert analog input to 1Bit pulse density stream Move quantization error to high frequencies f >>B Operates at high frequency f s >> f N M 8 56 (typical).104 Since modulator operated at high frequencies need to keep circuitry simple ΣΔ ΔΣ Modulator EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 1
7 Sigma Delta Modulators Analog 1Bit ΣΔ modulators convert a continuous time analog input v IN into a 1Bit sequence d OUT f s v IN + _ H(z) d OUT DAC Loop filter 1b Quantizer (comparator) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 13 SigmaDelta Modulators The loop filter H can be either switchedcapacitor or continuous time Switchedcapacitor filters are easier to implement + frequency characteristics scale with clock rate Continuous time filters provide antialiasing protection Loop filter can also be realized with passive LC s at very high frequencies f s v IN + _ H(z) d OUT DAC EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 14
8 Oversampling A/D Conversion f s f s /M Input Signal Bandwidth Bf s /M Oversampling Modulator f s Decimation Filter f s /M f s sampling rate M oversampling ratio Analog frontend oversampled noiseshaping modulator Converts original signal to a 1bit digital output at the high rate of (MXB) Digital backend digital filter Removes outofband quantization noise Provides antialiasing to allow lower sampling rate EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 15 1 st Order ΣΔ Modulator In a 1 st order modulator, simplest loop filter an integrator H(z) z 1 1 z 1 v IN + _ d OUT DAC EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 16
9 1 st Order ΣΔ Modulator Switchedcapacitor implementation φ 1 φ φ V i  + d OUT 1,0 +Δ/ Δ/ EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 17 1 st Order ΔΣ Modulator v IN + Δ/ v IN +Δ/ _ dout Δ/ or +Δ/ DAC Properties of the firstorder modulator: Analog input range is equal to the DAC reference The average value of d OUT must equal the average value of v IN +1 s (or 1 s) density in d OUT is an inherently monotonic function of v IN linearity is not dependent on component matching Alternative multibit DAC (and ADCs) solutions reduce the quantization error but loose this inherent monotonicity & relaxed matching requirements EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 18
10 1 st Order ΣΔ Modulator Analog input Δ/ V in +Δ/ Tally of quantization error 1 X Q 1Bit quantizer 3 Y Sine Wave z z Integrator Comparator 1Bit digital output stream, 1, +1 Instantaneous quantization error Implicit 1Bit DAC +Δ/, Δ/ (Δ ) M chosen to be 8 (low) to ease observability EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 19 1 st Order Modulator Signals st Order SigmaDelta X Q Y X analog input Q tally of qerror Y digital/dac output Amplitude Mean of Y approximates X T 1/f s 1/ (M f N ) Time [ t/t ] EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 0
11 ΣΔ Modulator Characteristics Quantization noise and thermal noise (KT/C) distributed over f s / to +f s / Total noise within signal bandwidth reduced by 1/M Very high SQNR achievable (> 0 Bits!) Inherently linear for 1Bit DAC To first order, quantization error independent of component matching Limited to moderate & low speed EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 1 Output Spectrum Amplitude [ dbwn ] Input Frequency [ f /f s ] Definitely not white! Skewed towards higher frequencies Notice the distinct tones dbwn (db White Noise) scale sets the 0dB line at the noise per bin of a random 1, +1 sequence EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page
12 Quantization Noise Analysis Integrator Quantization Error e(kt) x(kt) Σ H( z) z z Σ Quantizer Model y(kt) SigmaDelta modulators are nonlinear systems with memory difficult to analyze directly Representing the quantizer as an additive noise source linearizes the system EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 3 Signal Transfer Function z H( z) 1 + z ω0 H( jω ) jω x(kt) Σ  Integrator H(z) y(kt) Signal transfer function low pass function: 1 HSig ( jω ) 1 + s ω0 Y( z) H( z) HSig ( z) z X( z) 1 + H( z) Delay Magnitude f 0 Frequency EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 4
13 v i Σ  ω 0 jω Noise Transfer Function Qualitative Analysis v n v o v eq v i Σ  v f n f 0 ω0 jω v o f f 0 eq vn v f f 0 eq vn v Σ v i  ω0 jω v o f 0 Frequency Input referrednoise DC (splane) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 5 STF and NTF Integrator Quantization Error e(kt) x(kt) Σ z H( z) 1 + z Σ Quantizer Model y(kt) Signal transfer function: Y( z) H( z) STF z X( z) 1 + H( z) Delay Noise transfer function: Y ( z) 1 NTF 1 z E( z) 1+ H ( z) Differentiator EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 6
14 Noise Transfer Function Y( z) 1 NTF 1 z Ez ( ) 1 + Hz ( ) jωt / jωt / jωt / jωt jωt / e e NTF( jω) (1 e )e ( ω ) ( ω ) e jsin T / jωt / jπ / e e sin T / j( ωt π) / sin ( ωt /) e where T 1/ fs Thus: ( ω ) ( π ) NTF( f ) sin T / sin f / f s N ( f ) NTF( f ) N ( f ) y e EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 7 First Order ΣΔ Modulator Noise Transfer Characteristics Noise Shaping Function Lowpass Digital Filter N ( f ) NTF( f) N ( f ) y ( π f f ) 4sin / FirstOrder Noise Shaping s e f B f N Frequency f s / Key Point: Most of quantization noise pushed out of frequency band of interest EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 8
15 First Order ΣΔ Modulator Simulated Noise Transfer Characteristic Amplitude [ dbwn ] Signal Simulated output spectrum Computed NTF ( π ) N ( f) 4 sin f / f y s Frequency [f/f s ] EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 9 Quantizer Error For quantizers with many bits e Δ ( kt) 1 Let s use the same expression for the 1Bit case Use simulation to verify validity Experience: Often sufficiently accurate to be useful, with enough exceptions to be very careful EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 30
16 First Order ΣΔ Modulator InBand Quantization Noise ( ) ( ) ( π ) fs M fs M NTF z 1 z s NTF f 4sin f / f for M >> 1 Y B B Q ( ) ( ) S S f NTF z df 1 Δ f 1 s z e ( sinπ ft ) π jft df S Y π 1 Δ M EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 31 Dynamic Range peak signal power S X DR 10log 10log peak noise power SY S S S S X Y X Y 1 Δ sinusoidal input, STF 1 π 1 Δ 3 3 M M π DR 10log M 10log + 30log M π π M DR db 3 4 db db DR 3.4dB ++ 30log M X increase in M 9dB (1.5Bit) increase in dynamic range EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 3
17 Oversampling and Noise Shaping ΣΔ modulators have interesting characteristics Unity gain for input signal V IN Large inband attenuation of quantization noise injected at quantizer input Performance significantly better than 1Bit noise performance possible for frequencies << f s Increase in oversampling (M f s /f N >> 1) improves SQNR considerably 1 st order ΣΔ: DR increases 9dB for each doubling of M To first order, SQNR independent of circuit complexity and accuracy Analysis assumes that the quantizer noise is white Not true in practice, especially for loworder modulators Practical modulators suffer from other noise sources also (e.g. thermal noise) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 33 DC Input Amplitude [ dbwn ] Frequency [ f /f s ] DC input A 1/11 Doesn t look like spectrum of DC at all Tones frequency shaped the same as quantization noise More prominent at higher frequencies Seems like periodic quantization noise EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 34
18 Output 0. 0 Limit Cycle First order sigmadelta, DC input Time [t/t] DC input 1/11 Periodic sequence: EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 35 Limit Cycle Noise Shaping Function Ideal Lowpass Digital Filter Inband spurious tone with f ~ DC input FirstOrder Noise Shaping f B f N Frequency f s / Problem: quantization noise is periodic Solution: Use dithering: randomizes quantization noise  Thermal noise acts as dither Second order loop EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 36
19 1 st Order ΣΔ Modulator ( ) 1 1 Y( z) z X( z) + 1 z E( z) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 37 nd Order ΣΔ Modulator Two integrators 1st integrator nondelaying Feedback from output to both integrators Tones less prominent compared to 1st order EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 38
20 nd Order ΣΔ Modulator ( ) Recursive drivation: Y X + E E + E n n n n n ( ) Using the delay operator z : Y( z) z X( z) + 1 z E( z) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 39 nd Order ΣΔ Modulator InBand Quantization Noise ( ) ( 1 z ) ( f ) 4 z H( z) 1 z G 1 NTF z NTF ( π ) sin f / f for M >> 1 B Y Q( ) ( ) z e B S S f NTF z df f s f s M M 1 Δ f Δ 5 π 5 M 1 s s 4 ( sinπ ft) π jft 4 df EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 40
21 Quantization Noise nd Order ΣΔ Modulator Noise Shaping Function Ideal Lowpass Digital Filter nd Order Noise Shaping FirstOrder Noise Shaping f B Frequency f s / EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 41 nd Order ΣΔ Modulator Dynamic Range peak signal power S X DR 10log 10log peak noise power SY S S S S X Y X Y 1 Δ sinusoidal input, STF 1 4 π 1 Δ 5 5 M M 4 π DR 10log M 10log + 50log M 4 4 π π M DR db 3 64 db db DR 11.1dB log M X increase in M 15dB (.5bit) increase in DR EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 4
22 Digital audio application Signal bandwidth 0kHz Resolution 16bit nd Order ΣΔ Modulator Example 16 bit 98 db Dynamic Range M DR 11.1dB ++ 50log M min 153 M 56 8 to allow some margin & also for ease of digital filter implementation Sampling rate (x0khz + 5kHz)M 1MHz EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 43 Higher Order ΣΔ Modulator Dynamic Range ( ) L 1 Y( z) z X( z) + 1 z E( z), L ΣΔ order S S S S X Y X Y Δ L 1 sinusoidal input, STF 1 π 1 L M 3 ( L + 1) M L π + 1 L+ 1 1 L+ 1 ( L + ) 3 1 DR 10log M L π DR L+ 1 3 ( L + 1) 10log +( L ) π L Δ logm X increase in M (6L+3)dB or (L+0.5)bit increase in DR EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 44
23 ΣΔ Modulator Dynamic Range As a Function of Modulator Order L3 L L1 Potential stability issues for L > EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 45 Tones in 1 st Order & nd Order ΣΔ Modulator Higher oversampling ratio lower tones nd order much lower tones compared to 1 st Xincrease in M decreases the tones by 6dB for 1 st order loop and 1dB for nd order loop 1dB 6dB 1 st Order ΣΔ Modulator nd Order ΣΔ Modulator Ref: B. P. Brandt, et al., "Secondorder sigmadelta modulation for digitalaudio signal acquisition," IEEE Journal of SolidState Circuits, vol. 6, pp , April R. Gray, Spectral analysis of quantization noise in a singleloop sigma delta modulator with dc input, IEEE Trans. Commun., vol. 37, pp , June EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 46
24 nd Order ΣΔ Modulator SwitchedCapacitor Implementation IN Dout EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 47 SwitchedCapacitor Implementation nd Order ΣΔ Phase 1 Sample inputs Compare output of nd integrator At the end of phase1, S3 opens prior to S1 opening EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 48
25 SwitchedCapacitor Implementation nd Order ΣΔ Phase Enable feedback from output to input of both integrators Integrate Reset comparator At the end of phase S4 opens before S EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 49 ΣΔ Implementation Practical Design Considerations Internal nodes scaling & clipping Finite opamp gain & linearity Capacitor ratio errors KT/C noise Opamp noise Power dissipation considerations EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 50
26 SwitchedCapacitor Implementation nd Order ΣΔ Nodes Scaled for Maximum Dynamic Range Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input fullscale (Δ) Ref: B.E. Boser and B.A. Wooley, The Design of SigmaDelta Modulation A/D Converters, IEEE J. SolidState Circuits, vol. 3, no. 6, pp , Dec EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 51 nd Order ΣΔ Modulator SwitchedCapacitor Implementation The ½ loss in front of each integrator implemented by choice of: C C 1 EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 5
27 nd Order ΣΔ Effect of Integrator Maximum Signal Handling Capability on SNR Effect of 1 st Integrator maximum signal handling capability on converter SNR Ref: B.E. Boser and B.A. Wooley, The Design of SigmaDelta Modulation A/D Converters, IEEE J. SolidState Circuits, vol. 3, no. 6, pp , Dec EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 53 nd Order ΣΔ Effect of Integrator Maximum Signal Handling Capability on SNR Effect of nd Integrator maximum signal handling capability on SNR Ref: B.E. Boser and B.A. Wooley, The Design of SigmaDelta Modulation A/D Converters, IEEE J. SolidState Circuits, vol. 3, no. 6, pp , Dec EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 54
28 nd Order ΣΔ Effect of Integrator Finite DC Gain V i φ 1 φ Cs  a + CI V o ( ) H z ( ) H z ideal Finit DC Gain Cs z 1 CI 1 z a z Cs 1+ a + Cs CI CI 1+ a 1 z Cs 1+ a + CI EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 55 nd Order ΣΔ Effect of Integrator Finite DC Gain log H ( s) a Ideal Integ. (ainfinite) Max signal level ω P1 0 a ω 0 a Integrator magnitude response f 0 /a Low integrator DC gain Increase in total inband noise Can be shown: If a > M (oversampling ratio) Insignificant degradation in SNR Normally DC gain designed to be >> M in order to suppress nonlinearities EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 56
29 nd Order ΣΔ Effect of Integrator Finite DC Gain M / a Example: a M 0.4dB degradation in SNR Ref: B.E. Boser and B.A. Wooley, The Design of SigmaDelta Modulation A/D Converters, IEEE J. SolidState Circuits, vol. 3, no. 6, pp , Dec EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 57 nd Order ΣΔ Effect of Integrator Overall Integrator Gain Inaccuracy Gain of ½ in front of integrators determined by ratio of C1/C Effect of inaccuracy in ratio of C1/C inspected by simulation EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 58
30 nd Order ΣΔ Effect of Integrator Overall Gain Inaccuracy Simulation show gain can vary by 0% w/o loss in performance Confirms insensitivity of ΣΔ to component variations Note that for gain >0.65 system becomes unstable & SNR drops rapidly EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 59 nd Order ΣΔ Effect of Integrator Nonlinearities u(kt) Ideal Integrator Delay v(kt) v(kt+ T) u(kt) + v(kt) With nonlinearity added: 3 v(kt + T ) u(kt ) + α u( kt ) + α 3 u( kt ) v(kt ) + β v( kt ) + β 3 v( kt ) +... Ref: B.E. Boser and B.A. Wooley, The Design of SigmaDelta Modulation A/D Converters, IEEE J. SolidState Circuits, vol. 3, no. 6, pp , Dec EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 60
31 nd Order ΣΔ Effect of Integrator Nonlinearities α β 0.01, 0.0, 0.05, 0.1% Simulation for singleended topology Even order nonlinearities can be significantly attenuated by using differential circuit topologies Ref: B.E. Boser and B.A. Wooley, The Design of SigmaDelta Modulation A/D Converters, IEEE J. SolidState Circuits, vol. 3, no. 6, pp , Dec EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 61 nd Order ΣΔ Effect of Integrator Nonlinearities α 3 β , 0.,1% 6dB 1Bit Simulation for singleended topology Odd order nonlinearities (3 rd in this case) Ref: B.E. Boser and B.A. Wooley, The Design of SigmaDelta Modulation A/D Converters, IEEE J. SolidState Circuits, vol. 3, no. 6, pp , Dec EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 6
Summary Last Lecture
Interleaved ADCs EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulsecount modulation Sigmadelta modulation 1Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations
More informationAnalogtoDigital Converters
EE47 Lecture 3 Oversampled ADCs Why oversampling? Pulsecount modulation Sigmadelta modulation 1Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ
More informationSummary Last Lecture
EE47 Lecture 5 Pipelined ADCs (continued) How many bits per stage? Algorithmic ADCs utilizing pipeline structure Advanced background calibration techniques Oversampled ADCs Why oversampling? Pulsecount
More informationEE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting
EE47 Lecture 6 This lecture is taped on Wed. Nov. 8 th due to conflict of regular class hours with a meeting Any questions regarding this lecture could be discussed during regular office hours or in class
More informationEE247 Lecture 26. EE247 Lecture 26
EE247 Lecture 26 Administrative EE247 Final exam: Date: Mon. Dec. 18 th Time: 12:30pm3:30pm Location: 241 Cory Hall Extra office hours: Thurs. Dec. 14 th, 10:30am12pm Closed book/course notes No calculators/cell
More informationEE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K.
EE247 Lecture 22 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Figures of merit (FOM) and trends for ADCs How to use/not use FOM Oversampled ADCs EECS 247 Lecture 22:
More informationEE247 Lecture 24. EE247 Lecture 24
EE247 Lecture 24 Administrative EE247 Final exam: Date: Wed. Dec. 15 th Time: 12:30pm3:30pm Location: 289 Cory Closed book/course notes No calculators/cell phones/pdas/computers Bring one 8x11 paper
More informationEE247 Lecture 27. EE247 Lecture 27
EE247 Lecture 27 Administrative EE247 Final exam: Date: Wed. Dec. 19 th Time: 12:30pm3:30pm Location: 70 Evans Hall Extra office hours: Thurs. Dec. 13 th, 10:am2pm Closed course notes/books No calculators/cell
More informationEE247 Lecture 26. EE247 Lecture 26
EE247 Lecture 26 Administrative Project submission: Project reports due Dec. 5th Please make an appointment with the instructor for a 15minute meeting on Monday Dec. 8 th Prepare to give a 3 to 7 minute
More informationEE247 Lecture 26. EE247 Lecture 26
EE247 Lecture 26 Administrative Final exam: Date: Tues. Dec. 13 th Time: 12:3pm3:3pm Location: 285 Cory Office hours this week: Tues: 2:3p to 3:3p Wed: 1:3p to 2:3p (extra) Thurs: 2:3p to 3:3p Closed
More informationTones. EECS 247 Lecture 21: Oversampled ADC Implementation 2002 B. Boser 1. 1/512 1/161/64 b1. 1/10 1 1/4 1/4 1/8 k1z 1 1z 1 I1. k2z 1.
Tones 5 th order Σ modulator DC inputs Tones Dither kt/c noise EECS 47 Lecture : Oversampled ADC Implementation B. Boser 5 th Order Modulator /5 /6/64 b b b b X / /4 /4 /8 kz  z  I kz  z  I k3z
More informationEE247 Lecture 25. Oversampled ADCs (continued)
EE247 Lecture 25 Oversampled ADCs (continued) Higher order ΣΔ modulators Last lecture Cascaded ΣΔ modulators (MASH) (continued) Singleloop singlequantizer modulators with multiorder filtering in the
More informationBandPass SigmaDelta Modulator for wideband IF signals
BandPass SigmaDelta Modulator for wideband IF signals Luca Daniel (University of California, Berkeley) Marco Sabatini (STMicroelectronics Berkeley Labs) maintain the same advantages of BaseBand converters
More informationSigmaDelta ADC Tutorial and Latest Development in 90 nm CMOS for SoC
SigmaDelta ADC Tutorial and Latest Development in 90 nm CMOS for SoC Jinseok Koh Wireless Analog Technology Center Texas Instruments Inc. Dallas, TX Outline Fundamentals for ADCs Oversampling and Noise
More informationINF4420. ΔΣ data converters. Jørgen Andreas Michaelsen Spring 2012
INF4420 ΔΣ data converters Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Oversampling Noise shaping Circuit design issues Higher order noise shaping Introduction So far we have considered
More informationESE 531: Digital Signal Processing
ESE 531: Digital Signal Processing Lec 11: February 20, 2018 Data Converters, Noise Shaping Lecture Outline! Review: MultiRate Filter Banks " Quadrature Mirror Filters! Data Converters " Antialiasing
More informationCHAPTER. deltasigma modulators 1.0
CHAPTER 1 CHAPTER Conventional deltasigma modulators 1.0 This Chapter presents the traditional first and secondorder DSM. The main sources for nonideal operation are described together with some commonly
More informationLecture #6: AnalogtoDigital Converter
Lecture #6: AnalogtoDigital Converter All electrical signals in the real world are analog, and their waveforms are continuous in time. Since most signal processing is done digitally in discrete time,
More informationESE 531: Digital Signal Processing
ESE 531: Digital Signal Processing Lec 12: February 21st, 2017 Data Converters, Noise Shaping (con t) Lecture Outline! Data Converters " Antialiasing " ADC " Quantization " Practical DAC! Noise Shaping
More informationECE 627 Project: Design of a HighSpeed DeltaSigma A/D Converter
ECE 627 Project: Design of a HighSpeed DeltaSigma A/D Converter Brian L. Young youngbr@eecs.oregonstate.edu Oregon State University June 6, 28 I. INTRODUCTION The goal of the Spring 28, ECE 627 project
More informationOversampling Converters
Oversampling Converters Behzad Razavi Electrical Engineering Department University of California, Los Angeles Outline Basic Concepts First and SecondOrder Loops Effect of Circuit Nonidealities Cascaded
More informationLecture Outline. ESE 531: Digital Signal Processing. AntiAliasing Filter with ADC ADC. Oversampled ADC. Oversampled ADC
Lecture Outline ESE 531: Digital Signal Processing Lec 12: February 21st, 2017 Data Converters, Noise Shaping (con t)! Data Converters " Antialiasing " ADC " Quantization "! Noise Shaping 2 AntiAliasing
More informationLecture 390 Oversampling ADCs Part I (3/29/10) Page 3901
Lecture 390 Oversampling ADCs Part I (3/29/0) Page 390 LECTURE 390 OVERSAMPLING ADCS PART I LECTURE ORGANIZATION Outline Introduction Deltasigma modulators Summary CMOS Analog Circuit Design, 2 nd Edition
More information! MultiRate Filter Banks (con t) ! Data Converters. " Antialiasing " ADC. " Practical DAC. ! Noise Shaping
Lecture Outline ESE 531: Digital Signal Processing! (con t)! Data Converters Lec 11: February 16th, 2017 Data Converters, Noise Shaping " Antialiasing " ADC " Quantization "! Noise Shaping 2! Use filter
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 5: Data Conversion ADC Background/Theory Examples Background Physical systems are typically analogue To apply digital signal processing, the analogue signal
More informationChapter 2: Digitization of Sound
Chapter 2: Digitization of Sound Acoustics pressure waves are converted to electrical signals by use of a microphone. The output signal from the microphone is an analog signal, i.e., a continuousvalued
More informationMASH 21 MULTIBIT SIGMADELTA MODULATOR FOR WLAN L 2 ( ) ( ) 1( 1 1 1
MASH 2 MULTIBIT SIGMADELTA MODULATOR FOR WLAN Yu hang, Ning Xie, Hui Wang and Yejun He College of Information Engineering, Shenzhen University, Shenzhen, Guangdong 58060, China kensouren@yahoo.com.cn
More informationOversampling Data Converters Tuesday, March 15th, 9:15 11:40
Oversampling Data Converters Tuesday, March 15th, 9:15 11:40 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Last time and today, Tuesday 15th of March:
More informationCascaded NoiseShaping Modulators for Oversampled Data Conversion
Cascaded NoiseShaping Modulators for Oversampled Data Conversion Bruce A. Wooley Stanford University B. Wooley, Stanford, 2004 1 Outline Oversampling modulators for A/D conversion Cascaded noiseshaping
More informationEE247 Midterm Exam Statistics
EE247 Lecture 22 Pipelined ADCs (continued) Effect gain stage, subdac nonidealities on overall ADC performance Digital calibration (continued) Correction for interstage gain nonlinearity Implementation
More informationECEN 610 MixedSignal Interfaces
Spring 2014 S. HoyosECEN610 1 ECEN 610 MixedSignal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Oversampling ADC Spring 2014 S. HoyosECEN610 2 Spring 2014 S. HoyosECEN610
More informationLecture 10, ANIK. Data converters 2
Lecture, ANIK Data converters 2 What did we do last time? Data converter fundamentals Quantization noise Signaltonoise ratio ADC and DAC architectures Overview, since literature is more useful explaining
More informationDesign of Bandpass DeltaSigma Modulators: Avoiding Common Mistakes
Design of Bandpass DeltaSigma Modulators: Avoiding Common Mistakes R. Jacob Baker and Vishal Saxena Department of Electrical and Computer Engineering Boise State University 1910 University Dr., ET 201
More informationSystemonChip. Oversampling and LowOrder ΔΣ Modulators. Overview. Principle of oversampling. Speed vs. accuracy of ADCs. Principle of oversampling
SystemonChip Overview Principle of oversampling Oversampling and LowOrder ΔΣ Modulators Noise shaping st order ΣΔ modulator nd order ΣΔ modulator Pietro Andreani Dept. of Electrical and Information
More informationNPTEL. VLSI Data Conversion Circuits  Video course. Electronics & Communication Engineering.
NPTEL Syllabus VLSI Data Conversion Circuits  Video course COURSE OUTLINE This course covers the analysis and design of CMOS AnalogtoDigital and DigitaltoAnalog Converters,with about 7 design assigments.
More informationPipeline vs. Sigma Delta ADC for Communications Applications
Pipeline vs. Sigma Delta ADC for Communications Applications Noel O Riordan, MixedSignal IP Group, S3 Semiconductors noel.oriordan@s3group.com Introduction The AnalogtoDigital Converter (ADC) is a key
More informationAnalog to Digital Conversion
Analog to Digital Conversion Florian Erdinger Lehrstuhl für Schaltungstechnik und Simulation Technische Informatik der Uni Heidelberg VLSI Design  Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg
More informationFundamentals of Data Converters. DAVID KRESS Director of Technical Marketing
Fundamentals of Data Converters DAVID KRESS Director of Technical Marketing 9/14/2016 Analog to Electronic Signal Processing Sensor (INPUT) Amp Converter Digital Processor Actuator (OUTPUT) Amp Converter
More informationData Converters. Oversampling and LowOrder ΔΣ Modulators. Overview. Speed vs. accuracy of ADCs. Principle of oversampling. Principle of oversampling
Data Converters Overview Principle of oversampling Oversampling and LowOrder ΔΣ Modulators Noise shaping st order ΔΣ modulator nd order ΔΣ modulator Pietro Andreani Dept. of Electrical and Information
More informationNOISE IN SC CIRCUITS
ECE37 Advanced Analog Circuits Lecture 0 NOISE IN SC CIRCUITS Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen Understanding of CMOS analog circuit
More informationUnderstanding DeltaSigma Data Converters
Understanding DeltaSigma Data Converters Richard Schreier Analog Devices, Inc. Gabor C. Temes Oregon State University OlEEE IEEE Press iwiley INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION Foreword
More informationOutline. Noise and Distortion. Noise basics Component and system noise Distortion INF4420. Jørgen Andreas Michaelsen Spring / 45 2 / 45
INF440 Noise and Distortion Jørgen Andreas Michaelsen Spring 013 1 / 45 Outline Noise basics Component and system noise Distortion Spring 013 Noise and distortion / 45 Introduction We have already considered
More informationSecondOrder SigmaDelta Modulator in Standard CMOS Technology
SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 1, No. 3, November 2004, 3744 SecondOrder SigmaDelta Modulator in Standard CMOS Technology Dragiša Milovanović 1, Milan Savić 1, Miljan Nikolić 1 Abstract:
More informationDesign Examples. MEAD March Richard Schreier. ANALOG DEVICES R. SCHREIER ANALOG DEVICES, INC.
Design Examples MEAD March 008 Richard Schreier Richard.Schreier@analog.com ANALOG DEVICES Catalog nd Order Lowpass Architecture: Singlebit, switchedcapacitor Application: Generalpurpose, lowfrequency
More informationINTRODUCTION TO DELTASIGMA ADCS
ECE37 Advanced Analog Circuits Lecture INTRODUCTION TO DELTASIGMA ADCS Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen understanding of CMOS
More informationA 2.5 V 109 db DR ADC for Audio Application
276 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.4, DECEMBER, 2010 A 2.5 V 109 db DR ADC for Audio Application Gwangyol Noh and GilCho Ahn Abstract A 2.5 V feedforward secondorder deltasigma
More informationDesign and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009
Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009 Introduction The first thing in design an ADC is select architecture of ADC that is depend on parameters like bandwidth, resolution,
More informationAppendix A Comparison of ADC Architectures
Appendix A Comparison of ADC Architectures A comparison of continuoustime deltasigma (CT ), pipeline, and timeinterleaved (TI) SAR ADCs which target wide signal bandwidths (greater than 100 MHz) and
More informationTelecommunication Electronics
Politecnico di Torino ICT School Telecommunication Electronics C5  Special A/D converters» Logarithmic conversion» Approximation, A and µ laws» Differential converters» Oversampling, noise shaping Logarithmic
More informationElectronic Noise. Analog Dynamic Range
Electronic Noise Dynamic range in the analog domain Resistor noise Amplifier noise Maximum signal levels TowThomas Biquad noise example Implications on power dissipation EECS 247 Lecture 4: Dynamic Range
More information6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers
6.976 High Speed Communication Circuits and Systems Lecture 17 Advanced Frequency Synthesizers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Bandwidth Constraints
More informationADVANCES in VLSI technology result in manufacturing
INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2013, VOL. 59, NO. 1, PP. 99 104 Manuscript received January 8, 2013; revised March, 2013. DOI: 10.2478/eletel20130012 Rapid Prototyping of ThirdOrder
More informationSIGMADELTA CONVERTER
SIGMADELTA CONVERTER (1995: Pacífico R. Concetti Western A. GeophysicalArgentina) The SigmaDelta A/D Converter is not new in electronic engineering since it has been previously used as part of many
More informationChoosing the Best ADC Architecture for Your Application Part 3:
Choosing the Best ADC Architecture for Your Application Part 3: Hello, my name is Luis Chioye, I am an Applications Engineer with the Texas Instruments Precision Data Converters team. And I am Ryan Callaway,
More informationEE247 Lecture 11. SwitchedCapacitor Filters (continued) Effect of nonidealities Bilinear switchedcapacitor filters Filter design summary
EE47 Lecture 11 SwitchedCapacitor Filters (continued) Effect of nonidealities Bilinear switchedcapacitor filters Filter design summary Comparison of various filter topologies Data Converters EECS 47
More informationA 98dB 3.3V 28mWperchannel multibit audio DAC in a standard 0.35µm CMOS technology
A 98dB 3.3V 28mWperchannel multibit audio DAC in a standard 0.35µm CMOS technology M. Annovazzi, V. Colonna, G. Gandolfi, STMicroelectronics Via Tolomeo, 2000 Cornaredo (MI), Italy vittorio.colonna@st.com
More informationCascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University
Cascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University Bruce A. Wooley  1  Copyright 2005, Stanford University Outline Oversampling modulators for AtoD conversion
More informationAnalogtoDigital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999
AnalogtoDigital Converter Survey & Analysis Update: July 16,1999 References: 1. R.H. Walden, Analogtodigital converter survey and analysis, IEEE Journal on Selected Areas in Communications, vol. 17,
More informationAnalog and Telecommunication Electronics
Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D6  High speed A/D converters» Spectral performance analysis» Undersampling techniques» Sampling jitter» Interleaving
More informationEnhancing Analog Signal Generation by Digital Channel Using PulseWidth Modulation
Enhancing Analog Signal Generation by Digital Channel Using PulseWidth Modulation Angelo Zucchetti Advantest angelo.zucchetti@advantest.com Introduction Presented in this article is a technique for generating
More informationQuick View. Analog input time. Oversampling & pulse density modulation fs (sampling rate) >> fn (Nyquist rate)
SigmaDelta ADC Quick View Analog input time Oversampling & pulse density modulation sampling rate >> fn Nyquist rate One bit digital output Higher input > more 's Lower input > more 's Oversampling ratio
More informationMultirate DSP, part 3: ADC oversampling
Multirate DSP, part 3: ADC oversampling Li Tan  May 04, 2008 Order this book today at www.elsevierdirect.com or by calling 18005452522 and receive an additional 20% discount. Use promotion code 92562
More informationOutline. Discrete time signals. Impulse sampling ztransform Frequency response Stability INF4420. Jørgen Andreas Michaelsen Spring / 37 2 / 37
INF4420 Discrete time signals Jørgen Andreas Michaelsen Spring 2013 1 / 37 Outline Impulse sampling ztransform Frequency response Stability Spring 2013 Discrete time signals 2 2 / 37 Introduction More
More informationImproved SNR Integrator Design with Feedback Compensation for Modulator
Improved SNR Integrator Design with Feedback Compensation for Modulator 1 Varun Mishra, 2 Abhishek Bora, 3 Vishal Ramola 1 M.Tech Student, 2 M.Tech Student, 3 Assistant Professor 1 VLSI Design, 1 Faculty
More informationEE247 Lecture 9. Sampling Sine Waves Frequency Spectrum
EE247 Lecture 9 Switchedcapacitor filters (continued) Example of antialiasing prefilter for S.. filters Switchedcapacitor network electronic noise Switchedcapacitor integrators DDI integrators LDI
More informationData Converter Topics. Suggested Reference Texts
Data Converter Topics Basic Operation of Data Converters Uniform sampling and reconstruction Uniform amplitude quantization Characterization and Testing Common ADC/DAC Architectures Selected Topics in
More informationTHE USE of multibit quantizers in oversampling analogtodigital
966 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 57, NO. 12, DECEMBER 2010 A New DAC Mismatch Shaping Technique for Sigma Delta Modulators Mohamed Aboudina, Member, IEEE, and Behzad
More informationEE247 Lecture 11. SwitchedCapacitor Filters (continued) Effect of nonidealities Bilinear switchedcapacitor filters Filter design summary
EE247 Lecture 11 SwitchedCapacitor Filters (continued) Effect of nonidealities Bilinear switchedcapacitor filters Filter design summary Comparison of various filter topologies Data Converters EECS 247
More informationElectronics A/D and D/A converters
Electronics A/D and D/A converters Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED December 1, 2014 1 / 26 Introduction The world is analog, signal processing nowadays is
More informationChapter 2 Analysis of Quantization Noise Reduction Techniques for FractionalN PLL
Chapter 2 Analysis of Quantization Noise Reduction Techniques for FractionalN PLL 2.1 Background High performance phase lockedloops (PLL) are widely used in wireless communication systems to provide
More informationCONTINUOUSTIME (CT) ΔΣ modulators have gained
530 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 56, NO. 7, JULY 009 DT Modeling of Clock PhaseNoise Effects in LP CT ΔΣ ADCs With RZ Feedback Martin Anderson, Member, IEEE, and
More informationAN ABSTRACT OF THE THESIS OF. Title: Effects and Compensation of the Analog Integrator Nonidealities in Dual GAL C. Temes
AN ABSTRACT OF THE THESIS OF Yaohua Yang for the degree of Master of Science in Electrical & Computer Engineering presented on February 20, 1993. Title: Effects and Compensation of the Analog Integrator
More informationAdvanced AD/DA converters. ΔΣ DACs. Overview. Motivations. System overview. Why ΔΣ DACs
Advanced AD/DA converters Overview Why ΔΣ DACs ΔΣ DACs Architectures for ΔΣ DACs filters Smoothing filters Pietro Andreani Dept. of Electrical and Information Technology Lund University, Sweden Advanced
More informationINF4420 Switched capacitor circuits Outline
INF4420 Switched capacitor circuits Spring 2012 1 / 54 Outline Switched capacitor introduction MOSFET as an analog switch ztransform Switched capacitor integrators 2 / 54 Introduction Discrete time analog
More informationEE247 Lecture 11. Example: Switchedcapacitor filters in CODEC integrated circuits. Switchedcapacitor filter design summary
EE47 Lecture 11 Filters (continued) Example: Switchedcapacitor filters in CODEC integrated circuits Switchedcapacitor filter design summary Comparison of various filter topologies New Topic: Data Converters
More informationEE247 Lecture 11. EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics 2009 H. K. Page 1. Typical Sampling Process C.T. S.D. D.T.
EE247 Lecture Data converters Sampling, aliasing, reconstruction Amplitude quantization Static converter error sources Offset Fullscale error Differential nonlinearity (DNL) Integral nonlinearity (INL)
More informationDesign Of Multirate Linear Phase Decimation Filters For Oversampling Adcs
Design Of Multirate Linear Phase Decimation Filters For Oversampling Adcs Phanendrababu H, ArvindChoubey Abstract:This brief presents the design of a audio pass band decimation filter for DeltaSigma analogtodigital
More informationEE 230 Lecture 39. Data Converters. Time and Amplitude Quantization
EE 230 Lecture 39 Data Converters Time and Amplitude Quantization Review from Last Time: Time Quantization How often must a signal be sampled so that enough information about the original signal is available
More informationA VERY HIGH SPEED BANDPASS CONTINUOUS TIME SIGMA DELTA MODULATOR FOR RF RECEIVER FRONT END A/D CONVERSION K. PRAVEEN JAYAKAR THOMAS
A VERY HIGH SPEED BANDPASS CONTINUOUS TIME SIGMA DELTA MODULATOR FOR RF RECEIVER FRONT END A/D CONVERSION K. PRAVEEN JAYAKAR THOMAS (B. Tech., Madras Institute of Technology, Anna University) A THESIS
More informationEE247 Lecture 27 Today:
EE247 Lecture 27 Today: ΣΔ Modulator (continued) Examples of systems utilizing analogdigital interface circuitry Acknowledgements EECS 247 Lecture 27: Oversampled ADCs Cont'd & Final Remarks 2005 H. K.
More informationA KDelta1Sigma Modulator for Wideband AnalogtoDigital Conversion
A KDelta1Sigma Modulator for Wideband AnalogtoDigital Conversion Abstract : R. Jacob Baker and Vishal Saxena Department of Electrical and Computer Engineering Boise State University jbaker@boisestate.edu
More informationOneBit Delta Sigma D/A Conversion Part I: Theory
OneBit Delta Sigma D/A Conversion Part I: Theory Randy Yates mailto:randy.yates@sonyericsson.com July 28, 2004 1 Contents 1 What Is A D/A Converter? 3 2 Delta Sigma Conversion Revealed 5 3 Oversampling
More informationINF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen
INF4420 Switched capacitor circuits Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Switched capacitor introduction MOSFET as an analog switch ztransform Switched capacitor integrators
More informationChapter 2 DDSM and Applications
Chapter DDSM and Applications. Principles of DeltaSigma Modulation In order to explain the concept of noise shaping in detail, we start with a standalone quantizer (see Fig..a) with a small number of
More informationThe Baker ADC An Overview Kaijun Li, Vishal Saxena, and Jake Baker
The Baker ADC An Overview Kaijun Li, Vishal Saxena, and Jake Baker An ADC made using the KDelta1Sigma modulator, invented by R. Jacob Baker in 2008, and a digital filter is called a Baker ADC or Baker
More informationCyberPhysical Systems ADC / DAC
CyberPhysical Systems ADC / DAC ICEN 553/453 Fall 2018 Prof. Dola Saha 1 AnalogtoDigital Converter (ADC) Ø ADC is important almost to all application fields Ø Converts a continuoustime voltage signal
More informationA/D Conversion and Filtering for Ultra Low Power Radios. Dejan Radjen Yasser Sherazi. Advanced Digital IC Design. Contents. Why is this important?
1 Advanced Digital IC Design A/D Conversion and Filtering for Ultra Low Power Radios Dejan Radjen Yasser Sherazi Contents A/D Conversion A/D Converters Introduction ΔΣ modulator for Ultra Low Power Radios
More informationNational Instruments Flex II ADC Technology The Flexible Resolution Technology inside the NI PXI5922 Digitizer
National Instruments Flex II ADC Technology The Flexible Resolution Technology inside the NI PXI5922 Digitizer Kaustubh Wagle and Niels Knudsen National Instruments, Austin, TX Abstract Singlebit deltasigma
More informationHow to turn an ADC into a DAC: A 110dB THD, 18mW DAC using sampling of the output and feedback to reduce distortion
How to turn an ADC into a DAC: A 110dB THD, 18mW DAC using sampling of the output and feedback to reduce distortion Axel Thomsen, Design Manager Silicon Laboratories Inc. Austin, TX 1 Why this talk? A
More informationGábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/25
Gábor C. Temes School of Electrical Engineering and Computer Science Oregon State University temes@ece.orst.edu 1/25 Noise Intrinsic (inherent) noise: generated by random physical effects in the devices.
More informationRELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE
RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE Mehdi Taghizadeh and Sirus Sadughi Department of Electrical Engineering, Science and Research Branch,
More informationSummary of Last Lecture
EE47 Lecture 7 DAC Converters (continued) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Sampling switch
More informationAnalog and Telecommunication Electronics
Politecnico di Torino  ICT School Analog and Telecommunication Electronics D5  Special A/D converters» Differential converters» Oversampling, noise shaping» Logarithmic conversion» Approximation, A and
More informationData Conversion Techniques (DAT115)
Data Conversion Techniques (DAT115) Hand in Report Second Order Sigma Delta Modulator with Interleaving Scheme Group 14N Remzi Yagiz Mungan, Christoffer Holmström [ 1 20 ] Contents 1. Task Description...
More informationBasic Concepts and Architectures
CMOS SigmaDelta Converters From Basics to Stateof oftheart Basic Concepts and Architectures Rocío del Río, R Belén PérezVerdú and José M. de la Rosa {rocio,belen,jrosa}@imse.cnm.es KTH, Stockholm,
More informationChapter 2 Basics of SigmaDelta Modulation
Chapter 2 Basics of SigmaDelta Modulation The principle of sigmadelta modulation, although widely used nowadays, was developed over a time span of more than 25 years. Initially the concept of oversampling
More informationAn Overview of the Decimation process and its VLSI implementation
MPRA Munich Personal RePEc Archive An Overview of the Decimation process and its VLSI implementation Rozita Teymourzadeh and Masuri Othman UKM University 1. February 2006 Online at http://mpra.ub.unimuenchen.de/41945/
More informationLOW SAMPLING RATE OPERATION FOR BURRBROWN
LOW SAMPLING RATE OPERATION FOR BURRBROWN TM AUDIO DATA CONVERTERS AND CODECS By Robert Martin and Hajime Kawai PURPOSE This application bulletin describes the operation and performance of BurrBrown
More informationActive Filter Design Techniques
Active Filter Design Techniques 16.1 Introduction What is a filter? A filter is a device that passes electric signals at certain frequencies or frequency ranges while preventing the passage of others.
More information10 bit Delta Sigma D/A Converter with Increased S/N ratio Using Compact Adder Circuits
International Journal of Scientific & Engineering Research, Volume 4, Issue 8, August 2013 10 bit Delta Sigma D/A Converter with Increased S/N ratio Using Compact Adder Circuits Jyothish Chandran G, Shajimon
More information