A Wide Tuning Range (1 GHz-to-15 GHz) Fractional-N All-Digital PLL in 45nm SOI

Transcription

1 7- A Wide Tuning Range ( GHz-to-5 GHz) Fractional-N All-Digital PLL in 45nm SOI Alexander Rylyakov, Jose Tierno, George English 2, Michael Sperling 2, Daniel Friedman IBM T. J. Watson Research Center Yorktown Heights, NY 0598 USA 2 IBM, Poughkeepsie, NY

2 Outline Motivation Review of DPLL linear model DPLL architecture, digital design details Measurement results Conclusion

3 Digital PLL Advantages Uses primarily technology elements of digital designs, simplifies technology support and should make yield profile match that of logic Enables extensive use of digital flows for design and verification, offers enhanced controllability and adaptability Compact: no explicit filter capacitor Ideal for ASIC, processor or any digital clocking application, where period jitter is the key metric

4 Charge-pump PLL vs BB-DPLL Fref Ffbk KPFD = Fref Ffbk ICP 2π PFD+CP 2π σ BB PFD K R + Cs + LF VCO Fout Linear PFD N Continuously tuned VCO Continuous-time K z z P I LF N KVCO s KDCO z Fout DCO Bang-bang PFD Discrete DCO Discrete-time

5 Bang-bang PFD Linearization Φ ref + BB PFD ± = sign(φ ref - Φ fbk ) Φ fbk Φ ref Φ fbk K PFD e PFD KPFD= Φ - ref - Φ fbk 2 π σ Φ ref + Φ ref - Φ fbk K PFD *(Φ ref - Φ fbk ) + e PFD Φ fbk - Assumptions: Gaussian jitter uncorrelated quantization noise Razavi 2004

6 Proportional-Integral Loop Filter z z KI ) ( + = z z K K z H I P I CP V CTRL Cs R s Z ) ( + = R C KP = + = + = Tz z s st T j e z T j ω ω (ωt << ) C T KI = + = + z z C T R Cs R R KP = analog and digital proportional-integral loop filters are equivalent

7 DCO Linear Model and Control word Quantization Noise DCO Fout VCO Fout Fout Quantizer f = K DCO e DCO L = Control word Fout VCO 2 f 2 f OFFSET f REF Example: f =0 MHz, f REF = 200 MHz results in -74 dbc/hz at MHz offset Note that DCO resolution of f = 0 MHz requires a ~9 bit DAC for 4 GHz range increasing DCO resolution to further reduce f requires a >0 bit DAC dithering can reduce DAC precision requirements

8 Linear Model of the BB-DPLL Fref Ffbk KPFD = 2π σ BB PFD K P + K I z z LF DCO KDCO z Fout N Noise sources: Quantization noise of the bang-bang PFD Quantization noise of the DCO Phase noise of the oscillator Quantization noise of the feedback divider (fractional-n) Kratyuk 2007, Hanumolu 2007, Da Dalt 2008

9 Bode Magnitude Plot Magnitude [db] Frequency [Hz] Fref=200 MHz N = 20 σ = 4 ps K P = 0.75 K I = 2-8 K DCO = 20 MHz linear model reflects the main features of the measured phase noise: high bandwidth (~ 40 MHz), limit cycle (~ 7 db peaking) not a substitute of full VHDL or Verilog time-domain simulation with noise, but useful for ballpark estimates

10 DPLL Block Diagram reference PFD early/late LF inc/dec frac DSM dither DCO output phold clkg /N /,2 or 4 N.FN DSM all gates are static CMOS (no CML, etc) 3 custom cells: in the PFD, in the DCO, plus voltage level shifter between the DCO and the logic power supplies highly modular design: loop filter (LF), multimodulus feedback divider (/N) and both DSMs use the same adder

11 Loop Filter Late 2 +I +P+I -P-I -I Realized Transfer Functions integral: X z - proportional: ( z - ) X z P = Proportional constant I = Integral constant Inc Dec Fractional Frequency 8-bit arithmetic realized using Kogge-Stone adder merging proportional, integral paths simplifies DPLL logic

12 DCO Dithering f+ f F VCO instantaneous frequency effective frequency f time Uniform dithering: L = 2 f 2 f OFFSET f DITH -8 dbc/hz at MHz offset, f=0 MHz, f DITH = GHz st order Σ dithering: L = 2 f f OFFSET 2 f DITH 2 sin π f f DITH 2-05 dbc/hz at MHz offset, f=0 MHz, f DITH = GHz Σ dithering works, but increases power dissipation, area, complexity

13 Analog vs Digital Σ modulator Analog st order Σ modulator: in + not needed in digital version: carry generation results in overflow and integrator is reset automatically Digital implementation: - in D/A carry (out) err + Z - digital quantizer is very easy: use the MSB out not needed in a digital circuit in + z - err = carry + err z - *err digital Σ modulator is a simple integrator, quantization noise is st order shaped carry = in + (z - ) err

14 Divider DSM vs DCO DSM Requires explicit 8-bit adders Requires signed arithmetic Pipelining requires careful latency matching for proper noise shaping Uses DCO as an adder Generates DC offset (invisible due to loop action) Dithering outputs are applied in parallel with matched delays N+FN+(z - -)*e N+FN+(z - -) 2 *e 2 N + Z DCO N Z - Z - Z - Z - Z - Z - Z - e e + Z- + Z- e 2 + Z- + Z- e 2

15 DPLL Internal Clocking Multi-modulus divider /N phold clkg divided clkg + const Timing diagram output clkg phold divided clkg phold is a masking signal divided clkg is compared with reference in PFD const can be updated between phold rising edges

16 DCO Schematic inc/dec dither <:3> output top row r o w s to 6 main array inv_on 2 3 columns to 48 row/column control inc/dec 784 delay cells (73 µm x 4 µm in 45nm CMOS) this is a ~ 9.5-bit DAC

17 Block Diagram: Annotated early/late +I +P+I -P -I -I inc/dec frac inc/dec reference PFD early/late phold LF frac /N DSM dither clkg DCO /,2 or 4 output N.FN DSM N FN

18 Frequency [GHz] DCO Tuning Curves 65 C 25 C.3 V 0.7 V DCO Fill Factor.0 V covers 2 GHz to 6 GHz range across wide V,T variations

19 KDCO [MHz per step] 30 DCO Gain vs Frequency V.0 V 0.7 V 5 ma 5 ma 0 ma Frequency [GHz] constant-current DCO bias enables trading off DCO tuning range for increase in DCO resolution

20 Period Jitter Histogram Output: 2.06 GHz Reference: 2.06 MHz Period jitter: 2.5 ps rms, 29 ps peak to peak 0.75 V, 65 C Time [ps] 494 main metric for digital clocking applications: peak to peak jitter ( shortest clock cycle at a given frequency ) long term jitter (N-cycle or rms integrated from phase noise) is less of a concern phase noise purity usually not a factor

21 Integer and Fractional-N Period Jitter Histograms , 3 rd order , st order 2 9.5, 3 rd order 2 9.5, st order 9, no DSM Time [ps] st order DSM is adequate for digital clocking applications fractional-n mode could be used to save power

22 Fractional-N Operation at GHz, 200 MHz reference Frequency Error [Hz] Fractional N value synthesized frequency deviation from ideal: 0.2 ppm pp limited by the sensitivity of the frequency counter

23 Output Spectrum at 5 GHz Power [dbm] Frequency [GHz] limited by the output driver, not by the DCO

24 Phase Noise at 4. GHz -60 Power [dbc/hz] Frequency Offset [Hz] high bandwidth, limit cycle are clearly visible overall shape follows linear model predictions acceptable for digital clocking applications

25 Physical Design 75µm Transistor Count: ~25k 60µm Technology: IBM 45nm SOI CMOS Divider-DSM Divider Loop Filter Row DCO-DSM DCO Control Column Control

26 Performance Summary CMOS Technology 45 nm SOI Area 75 µm X 60 µm Power Dissipation * DCO Logic.7 mw 6.9 mw Tuning Range 0.84 GHz 3.3 GHz (.0V, 65 C).2 GHz 5.9 GHz (.3V, 65 C) Period Jitter *.2 ps rms, 3.0 ps pp * at 4.2 GHz (206 MHz reference),.0v, 65 C

27 Conclusions All static CMOS, all-digital, fractional-n PLL demonstrated in 45 nm SOI Highly modular design: all key blocks (loop filter, feedback divider, DCO-DSM, divider-dsm) use instances of the same 8-bit Kogge-Stone adder Tuning range and period jitter performance adequate for ASIC and microprocessor clocking applications

28 Acknowledgements IBM Yorktown: B. Parker, D. Kuchta, S. Gowda and M. Soyuer IBM Poughkeepsie: P. Muench, G. Smith and R. Dussault Partial support through DARPA contract HR