AN ABSTRACT OF THE DISSERTATION OF. Volodymyr Kratyuk for the degree of Doctor of Philosophy in

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2 AN ABSTRACT OF THE DISSERTATION OF Volodymyr Kratyuk for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on December 12, Title: Digital Phase-Locked Loops for multi-ghz Clock Generation. Abstract approved: Kartikeya Mayaram Un-Ku Moon A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved performance similar to that of analog PLLs. However, there is an upper bound on the bandwidth of a DPLL and this limits its capability to track an input signal. The research described in this thesis is focused on new digital PLL architectures that overcome this bandwidth limitation in linear as well as in digital PLLs. A systematic design procedure for a second-order digital phase-locked loop with a linear phase detector is proposed. The design procedure is based on the analogy between a type-ii second-order analog PLL and a digital PLL. A new digital PLL architecture featuring a linear phase detector which eliminates the noise-bandwidth tradeoff is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and a low jitter. The measured results obtained from the prototype

3 chip demonstrate a significant jitter improvement with the STDC. A bang-bang digital PLL employing an adaptive tracking technique and a novel frequency acquisition scheme achieves a wide tracking range and fast frequency acquisition. The DPLL operates over a wide frequency range from 0.6GHz to 2GHz. The adaptive tracking mechanism detects PLL slewing by monitoring the output of the binary phase detector and corrects the VCO frequency to prevent loss of lock. The experimental results illustrate a tracking bandwidth improvement of 100%. As a result, this DPLL is suitable for applications employing spread-spectrum clocking. A fast frequency lock is achieved with a novel frequency detector which extracts the frequency error from the feedback divider in a PLL.

4 c Copyright by Volodymyr Kratyuk December 12, 2006 All Rights Reserved

5 Digital Phase-Locked Loops for multi-ghz Clock Generation by Volodymyr Kratyuk A DISSERTATION submitted to Oregon State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Presented December 12, 2006 Commencement June 2007

6 Doctor of Philosophy dissertation of Volodymyr Kratyuk presented December 12, APPROVED: Co-Major Professor, representing Electrical and Computer Engineering Co-Major Professor, representing Electrical and Computer Engineering Director of the School of Electrical Engineering and Computer Science Dean of the Graduate School I understand that my dissertation will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my dissertation to any reader upon request. Volodymyr Kratyuk, Author

7 ACKNOWLEDGMENTS First of all I would like to thank my academic advisors, Prof. Kartikeya Mayaram and Prof. Un-Ku Moon, for convincing me to stay at Oregon State University for the Ph.D. program. More than three years have passed from that time but I still remember our conversation in the Beanery coffee shop. Also I deeply appreciate their advising and great help in my research. Special thanks are due to Pavan Kumar Hanumolu for helping me on various circuit design problems. Also I would like to thank MinGyu Kim, Gil-Cho Ahn, Jose Silva, Jose Ceballos, Robert Batten, Merrick Brownlee, and Ting Wu for useful discussions and help with technical questions. I would like to thank Semiconductor Research Corporation (SRC) and Center for Design of Analog-Digital Integrated Circuits (CDADIC) for funding my research. Also, I am very thankful to Samsung Electronics for IC fabrication. Speaking about numerous classes I took at OSU, I would like to thanks Prof. Mayaram for his very knowledgeable and systematic lectures and perfect class notes, Prof. Moon for his insightful explanations of circuit design issues, Prof. Lucchese for introducing me to the world of digital signal processing and Prof. Roger Traylor for his excellent class VLSI system design. I am very grateful to Prof. Jimmy Yang, Prof. Roger Traylor, Dr. Oleg Mikulchenko and Prof. Pavan Kumar Hanumolu for finding time to participate in my Ph.D. committee. Special thanks go to design managers of SPG/PREAMP group at Texas Instruments Ashish Manjrekar and Brian Bloodworth. They kindly allow me to be a part of their team as an intern and introduce me to the real world of the high competitive semiconductor industry.

8 I would like to thank all my friends and colleagues from Owen245/KEC4130 for all the good time spent together and friendship. I am very thankful to my parents for showing me the proper way to lead life and for their love and support. And finally, I would like to thank my wife Myroslava and my son Andriy for their love, patience, understanding and support. This thesis is dedicated to them.

9 TABLE OF CONTENTS Page 1 INTRODUCTION Phase-Locked Loop Basics Overview of Digital PLLs Motivation and Contribution Thesis Organization A DESIGN PROCEDURE FOR DIGITAL PHASE-LOCKED LOOPS Introduction TDC resolution A design flow for a DPLL s-domain model for a second-order DPLL Design of a second-order CPPLL Calculation of the digital loop filter coefficients A transformation from an analog to a digital loop filter using an impulse invariant transform Relationship between K P and K I Design example Summary A DIGITAL PLL WITH A STOCHASTIC TIME-TO-DIGITAL CON- VERTER Introduction TDC - prior art Stochastic time-to-digital converter Principle of operation Analysis of the STDC Implementation of the STDC

10 TABLE OF CONTENTS (Continued) Page 3.4 Digital PLL architecture Analysis of the Digital PLL Circuit design Bang-bang PFD Digital loop filters Current steering DAC Delta-sigma modulator Fine loop DAC Digitally controlled oscillator Experimental Results Summary A 0.6 TO 2GHZ DIGITAL PLL WITH WIDE TRACKING RANGE Introduction Dynamics of a DPLL with a bang-bang phase detector Improving tracking capability of bang-bang DPLLs A Frequency Detector for Fast Frequency Lock of Digital PLLs Operation of the new frequency detector Frequency-locked loop architecture Simulation results DPLL architecture Circuit Design Measured results Summary CONCLUSION

11 TABLE OF CONTENTS (Continued) Page BIBLIOGRAPHY

12 LIST OF FIGURES Figure Page 1.1 Block diagram of a phase-locked loop Block diagram of a digital phase-locked loop A typical implementation of a P2D converter Transfer characteristic of P2D Linear model of P2D s-domain approximation of the DPLL s-domain model for a second-order CPPLL Transform from an analog to a digital loop filter Magnitude and phase responses of the DPLL Step response for a digital PLL. (a) PM=50.3. (b) PM=19.6. (c) PM= Noise sources in a digital PLL Noise transfer functions Delay line based TDC Transfer characteristic of a TDC Vernier delay line based TDC TDC with parallel delay elements Multibit TDC. (a) 1 bit, (b) 2 bit, and (c) L bit Operation of the stochastic TDC Stochastic TDC Stochastic TDC simulation results The block diagram of an arbiter Arbiter decision circuit

13 LIST OF FIGURES (Continued) Figure Page 3.13 Block diagram of the proposed DPLL z-domain model of the DPLL s fine loop Magnitude and phase responses of the DPLL s fine loop Bang-bang PFD Digital loop filter Current steering DAC Active current mirror Delta-sigma modulator Fine loop DAC Digitally controlled oscillator Chip micrograph DPLL spectra DPLL jitter with the coarse loop only DPLL jitter with the fine loop Bang-bang digital PLL Frequency tracking by a bang-bang DPLL Improving tracking range by proportional gain boosting Adaptive tracking mechanism Adaptive tracking mechanism: (a) state diagram of the finitestate machine, (b) frequency tracking operation with a time varying reference clock Proposed frequency detector Suggested PLL architecture z-domain model of the FLL

14 LIST OF FIGURES (Continued) Figure Page 4.9 Loop filter output Block diagram of the proposed DPLL Bang-bang phase-frequency detector Digitally controlled oscillator Voltage controlled oscillator Die micrograph Power spectral density Time domain DPLL output DPLL input modulation tolerance DPLL jitter Frequency locking behavior of the DPLL

15 LIST OF TABLES Table Page 2.1 Summary of DPLL designs Performance summary DPLL performance summary

16 DIGITAL PHASE-LOCKED LOOPS FOR MULTI-GHZ CLOCK GENERATION CHAPTER 1. INTRODUCTION Recent advances in integrated circuit (IC) technology are oriented towards making fabrication processes suitable for digital designs. Complex digital systems with a wide range of functionality and small area and low power consumption are mandated by market requirements. Such systems are currently implemented using ever shrinking process technology. Although systems of today are designed with a digital paradigm, analog blocks are still required for these systems on a chip (SoC). Analog circuits such as clock generators, input-output (IO) interface circuits, temperature sensors, voltage fault detectors are necessary in many applications. The design of analog circuits in a fabrication process optimized for a digital design poses many difficulties. Gate current leakage, component mismatches, layout dependent I-V characteristics of MOS transistors, and many more effects make analog design in a deep submicron process a very challenging task [1]. To alleviate all these problems digital equivalent implementations of analog circuits should be used whenever possible. One advantage of a digital implementation is the inherent noise immunity of digital circuits. Another advantage of a digital design is its scalability and easy redesign with process changes or shrinks. Since analog blocks are present in a number of digital and mixed-signal ICs, their redesign is an important factor in the release of a new product. However, the performance requirements of analog blocks necessitates

17 2 a complete redesign in a new process, thereby increasing the design cycle time. Reducing the amount of analog circuitry can improve the redesign time of these mixed-signal ICs. Due to above mentioned reasons, research in the area of digital equivalent implementations of analog and RF circuits is in great demand now. This thesis, in particular, is focused on the digital implementation of phase-locked loops. Phaselooked loops (PLLs) are important and often performance limiting building blocks in modern SoCs. They are used for clock generation and distribution, frequency synthesis, clock and data recovery, etc. 1.1 Phase-Locked Loop Basics A phase-locked loop is a negative feedback system which aligns the phases of the input and output signals. A block diagram of a simple PLL is shown in Fig A phase detector (PD) compares the phase of the input signal F REF to the phase of the output signal F CKV and generates an output that is proportional to the phase difference. The output of the PD is filtered by the loop filter and then used to control the frequency of a voltage controlled oscillator. An optional divider ( N) can be used in the feedback path for frequency multiplication. Figure 1.1: Block diagram of a phase-locked loop. The negative feedback in a PLL has to correct any phase misalignment re-

18 3 sulting from the internal or external noise sources. If the input and output phases are aligned, the PLL is in phase lock. 1.2 Overview of Digital PLLs There are many ways to implement a PLL. A PLL can be built using only analog, only digital, or both, analog and digital circuits. A digital PLL (DPLL) is a PLL built mostly from digital circuits. Figure 1.2: Block diagram of a digital phase-locked loop. A simplified block diagram of the digital PLL is shown in Fig It consists of a phase-to-digital converter (P2D), a digital loop filter (DLF), a digitallycontrolled oscillator (DCO) and a feedback divider. The P2D senses the phase difference between the reference clock F REF and the DCO divided clock F CKV and converts it to a digital format. This information is filtered by the digital LF and then is used to control the DCO. In the case of a ring oscillator based DCO, frequency tuning can be performed digitally by turning on and off bias current sources. When an LC based DCO is employed, frequency tuning is done by switching on and off tank capacitors. The P2D can be implemented in many different ways. By sampling F REF with F CKV using a D-type flip-flop, the sign of the phase error can be determined. This 1-bit phase digitizer is called a bang-bang or binary phase detector. A linear

19 4 phase digitizing can be performed by a time-to-digital converter (TDC), which measures the time difference between the rising edges of F REF and F CKV clocks. If the frequency error has to be determined together with the phase error, a more sophisticated approach should be taken. Figure 1.3: A typical implementation of a P2D converter. One way to implement a P2D converter, shown in Fig. 1.3, features a conventional phase-frequency detector (PFD) followed by a time-to-digital converter. The PFD produces up (UP) and down (DN) pulses. They are overlapped by an OR gate to create a pulse, the width of which is proportional to the absolute value of the phase error. The width of this pulse is digitized by a TDC with a resolution T DC and an L-bit output ABS is produced. The D-type flip-flop samples the UP pulse on the rising edge of the DN pulse. In this manner, the sign of the phase-frequency error can be determined. 1.3 Motivation and Contribution The design of PLLs becomes even more challenging in a deep submicron processes. Increased gate leakage currents prevent the use of MOS capacitors in a loop filter (LF) which leads to bigger area occupied by a loop filter. The I- V characteristics of MOS transistors become layout dependent and thus device

20 5 matching is a more complicated task. Therefore, it is beneficial to utilize digital circuitry as much as possible. In addition to eliminating the above mentioned problems, a digital implementation of a PLL does not have the noise susceptible analog control for a voltage controlled oscillator (VCO). Recently, several digital PLLs (DPLLs) for different applications (including multi-ghz ones) have been reported [2, 3, 4, 5]. They demonstrate the ability of a digital implementation to achieve the performance of analog PLLs and even outperform them. In spite of many advantages of digital PLLs, they present several circuit design bottlenecks that limit their performance. In the design of a digital PLL, the digital loop filter parameters have to be determined based on specifications. A systematic design procedure for a secondorder digital phase-locked loop with a linear phase detector is proposed in this work. The design procedure is based on the analogy between a type-ii secondorder analog PLL and a digital PLL. The conventional way to digitize phase error in a DPLL is by employing a chain of minimum-sized inverters. This leads to poor resolution and, thus, to high phase-quantization error. Therefore, a high resolution phase-to-digital converter is needed to improve the noise performance of the DPLL. In order to create a high resolution phase digitizer, a stochastic approach is explored in this thesis. As a result, a new digital PLL architecture which employs a high resolution stochastic time-to-digital converter (STDC) was developed. Due to the high resolution TDC, the proposed DPLL doesn t need a low bandwidth to filter noise from the TDC. Bang-bang type digital PLLs employ a binary or bang-bang phase detector to determine only the sign of the phase error. Bang-bang DPLLs suffer from a jitter versus tracking range trade-off. A higher VCO frequency step is required for the larger tracking range, but it also adds more noise into the system. An

21 6 adaptive approach to the frequency tracking problem is investigated in this thesis to overcome the above-mentioned trade-off. The implemented adaptive tracking mechanism detects when the DPLL cannot keep up with the reference frequency changes by monitoring the output of the binary phase detector. Then, the VCO frequency gets corrected accordingly to prevent loss of lock. The proposed DPLL achieves fast frequency lock with a novel frequency detector which extracts the frequency error from a feedback divider. 1.4 Thesis Organization Since the focus of this thesis is the design of digital PLLs, Chapter 2 presents a systematic design procedure for a second-order digital phase-locked loop. The design procedure is based on the the analogy between a type-ii second-order analog PLL and a digital PLL. A new dual-loop digital PLL architecture is presented in Chapter 3. It employs a stochastic time-to-digital converter (STDC) and a high frequency deltasigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. Chapter 4 discusses a DPLL that uses a new adaptive technique to obtain twice the tracking range of a conventional bang-bang DPLL while achieving a wide frequency tuning range of 0.6GHz to 2GHz. This DPLL also employs a new frequency detector for fast frequency locking. Conclusions and suggestions for future research directions are highlighted in Chapter 5.

22 CHAPTER 2. A DESIGN PROCEDURE FOR DIGITAL PHASE-LOCKED LOOPS 2.1 Introduction Analog PLLs (Fig. 1.1) have been investigated for the past several decades. As a result, different types and orders of analog PLLs have been analyzed and procedures for their design have been developed. Second-order analog PLLs have been analyzed by Hein and Scott [6] and Gardner [7]. Several other references [8, 9, 10] provide an analysis and design procedure for third-order charge-pump PLLs (CP- PLLs). But there is only limited research dedicated to the analysis of digital PLLs. Phase-domain all-digital phase-locked loops have been analyzed in [3] and [11]. In [12] the root locus technique has been applied to analyze the effect of the digital loop filter parameters on the bandwidth and stability of a DPLL. However, none of these publications presents a procedure for designing a digital PLL given required bandwidth and phase margin specifications. This chapter is focused on a design approach for type-ii second-order digital PLLs, and forms the basis for a systematic design procedure starting from the DPLL specifications. In general, the proposed approach can be extended for the design of digital PLLs with different types and orders. The DPLL of Fig. 1.2 has a structure and operation very similar to a secondorder charge-pump PLL. The principal difference is that the phase error information is processed in different domains. In the digital PLL, the UP and DN pulses

23 8 are overlapped and the result is digitized and processed by a digital filter. For the CPPLL, a charge pump (CP) is used to generate a charge which is proportional to the time difference between the UP and DN pulses. The resulting charge is pumped into the analog filter, the output voltage of which controls the VCO. This similarity allows one to extend the design procedure for a second-order CPPLL to a second-order DPLL. 2.2 TDC resolution The operation of a DPLL fully depends on the TDC resolution, since it defines the resolution of the phase detector. Assuming that the period of the reference signal T REF remains unchanged over time, the time resolution of the TDC T DC can be converted in to a phase resolution of the phase-to-digital converter Φ as: Φ = 2π T DC T REF (2.1) Fig. 2.1 shows a representative characteristic of the P2D, where the input phase difference is noted as Φ error. The relation between Φ error and the phase resolution of the P2D determines the applicability of a linear analysis for the DPLL. If the input phase error Φ error is smaller than the resolution of the P2D converter, the behavior of the P2D is no different from a bang-bang phase detector. A linear analysis is not applicable in this case and thus the bandwidth in a strict sense is not defined. The interested reader is referred to [13] for further discussion on this topic. On the other hand, if the input phase error Φ error is much larger than the resolution of the P2D converter, the input phase error is digitized in a linear

24 9 Figure 2.1: Transfer characteristic of P2D. manner. The P2D can be modeled as a gain of 1/ Φ plus quantization noise as in Fig Having a linear phase detector allows us to use linear techniques for the analysis of DPLLs. The noise contribution of a TDC is given in [14]. Figure 2.2: Linear model of P2D. 2.3 A design flow for a DPLL It is beneficial to have a clear procedure for calculating the DPLL parameters. Given a set of specifications, which usually include the phase margin (P M), the unity gain bandwidth (ω UGBW ) and the reference frequency (F REF ), a designer should choose the loop filter parameters. This task can be accomplished by comparing s-domain models for digital and charge-pump PLLs. A conventional charge-pump PLL has three poles and a zero. The third pole is introduced in order to attenuate the ripple which appears due to the nature of the charge-pump PLL.

25 10 In digital PLLs this problem does not exist, and a second-order PLL is sufficient s-domain model for a second-order DPLL Figure 2.3: s-domain approximation of the DPLL. An s-domain approximation for the second-order DPLL is shown in Fig The phase-frequency detector together with the OR gate converts the input phase error into an output pulse of width t. The transfer function of the PFD can be approximated as: P F D(s) = T REF 2π (2.2) The pulse width t is digitized by a time-to-digital converter with a resolution of T DC. Usually the resolution of the TDC is limited to one inverter delay and is considered to be fixed in our design approach. The transfer function of this operation can be approximated as: T DC(s) = 1 T DC (2.3) Combining Eqs. (2.2) and (2.3), the joint PFD and TDC transfer function (P2D) can be obtained:

26 11 P 2D(s) = T REF 2π T DC (2.4) The phase error in the digital domain is filtered by a first-order digital loop filter and then fed to the DCO with a transfer function given by Eq. (2.5). DCO(s) = K DCO s (2.5) When comparing this model to the s-domain model for a second-order chargepump PLL (Fig. 2.4), it can be seen that they are the same if: I CP = T REF T DC K V CO = K DCO Z(s) = H(s) (2.6) "!$#&% ' ()"*,+.-/( Figure 2.4: s-domain model for a second-order CPPLL. Thus, in order to design a DPLL given a set of specifications, first a CPPLL can be designed. Then the specific parameters of the DPLL can be calculated based on the relationships given in Eq. (2.6).

27 Design of a second-order CPPLL Let us consider I CP and K V CO as pre-determined constants. For the DPLL I CP is equivalent to the ratio of a reference clock period T REF to the resolution of the TDC ( T DC ), and K V CO is equivalent to K DCO. A loop filter for the second-order CPPLL consists of a capacitor and a resistor connected in series. The capacitor value C and the resistor value R are the only unknowns. The open loop gain of the CPPLL in Fig. 2.4 is given by: where ω z is the zero frequency: LG(s) = I CP 2π K V CO s 1 N s + ω z R (2.7) s ω z = 1 RC (2.8) The phase margin for this system is given by: P M = arctan( ω UGBW ω z ) (2.9) From Eq. (2.9) the required zero frequency ω z can be found: way as: ω z = ω UGBW tan(p M) (2.10) Based on LG(jω UGBW ) = 1, the resistance value R can be found in a unique R = 2πN I CP K V CO 2 ω z ωz2 + ω 2 UGBW Then, from Eqs. (2.8) and (2.10), the capacitance value C is found to be: (2.11)

28 13 C = tan(p M) Rω UGBW (2.12) Calculation of the digital loop filter coefficients A digital equivalent of an analog loop filter consists of a proportional path with a gain K P and an integral path with a gain K I. The parameters of a digital loop filter K P and K I can be obtained from the parameters of an analog loop filter R and C by using the bilinear transform (Fig. 2.5). The bilinear transform (Eq. (2.13)) is commonly used to design digital filters based on their analog prototypes [15]: s = 2 T s 1 z z 1 (2.13) where T s is the sampling time of a discrete-time system, which is the inverse of the reference frequency in our case. Figure 2.5: Transform from an analog to a digital loop filter. Our goal is to preserve the frequency response and stability of the system, thus the bilinear transform is an obvious choice. The only disadvantage of the bilinear transform is frequency warping. This affects the frequency response at

29 14 frequencies close to the Nyquist rate. Since the bandwidth of the PLL is at least 10 times smaller than the update rate, frequency warping will have a negligible effect. The z-domain transfer function of the digital loop filter is given by Eq. (2.14), where K P represents the proportional part and K I represents the integral part of the loop filter gain. H(z) = K P + K I 1 1 z 1 = (K P + K I ) K P z 1 1 z 1 (2.14) The s-domain transfer function of the analog loop filter, given by Eq. (2.15), can be converted to the z-domain via the bilinear transform (Eq. (2.19)). Z(s) = V (s) I(s) = R + 1 sc (2.15) Z(s) s z = ( Ts 2C + R) + z 1 ( Ts 2C R) 1 z 1 (2.16) Comparing Eqs. (2.14) and (2.19), K P and K I can be found: K P = R T s 2C K I = T s C (2.17) where K P and K I are the only unknown parameters that need to be determined for the DPLL design at this stage.

30 2.3.4 A transformation from an analog to a digital loop filter using an impulse invariant transform 15 Other transforms, such as an impulse invariant transform, can also be used for transformation of an analog loop filter into a digital loop filter. The impulseinvariant transform was developed to preserve the shape of an impulse response during conversion from an s-domain to a z-domain representation. This transform was used in [6] to develop a discrete-time model for a PLL. The impulse response of the analog loop filter is found by applying the inverse Laplace transform to Eq. (2.15): h a (t) = Rδ(t) + 1 u(t) (2.18) C According to the impulse-invariant property, the shape of the continuous time impulse response h a (t) should be the same as the shape of the discrete-time impulse response h[n]. By sampling Eq. (2.18) with a period T s and then applying the z-transform to the resulting h[n], the z-domain loop filter transfer function is found to be: Z(z) = R + T s C(1 z 1 ) Comparing Eqs. (2.14) and (2.19), K P and K I can be found: (2.19) K P = R K I = T s C K I is the same as in Eq. (2.17) but K P (2.20) is different. It will be shown later, that this difference is not significant in the hardware implementation of a digital

31 16 loop filter Relationship between K P and K I As a consequence of the analysis presented above, a simple relationship between the proportional gain K P and the integral gain K I (obtained by the bilinear transform) can be established. From Eq. (2.17), the ratio of K P to K I is found to be: Eq. (2.21). K P K I = RC T s 1 2 (2.21) Then R and C from Eqs. (2.11) and (2.12), respectively, are substituted in K P K I = 1 T s tan(p M) ω UGBW 1 2 (2.22) Given that T s = 1/F REF and ω UGBW = 2πF UGBW, Eq. (2.22) can be expressed as: K P = F REF tan(p M) 1 K I F UGBW 2π 2 (2.23) It can be seen from Eq. (2.23) that for a given DPLL reference frequency F REF and a unity gain bandwidth F UGBW, the K P to K I ratio defines the phase margin and thus the stability of a system.

32 Design example To validate the proposed approach, a digital PLL with the following specifications has been designed. Phase margin P M = 45. Unity gain bandwidth F UGBW = 1MHz. Reference frequency F REF = 80MHz. Feedback divider N = 16. DCO gain K DCO = 1MHz/LSB TDC resolution T DC = 20ps The phase margin has been intentionally chosen to be 45 in order to have ringing in the PLL s step response. This allows for better visual comparison of the step responses obtained by different methods. If a conventional inverter chain based TDC is used, fine resolution ( T DC = 20ps) is possible only in a deepsubmicron CMOS process. There are other types of TDC as in [16] and [17] which can overcome this limitation. The calculation starts with Eq. (2.10) from which, using the specifications for the unity gain bandwidth and phase margin, the required zero frequency is found to be ω z = rad/s. Given the DCO gain K DCO, the resolution of the TDC, T DC, and the period of the reference clock T s = 1/F REF, I CP and K V CO are determined from Eq. (2.6). Based on that, the equivalent resistance R = Ω is calculated from the Eq. (2.11). Then the equivalent capacitance C = F is determined using Eq. (2.12). Finally, the digital loop filter

33 18 parameters K P and K I have been determined from Eq. (2.17). For easy hardware implementation the coefficients of the digital loop filter have to be approximated as power of two values: K P = = 2 3 K I = = 2 7. The above approximation affects the effective loop bandwidth and phase margin of the designed DPLL. For the designed DPLL, the effective phase margin is P M = 50.3 and the effective unity gain bandwidth is UGBW = 1.01MHz. A calculation of K P and K I can also be done using Eq. (2.20) to yield: K P = = 2 3 K I = = 2 7. After approximating K P and K I as power of two values for easy hardware implementation, the coefficients are the same as those obtained from Eq. (2.17). Intuitively, this result is not surprising, because the K P value obtained from the impulse invariant transform differs from that obtained from the bilinear transform only by: K P = T s 2C = K I 2 (2.24) Since K I is usually much smaller than K P, K P does not affect the K P value after making the power of two approximation. The magnitude and phase responses of the analog prototype, the analog prototype with coefficients approximated for the digital implementation, and the resulting DPLL have been calculated and are shown in Fig In Fig. 2.6, peaking

34 19 of the magnitude responses is due to the low phase margin. An s-domain prototype inaccurately models a DPLL at frequencies close to the Nyquist rate, thus there are differences between the frequency responses at higher frequencies. Since the unity gain bandwidth of the DPLL is a factor of 80 smaller than its reference frequency, the phase and frequency responses of the analog prototype and the DPLL transfer functions are in good agreement in the band of interest. Magnitude (db) Analog prototype 10 Analog prot. with approx. coef. 20 ADPLL Phase (deg) Frequency (Hz) Figure 2.6: Magnitude and phase responses of the DPLL. The step response has been used to validate the design. Fig. 2.7 (a) shows two step responses obtained in different ways. The dashed line represents the step response calculated in MATLAB from the s-domain transfer function using the

35 20 Amplitude Time domain simulation MATLAB calculation PM=50.3 o (a) Amplitude PM=19.6 o (b) Amplitude PM=74.4 o Time (µs) (c) Figure 2.7: Step response for a digital PLL. (a) PM=50.3. (b) PM=19.6. (c) PM=74.4.

36 21 step function. The solid line shows the step response obtained by a time-domain simulation of the designed digital PLL in Simulink. It can be seen that the plots are in good agreement. This demonstrates that the designed DPLL behaves similar to the initial s-domain prototype. The results from the time domain simulation of the CPPLL are not shown in this figure because of ripples. However, the filtered step response matches the s-domain calculations. Two additional digital PLLs for a target UGBW = 1MHz and target phase margins of 20 and 80 have been designed. Their step responses are shown in Figs. 2.7 (b) and (c). Once again, it is seen that the s-domain prototype and the DPLL behave similarly. Table 2.1 summarizes the loop filter parameters and the effective P M and UGBW for all three DPLL designs. Table 2.1: Summary of DPLL designs. Target PM K P K I K P K I PM UGBW, MHz Summary In this chapter, a simple and systematic procedure for the design of a secondorder digital PLL has been presented. Closed-form expressions have been derived for the digital loop filter parameters. Based on this analysis a DPLL can be easily

37 22 designed from specifications. The procedure presented in this paper has been used for the design of a oversampled (F REF F UGBW ) second-order digital PLL where the s-domain approximation has proven to be sufficiently accurate in the design of traditional/analog PLLs. A time-domain step response simulation is in good agreement with a calculation of the step response in MATLAB using the DPLL transfer function.

38 CHAPTER 3. A DIGITAL PLL WITH A STOCHASTIC TIME-TO-DIGITAL CONVERTER 3.1 Introduction A block diagram of a digital PLL is shown in Fig It consists of a timeto-digital converter (TDC), which performs the function of a phase detector (PD), a digital loop filter (DLF), a digitally-controlled oscillator (DCO) and a feedback divider. The TDC senses the time difference between the reference clock F REF and the DCO divided clock F CKV and converts it to a digital format. The time resolution of the TDC ( T DC ) is related to the phase resolution Φ by Eq. (3.1). The digitized phase error information is filtered by the DLF and then used to control the DCO. In the case of a ring oscillator based DCO, frequency tuning can be performed by digitally turning on and off bias current sources. When an LC based DCO is employed, frequency tuning is done by switching on and off the tank capacitors. Φ = 2π T DC T REF (3.1) There are two major sources of noise in digital PLLs. They are quantization noise from the time to digital converter and oscillator noise, indicated in Fig. 3.1 by S QT DC and S Φ, respectively. The contributions of these two noise sources to the overall DPLL noise are affected by the loop dynamics. Fig. 3.2 shows repre-

39 24 SQTDC SΦ Figure 3.1: Noise sources in a digital PLL. sentative magnitude responses of the noise transfer functions. The quantization noise from the TDC is suppressed by the low-pass transfer function of the PLL. However, oscillator noise is filtered by a high-pass transfer function. Therefore, the DPLL architecture of Fig. 3.1 suffers from conflicting requirements on the DPLL bandwidth. The filtering of the quantization noise from TDC requires a low DPLL Figure 3.2: Noise transfer functions. bandwidth while the suppression of the DCO phase noise mandates a high bandwidth. In order to alleviate this bandwidth trade-off, existing high-performance digital PLLs employs low noise LC oscillators [5, 18]. This allows to keep the DPLL bandwidth small and, thus, to filter phase-quantization noise from the TDC. On the contrary, the focus of the research described in this chapter is to use a ring oscillator and extend the DPLL bandwidth to achieve enough suppression of the oscillator phase noise. Thus, a high resolution TDC is needed to reduce the amount

40 25 of quantization noise added. 3.2 TDC - prior art A significant amount of research has been done in prior years to identify ways to build a high resolution time-to-digital converter. As a result, many time digitizing methods are described in the literature. The simplest TDC is based on a delay line composed of buffers with a delay time T DEL (Fig. 3.3). Inverters are used in [14] for the delay line. As the signal F CKV propagates through the delay line, the output of each buffer is flipped after time T DEL. When the F REF signal arrives, the outputs of all buffers are read into a register and then decoded. The digital output D error is a code that represents the time difference between two signals with a resolution of T DEL. Figure 3.3: Delay line based TDC. Despite its simplicity and ease of implementation, this approach suffers from several drawbacks. The resolution of such a TDC depends on process variations and ambient conditions, and, furthermore, is limited by the time delay of a single buffer. A delay-locked loop (DLL) can be utilized to calibrate the delay line [19] and make the resolution tolerant to process variations and ambient conditions. But, buffers with controlled delay are needed for the DLL operation. Such buffers

41 26 have larger delay than buffers with fixed delay due to the control circuitry. Thus, the use of controlled delay buffers increases the lower limit on the resolution of the TDC. Figure 3.4: Transfer characteristic of a TDC. The coarse resolution of such a TDC results in large quantization noise added to the system which can be suppressed only by a low DPLL bandwidth. Fig. 3.4 shows a representative transfer characteristic of a TDC. The x-axis indicates the input phase error Φ and the y-axis is the digital output word of the TDC. As can be seen, the quantization error of a TDC is proportional to its resolution. The power spectral density (PSD) of the noise resulting from the phase-quantization error is given by Eq. (3.2). S QT DC = Φ2 12F REF (3.2) A time-to-digital converter, proposed in [16], is based on a Vernier delay line. The Vernier delay line utilizes two delay chains as shown in Fig The upper delay chain consists of buffers with delay T DEL1 while the lower delay chain has buffers with delay T DEL2. Assume that F REF comes before F V CO and T DEL1 is greater than T DEL2. As signals F REF and F CKV propagate through the delay lines, the time difference between them is decreased by T R = T DEL1 T DEL2 after each

42 27 stage. The position in the delay line, at which both signals are at the same time, defines the time difference between them with resolution T R. The resolution of Figure 3.5: Vernier delay line based TDC. this TDC does not depend on the delays of the unit elements used in the delay chains, but rather on their difference. Therefore, time intervals that are smaller than a single inverter delay in a given process can be measured. This approach also utilizes a DLL for calibration purposes. The calibration is done on a replica delay line. Since calibration and measurements are done using different delay lines, their matching is a big concern in this approach, especially in a deep sub-micron process. Also, the calibrating DLL is usually composed of analog circuits and thus is not consistent with a digital PLL concept. Another way to achieve a resolution better than a single delay element is described in [20]. A delay line consisting of parallel buffers is utilized in this technique as shown in Fig The delay of each buffer differs from that of the previous one by a certain time T DEL, which is set by adding a load capacitance. The F CKV signal propagates through the buffers, whose outputs are sampled by

43 28 a register when the F REF signal arrives. Clearly, such an approach suffers from random mismatches of both the delay elements and the load capacitors. Figure 3.6: TDC with parallel delay elements. All of the above mentioned methods for time digitizing suffer from random mismatches. Their performance will degrade as the IC industry moves further towards deep submicron processes. In this work, a new digital PLL with a TDC, similar to the one in [21], that uses random mismatches is proposed. This method overcomes the weakness of the other approaches, to achieve high resolution and thus low phase-quantization noise. 3.3 Stochastic time-to-digital converter Principle of operation A stochastic time-to-digital converter (STDC) exploits the stochastic properties of a set of latches to achieve high resolution. Let us first consider a one bit time to digital converter that is implemented with one latch as shown in Fig. 3.7 (a). There are two inputs to the latch, signal 1 and signal 2. If signal 2 arrives after signal 1 crosses the threshold V T H of the latch, that is after time t T H, the TDC

44 29 will report a +1, otherwise the TDC will report a -1. In other words, the 1-bit TDC behaves as a bang-bang phase detector. Fig. 3.7 (b) shows a 2-bit TDC that employs three latches with different thresholds. The different thresholds can be created by giving an input offset voltage to each latch. The output value of such a TDC is defined by the time when signal 2 comes. For example, if it comes after time t T H2 but before t T H3, the output of the TDC will be a +1, that is after signal 1 crosses V T H2, but before it crosses V T H3. In the same way, an L-bit TDC can be realized with 2 L 1 latches (Fig. 3.7 (c)). Assuming that the signal slope is constant over all voltage threshold spreads, it can be concluded that the thresholds in time are proportional to the voltage thresholds. Figure 3.7: Multibit TDC. (a) 1 bit, (b) 2 bit, and (c) L bit. A set of latches or arbiters exhibit random mismatches resulting from process variations. Thus, latches have inherent input offset voltages that create different

45 30 thresholds for each latch. By providing the same input signal to all latches and summing their outputs, a precise time difference between the two input signals can be determined. An input voltage offset is affected by different mismatch sources in a latch. Therefore, according to the Central Limit Theorem [22], the distribution of the input voltage offsets will be approximately normal or Gaussian. In Fig. 3.8 the outputs of all latches are summed, that is equivalent to the integration of a Gaussian distributed random variable. Thus, the time difference to the output code characteristic of the STDC has a shape similar to that of the error function. Figure 3.8: Operation of the stochastic TDC Analysis of the STDC According to the previously made assumption, the voltage threshold in arbiters has a Gaussian distribution. As has been mentioned earlier, thresholds in time are proportional to the voltage thresholds. Thus, the time thresholds are also normally distributed. The standard deviation of the time thresholds σ t is related to that of voltage thresholds σ v by Eq. (3.3): σ t = σ v SL (3.3)

46 31 where SL is the slope of a signal. The distribution of the time thresholds is given by Eq. (3.4) under a zero mean assumption: f T (t) = 1 e t 2 2σ t 2 (3.4) 2πσt where T is a random variable of the time thresholds, and σ t is the standard deviation of the time thresholds. Assume that the first signal arrives at time t = 0. Given the number of arbiters N ARBS, the digital output of the STDC when the time difference between two signals is t d, can be determine by Eq. (3.5). This equation is the time-to-digital characteristic of a stochastic TDC. D ST DC = N ARBS P (T t d ) = N ARBS td 1 e t 2 2σ t 2 dt. (3.5) 2πσt The most important property of a TDC in a digital PLL is the gain. Since the time-to-digital characteristic of the stochastic TDC (Eq. (3.5)) is not linear, the gain changes depending on the input time difference t d. If a DPLL is in lock, the input time difference t d is close to zero, and thus, the gain of the STDC can be determined for the in-lock condition by taking the time derivative of Eq. (3.5) when t d = 0 (Eq. (3.6)): G ST DC = N ARBS 2πσt (3.6) Since 99.7% of the normally distributed data lies in an interval of ±3σ t, this value can be considered as a limit of the linear operation for an STDC. If the input

47 32 time difference exceeds the ±3σ t range, an STDC saturates and is able to report only its maximum or minimum value. The resolution of the STDC in the vicinity of a zero input time difference is the inverse of the STDC gain (Eq. (3.7)): T DC = 1 G ST DC = 2πσt N ARBS (3.7) Implementation of the STDC A 6-bit stochastic TDC was implemented and consists of a set of latches and a digital encoder (Fig. 3.9). Fig shows a behavioral simulation of a stochastic TDC with 20 realizations. The digital output code D ST DC is plotted versus the input time difference t d. The solid black line represents calculations performed using Eq. (3.5). This simulation illustrates that the time-to-digital characteristic of a stochastic TDC is linear. Figure 3.9: Stochastic TDC. Each arbiter in Fig. 3.9 consists of an arbiter circuit itself followed by an SR-latch and a D flip-flop as shown in Fig Shown in Fig. 3.12, an arbiter circuit [21] determines which signal comes first and generates an SB or RB signal. An SR-latch after the arbiter reduces the probability of getting into the metastable

48 Output code Input time difference (ps) Figure 3.10: Stochastic TDC simulation results. state. The output of the SR-latch is sampled by a D flip-flop giving a 1-bit output to the encoder. The clock for the sampling D flip-flop should arrive after the SRlatch is set but before it might change state due to the falling edges of the input signals. A quadrature clock derived from the DCO divided output has been used in our case. Figure 3.11: The block diagram of an arbiter.

49 34 Figure 3.12: Arbiter decision circuit. 3.4 Digital PLL architecture A block diagram of the proposed DPLL architecture is shown in Fig It consists of two loops: a fine loop and a coarse loop. On power up only the coarse loop is active. In the coarse loop the bang-bang PFD (!!PFD) senses only the sign of the phase and the frequency difference between the reference signal F REF and the divided oscillator clock F CKV. This information is filtered by the 12-bit digital loop filter (DLF1), truncated and passed to the 8-bit DAC. The DAC converts a digital word into a current value which controls the digitally-controlled oscillator. The DCO has two control inputs for the coarse and fine loops. The lock detector (LD) monitors the output of the bang-bang PFD and decides whether the coarse loop is in lock. If so, the LD freezes the coarse loop and activates the fine loop. The stochastic TDC works as a phase detector in the fine loop. It measures the time difference between the rising edges of the reference signal F REF and the divided oscillator clock F CKV. The measured time difference has the phase information embedded in it. The 6-bit digital output of the STDC is filtered by