An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop

Transcription

1 An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop Abstract: With increased levels of integration in modern system-on-chips, the coupling of supply noise in a phase locked loop (PLL) has become the dominant source of performance degradation in many systems. In this paper, an all-digital approach to canceling the effects of supply noise is presented. By sensing the supply noise using an analog-to-digital converter (ADC), an observer controller loop filter jointly processes the ADC and phase detector outputs to determine the oscillator control signals that minimize the output jitter. The proposed digital PLL is shown to be significantly more robust to supply noise compared with a conventional PLL. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx Enhancement of the project: Existing System: PHASE-LOCKED loop (PLL) is an integral component of frequency synthesizers and clock generators, both of which are widely used in digital, analog, and radio-frequency integrated systems. More recently, digital PLL (DPLL) has been developed to exploit the digital signal processing capabilities of modern process technologies [1] [4]. The primary difference from a conventional analog PLL is the use of a time-to-digital converter (TDC) and digitalcontrolled oscillator (DCO), enabling an all-digital loop filter. A simplified block diagram of a DPLL is shown in Fig. 1. Compared with the conventional analog PLL, DPLL enjoys several implementation advantages: 1) robustness to circuit nonidealities, such as charge pump feedthrough and mismatches; 2) compatibility with deep-submicrometer CMOS process; and 3) simplified testing and calibration.

2 Fig. 1. Simplified block diagram of a DPLL. Much of the existing work on alleviating the effects of supply noise are based on supply voltage regulation. A low-dropout regulator is employed to shield the DCO from variations in the supply voltage. In practice, this shielding is not ideal. Furthermore, with the scaling down of supply voltages, the available voltage headroom of the DCO becomes limited. More recently, the supply voltage is digitally regulated to operate at the DCO s least sensitive voltage [9], but the magnitude of interferers it can suppress may be limited by the flatness of this optimal operating voltage. An alternative approach to linear regulation is to cancel the effects of supply noise. Existing cancellation approaches sense the supply voltage then drive active circuit elements embedded in the DCO in a feedforward fashion to cancel the phase shift caused by the supply noise. Although voltage headroom is not reduced, such cancellation approach suffers from several potential drawbacks, most of which arise from the nonidealities of the embedded active circuit elements. The primary drawback is that the addition of supply noise canceling circuit itself increases phase noise. In addition, the circuit must be kept linear, limiting the allowed magnitude of the supply voltage noise, and must be calibrated to track temperature drifts. In [10], foreground calibration was employed, whereas used background calibration. Disadvantages: output noise and jitter is high Proposed System: This section discusses the implementation issues of the proposed observer controller DPLL. Observer Structure

3 In the observer, Δθ[k k 1] and v[k k 1] are updated recursively based on observations y1[k] and y2[k]. As the elements of the Kalman gain matrix G R(M+2) 2 in (16) are nonzero, the estimate of supply voltage v[k] depends on both the supply ADC and the TDC outputs. The observer structure is shown in Fig. 3. It consists of a recursive estimator for Δθ[k] and v[k]. The estimate of Δθ[k] is updated based on the difference between the actual and the estimated PD output (i.e., y1[k] Δθ[k k 1]), the control signals u1[k] and u2[k], the estimate of supply noise v[k], and the difference between the actual and the estimated ADC output (i.e., y2[k] v[k k 1]). The Δθ[k] estimator has a structure of a classical second-order PLL with proportional and integral gains of g1,1 and g2,1, respectively, but with control signals and supply noise v[k] estimate incorporated in the recursion. The v[k] estimator is an AR moving average (ARMA) filter with an Mth-order AR and second-order moving average components. The ARMA model is driven by the difference of the actual and estimated ADC output, i.e., y2[k] v[k k 1]. The v[k] estimator structure in Fig. 3 is realized as a cascade of adders, which can add significant delay. Instead of this directform realization, which is chosen for the clarity of explanation, the transposed form can be used to reduce the critical path at the expense of increased capacitance at the input bus. In practice, a combination of direct and indirect transposed forms can be used.

4 Controller Structure Fig. 2. Observer structure to estimate Δθ [k k 1], Δω[k k 1], and v[k k 1]. Based on the observer state variables, the controller generates the DCO input signal e[k].

5 the L-step predicted DCO control word e[k + L] can be readily determined, as shown in Fig. 3. The input signals to the controller, namely, Δω[k + 1 k], Δθ[k + 1 k], and v[k + 1 k], are obtained from the observer internal nodes, as labeled in Fig. 2. As in the observer structure, the cascade of adders drawn for the clarity of explanation adds to the critical path. Fig. 3. Observer structure to compute DCO control word e[k].

6 Supply-Sensing ADC Unlike the supply-sensing circuits reported, which may need to support bandwidths in excess of 10 GHz, the proposed DPLL requirements are much more relaxed, since the supply noise attenuation of the proposed DPLL is limited to the Nyquist bandwidth of the reference clock frequency. As shown in Section VI, a 6-bit ADC with an input LPF bandwidth in excess of 0.3/T is sufficient to achieve near ideal performance. A possible realization of a supply-sensing circuit for the proposed DPLL is the oscillator-based ADC shown in Fig. 4. A three-stage inverter ring oscillator is driven by the DPLL DCO supply voltage. The ring oscillator continuously clocks a counter, the output of which is sampled by a retimed reference clock operating at 1/T. The increment from the previous count, which can be realized by a two-tap difference filter, represents the DCO supply voltage. Advantages: Fig. 4. Simplified block diagram of an oscillator-based supply-sensing ADC. Reduce the noise and jitter Software implementation: Modelsim Xilinx ISE