CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC

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1 138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit may produce a square wave or any complex signal based on the need of the hour. It usually consists of a resonant circuit which may be the piezoelectric crystal and an amplifier. The amplifier is used to amplify the signals from the oscillator and to give feedback to the oscillator for further operation. It finds its place in personal computers, where microprocessors are used and also in clocked circuits like counters in display units etc. A PLL can be used as a clock generator in microprocessors. Here, the clock frequency required is given as the input reference signal and once the PLL is made to lock with this frequency, even with a change in the reference signal due to distortions, it will automatically detect the changes and obtain an output that will always be equal to the needed clock frequency. So, this type of clock generator is gaining popularity in the areas where there can be any changes in the reference signal due to external conditions. A part of this research aims to implement the PLLs for the high speed clock generation in SoC processors. It also aims to implement a PLL as a clock generator for providing multi-phase clock signals in Analog to Digital Converters (ADC).

2 139 The ADC requires a clock generator whose clock output should have a jitter less than 1ps. A clock generator circuit for an ADC is developed using PLL architecture with the specification given in Table 6.1. To meet out the above constraint a phase locked loop is designed with the components mentioned below: (1) Precharge type phase detector (2) A charge pump (3) Single pole loop filter (4) Thirteen inverter stage based ring oscillator Table 6.1 Specifications of PLL based Clock generator circuit Parameters Values V DD (volt) 1.8 I D (ma) < 200 Frequency (MHz) 100 Clock period(ns) 10 Jitter < 1ps 6.2 THIRTEEN INVERTER STAGES BASED VCO VCO produces an output signal with an angular frequency that is controlled by the input control voltage given to it. The output angular frequency of the VCO is given below: out = o + K vco V c where o is the VCO center frequency, K vco is the conversion gain of the VCO and VCO is the input control voltage of the VCO.

3 140 The output phase is equal to the integral over the frequency variation which is expressed as: out (t) = out (t) dt = K VCO V C (t) dt Types of VCO There are different types of VCO, which are mentioned below LC Oscillator Relaxation Oscillator Crystal Oscillator Ring Oscillator. Of these, the present design focuses on a ring oscillator. Due to the complexity involved and the large area occupied by the oscillators, they are not used (Chang-Hyeon Lee et al 1998) Ring Oscillator The ring oscillator consists of a series of inverting amplifiers placed in a feedback loop. It is composed of an odd number of inverters as shown in Figure 6.1. It can be seen that the last output of a chain of an odd number of inverters is the logical NOT of the first input. This final output is asserted a finite amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation.

4 V out Figure 6.1 Schematic of ring oscillator with inverter stages This circuit is a form of negative feedback, but since each inverter has approximately a 90 degree phase shift at its unity gain frequency, it is assured that the loop gain will be still greater than unity when the phase shift around the loop becomes greater than 180 degree. As a result, the circuit is unstable and oscillations occur. At each half period the signal will propagate around the loop with an inversion. Assuming the output of first inverter change to be 1, this change will propagate through all n inverters in a time T/2, at which the output of first inverter changes to 0; after an additional time of T/2, the first inverter s output will change back to 1 and so on. Assuming each inverter has a delay of t inv and that there are n inverters, then T n * tinv 2 1 inv. T Thus the frequency of operation, f 2*n * t In a physical device with MOSFETS, the gate capacitance must be charged before the current can flow between the source and the drain. Thus, the output of every inverter changes a finite amount of time after the input has changed. From here, it can be easily seen that adding more inverters to the chain increases the total gate delay, reducing the frequency of oscillation.

5 Mechanism for controlling the delay By making the delay of the inverters to control the voltage, the ring oscillator s frequency can be made voltage controlled. This is achieved by replacing the standard inverter by a current starved inverter. The mechanism for controlling the delay of each inverter is to limit the current available to discharge the load capacitance of the gate. The maximum discharge current of the inverter is limited by adding an NMOS transistor in series. This transistor is controlled by a voltage which determines the available discharge current. Lowering the control voltage reduces the discharge current and hence increases the high to low transition time. The VCO circuit used in this design is the current starved inverter circuit. The VCO circuit consists of an odd number of inverters which equal around thirteen inverter stages. MOSFETs M 2 and M 3 operate as an inverter, while MOSFETs M 1 and M 4 operate as current sources. The current sources M 1 and M 4 limit the current available to the inverters M 2 and M 3 ; in other words, the inverter is starved of current. The drain currents of MOSFETs M 5 and M 7 are the same and are set by the input control voltage. The currents in M 5 and M 7 are mirrored in each inverter/current source stage. The filter configurations used rely on the facts that the input capacitance of the VCO is practically infinite and the input capacitance is small compared to the capacitances present in the loop filter. Attaining infinite resistance is usually an easy part of the design. For the charge-pump configuration, the input capacitance of the VCO can be added to C 2. The voltage controlled oscillator implemented using inverters is shown in Figure 6.2.

6 143 Figure 6.2 Circuit diagram of voltage controlled oscillator 6.3 PRECHARGE TYPE PHASE DETECTOR The other important block which forms the first part of the phaselocked loop architecture is the phase detector. This compares the phase of the local oscillator to that of the reference signal. On comparison, the detector produces an output signal that is proportional to the phase error between the two signals. A precharge type phase detector is used in this design. Initially the reset is low, so the transistor M 1 and M 2 will be ON precharging the node A to V DD. Transistor M 3 will be OFF at that time. The transistor M 4 and M 5 will be OFF and M 7 will be ON. When VCO clock arrives (assume VCO is faster than reference) transistor M 2 will be OFF and M 5 will be ON and thus up inverter will go low. When reference clock becomes high, down inverter will go low and reset will go high and thereby resetting the output. Thus this precharge type phase detector will produce pulses whose width is proportional to the phase difference between the two clock signals. NOR gate has been

7 144 used here to reduce the width of the reset pulse which will reduce the jitter in the output of the PLL. The circuit diagram of the precharge type phase detector is shown in Figure 6.3. Figure 6.3 Circuit diagram of Precharge type phase detector 6.4 CHARGE PUMP The function of the charge pump shown in Figure 6.4 is the conversion of the current into the voltage so that the dc voltage can be given to the VCO and that can be made to lock with the input reference signal. A charge pump is an electronic circuit that uses capacitors as energy storage elements to create either a higher or lower voltage source (Boerstler 1999).

8 145 Figure 6.4 Schematic of a typical charge pump Charge pump circuits are capable of high efficiencies, sometimes as high as 90-95% while being electrically simple circuits. Charge pumps use some form of switching device(s) to control the connection of voltages to the capacitor. For instance, to generate a higher voltage, the first stage involves the capacitor being connected across a voltage and charged up. In the second stage, the capacitor is disconnected from the original charging voltage and reconnected with its negative terminal to the original positive charging voltage. The charge pump has two current elements and two switches connected to them. The current elements act as a current source or a current sink. The outputs from the phase detector are given to the two switches of the charge pump. When the switch 1 is in the ON state, the capacitance connected will be charged to the value of V DD. While the switch 2 is in the ON state, the capacitance connected will be discharged to the value of ground (Gnd). So when the output 1(reference) from the phase detector is high then the capacitance will be charged to V DD and it will take approximately 700ns to charge to V DD. But during this process, the value of the second output from the phase detector which is related to the VCO is high

9 146 and this turns the second switch to the ON position. Hence the capacitance starts discharging to Gnd. Thus the output will be combination of the charging and the discharging plot. Finally, when the two output values of the phase detector are identical then the voltage in the capacitor is maintained and hence the PLL is said to be in the state of lock which is the desired operation of the PLL. In the model graph shown in Figure 6.5, Q B is the reset pulse which takes the value of 1 whenever the VCO output turns higher. The circuit operates in three states. If Q A = Q B = 0, then S 1 and S 2 will be in the OFF state and V out remains constant. If Q A is high and Q B is low then I 1 charges the capacitance C p and in the reverse case when Q A is low and Q B is high then I 2 discharges the capacitance C p. Thus if, for example, A leads B, Q A continues to produce pulses and V out rises steadily. Under a lock condition, the charge currents I 1 and I 2 called UP and DOWN currents nominally will be equal. The circuit diagram of charge pump is shown in Figure 6.6. Figure 6.5 Model graph showing charge pump output

10 147 Figure 6.6 Circuit diagram of the implemented charge pump 6.5 SECOND ORDER LOOP FILTER The second block of PLL is a loop filter. The loop filter filters the output of the phase detector to produce the VCO control voltage. The loop filter can be either an active or a passive filter. This design focuses on the passive second order loop filter shown in Figure 6.7. V in Vout C 1 C 2 R Figure 6.7 Second order passive loop filter The time constant of the filter is equal to RC. The break frequency (turnover frequency or cutoff frequency) is determined using the time constant as follows.

11 148 f c 1 2* * R *C In addition of LPF affects the loop response including parameters such as loop time response, loop bandwidth and damping factor of loop. One disadvantage of using a single pole filter is that both the closed loop bandwidth and the damping factor of the closed loop response of the PLL depend on the loop bandwidth. The loop bandwidth cannot be set without affecting the amount of transient overshoot. The following values of the R and C components given below are used in the filter design: R1 = 33 K C1 = 500f F C2 = 500f F 6.6 JITTER The difference between the ideal and actual sampling instants in a clock signal is shown in Figure 6.8. The jitter in the clock used in ADC can be indicated as a sampling time uncertainty which will affect the Effective Number of Bits (ENOB) of ADC as shown in Figure 6.9. The Signal to Noise Distortion Ratio (SNDR) and the ENOB are determined using the following equations: SNDR 1 10.log 2 f aperture 2 SNDR aperture 1.76 ENOB 6.02 in t

12 149 Signal V IN ΔV IN Change in V IN during τ 1 t τ 1 =Sampling time uncertainty Ideal sampling instant t+δt Actual sampling instant (Worst Case) Figure 6.8 Clock signal analysis diagram Effective Number Of Bits (ENOB) Effective Number of Bits (ENOB) MHz 1 MHz 20MHz 50MHz 100MHz Sampling time uncertainty (ps) Figure 6.9 ENOB as a function of sampling time uncertainty As mentioned above, for the proper operation of ADC the jitter should be less than 1ps. The components of PLL are chosen in such a way that the jitter incurred will be less than 1ps.

13 SIMULATION RESULTS The components opted for the design of PLL architecture for ADC are implemented and simulated using CADENCE analog design environment. Its operating characteristics are verified using 0.18 µm CMOS technology and it works for its designed features at all process corners. The precharge phase detector output obtained from the design is shown in Figure The output of the phase detector is taken as inputs in charge pump and it gives out a control voltage shown in Figure 6.11 which is used to drive the VCO for generating a clock signal with the same phase and frequency as that of the input. Figure 6.10 Output waveform of phase detector

14 151 Figure 6.11 Output waveform of charge pump Prior to being fed to the VCO, the control voltage is fed to the loop filter to filter out the noise contents in the error signal generated by phase detector. The output of the filter shown in Figure 6.12 is used to control the VCO. With respect to the control voltage fed to the VCO, a signal with a particular frequency and phase is generated which is shown in Figure Figure 6.12 Control voltage from loop filter

15 152 Figure 6.13 Control voltage with its associated VCO output The jitter is measured using the eye diagram. Once the PLL gets locked, the eye diagram is plotted by overlapping the output waveform as shown in Figures 6.14 and Figure 6.14 Eye diagram-i for jitter measurement

16 153 Figure 6.15 Eye diagram-ii for jitter measurement The physical design for the PLL architecture is done and the layout shown in Figure 6.16 is drawn considering the design rules. Figure 6.16 Layout of the PLL architecture for ADC

17 CONCLUDING REMARKS The PLL architecture modelled with the above discussed components works for its features. The jitter in this output is measured using the eye diagram approach as shown in Figures 6.14 and It is available in the CADENCE tool. The range for which the PLL will be locked is from 95MHz-145MHz where the center frequency is 100MHz. For frequency outside this range the PLL will not be locked. The integrated PLL architecture yields a jitter around 700 fs (is less than 1ps, as per the specification). It is verified for its operating characteristics at all process corners (Typical-Typical (TT), Fast-Fast (FF), Slow-Slow (SS)). An optimized layout is drawn for the PLL architecture. This clearly endorses that the designed PLL architecture can be used as clock generator in ADCs. The values obtained for various parameters are tabulated in Table 6.2. Table 6.2 Design summary of PLL for ADC Parameters Values V dd (volt) 1.8 I d (ma) < 200 Frequency (MHz) 100 Clock period(ns) 10 Jitter < 700fs Temperature Range -55ºC to 120ºC Working Corners TT, FF, SS