Case5:08-cv PSG Document Filed09/17/13 Page1 of 11 EXHIBIT

Transcription

1 Case5:08-cv PSG Document Filed09/17/13 Page1 of 11 EXHIBIT N

2 ISSCC 2004 Case5:08-cv PSG / SESSION 26 / OPTICAL AND Document FAST I/O / Filed09/17/13 Page2 of A PVT Tolerant 0.18MHz to 600MHz Self-Calibrated Digital PLL in 90nm CMOS Process Jerry (Heng-Chih) Lin, Baher Haroun, Tim Foo, Jin-Sheng Wang, Bob Helmick, Scott Randall, Terry Mayhugh, Chris Barr, Jeff Kirkpatrick Texas Instruments, Dallas, TX This DPLL is very flexible and meets tight clock jitter requirements for most wireless baseband circuits. It has wide reference frequency (0.03M-65MHz) and output frequency (0.18M-600MHz) with near constant damping factor and loop bandwidth to reference frequency ratio, independent of the reference frequency, the divider ratio, and the PVT variations (voltage of V, with 1.2V typical, and temperature -40 to 125 O C). The low jitter and wide operation range are achieved through (1) a logarithmic time digitizer (T2D), (2) a start-up auto-calibration and normalization algorithm, (3) a novel digitally controlled oscillator (DCO) with low voltage operation and high PSRR. Fabricated in 90nm CMOS, the p-p jitter is < 4% of the output clock. The power is 1.7mW at 1V and 520MHz output. The process scalability, flexibility, performance, and power/voltage of this DPLL compare favorably with state of the art analog PLL [1]. Figure is the block diagram of this DPLL. The input clock divides into the REFCLK. PFD and T2D blocks compare the feedback clock (FBCLK) and REFCLK to generate the signed, logarithmically compressed 6b digital representation of the phase error in terms of the number of inverter delays. Digital controller then linearizes the 6b phase error through a Look-Up- Table (LUT), and calculates the required DCO code with the digital filter, normalization block, and accumulator. The DCO frequency vs. code transfer function is almost linear. The wide output frequency (>3000x) is achieved through the smart L divider, with the ratio determined during the start-up calibration phase by setting the DCO at a pre-determined code and comparing the frequency difference between the divide by M clock and REFCLK. Two output clocks are provided. One is the high speed clock; the other is the divide-by-2 version with a better duty cycle. The output clock is divided by M to be the FBCLK, closing the loop. The user can select REFCLK from 0.03MHz to 65MHz, and the feedback divider M from 1 to Loop bandwidth and damping factor are critical design issues for this wide dynamic range DPLL. It does not have a REFCLK frequency range indicator and the loop transfer function is affected by the variability of individual blocks (over PVT, T2D has >4x delay variation and DCO >3x frequency variation). Hence, to maintain the constant loop bandwidth to REFCLK frequency ratio and constant damping factor, this DPLL performs a startup calibration and normalization by calibrating the DCO period with respect to the T2D delay. This is done by setting the DCO at a pre-determined code, forwarding it to the T2D, and counting the equivalent number of inverter delays within one DCO period (count). It is shown that if (1) the DCO frequency vs. code transfer function is linear (the slope can vary over PVT), (2) the x-axis intercept points of DCO transfer function are the same (-X) across PVT, then, with a normalization factor which is a function of the DCO_Code, X, count, M, and L, the constant damping factor and loop bandwidth vs. reference frequency ratio is attained regardless of the REFCLK frequency, divider ratio, and PVT conditions. Even if the two DCO assumptions are not accurate, this method is still valid to the first order and can be modified for calibration using two or more points at the cost of design complexity. Since the loop filter operates in the digital domain which scales with REFCLK, by calibrating two analog blocks, DCO & T2D, with each other and knowing the value of the L the entire loop is expressed as a REFCLK frequency independent Z domain transfer function with fixed coefficients. A consistent loop performance for wide range of operation is thus achieved. The wide input frequency range is achieved through the logarithmically compressed time measurement (T2D) block and a linearization LUT in the digital domain. As shown in Fig , the phase error (PE) pulse width is converted to 6b PE code through the self-terminating exponentially increased delay chain. This compressed PE code is linearized by the LUT. The combination of logarithmic T2D and LUT significantly increases the reference frequency range with very little area and power penalty. Although quantization error increases with the delay chain, it does not affect the output jitter percentage. With a lower REFCLK frequency (longer period), more delay chain elements get exercised, which increases the absolute PE and quantization error. However, the PE or quantization error expressed as a percentage of the REFCLK period remains the same. Figure shows the DCO schematic with one 10b DAC directly stacked on top of a 3-stage current-controlled ring oscillator. The delay element uses a concept similar to [2] with current dependent negative resistance (or delay). 10b (9b thermometer + 1b binary) segmented current steering DAC is used to ensure the monotonicity and to reduce the glitch energy. Memory-like layout architecture with a row/column decoder is used to reduce the number of control lines. This simplifies the routing and reduces the coupling to the current output. Each current element is constructed with a wide-swing cascode current source and with switches controlled by the appropriate combination of row/column decoder outputs. By using a triangular column decoder output and different odd and even row controls, large current glitches are avoided when DPLL locks at row boundaries. The oscillator is separated from the supply by the DAC output impedance thus good PSRR (typical 1% frequency changes with 5% supply changes) is achieved. Figure is the histogram of the measured 260MHz(65MHz x 4) and 30.7MHz(0.03MHz x 1023) divide-by-2 output waveforms. The p-p jitters with ~100k hits are 140ps(3.6%) and 400ps(1.2%), respectively. Part of the jitter is caused by the single ended open drain output buffer so that the internal clock jitter should be better. Figure shows the Schmoo plot of the SoC chip with this DPLL driving the embedded logic core. The absolute range of supply for this chip is V. This DPLL has the same maximum voltage range and higher frequency range than the core which helps in the characterization in the extreme limits. Figure summarizes the chip performance. The power consumption varies with supply voltage, input and output frequency. The measured power is 1.7mW at 1V and a 520MHz output. Figure is the chip micrograph. The overall area is 0.18mm 2 with the digital controller occupying ~45% and the decoupling capacitor ~20% of the chip area. Acknowledgments: We thank Y. F. Tuan on chip layout; R. Gu, B. Staszewski, S. Goldman for discussion; C. Buchanan & P. Blanc on characterization. References: [1] J. Maneatis et al., Self-Biased High-Bandwidth Low Jitter 1-to-4096 Multiplier Clock-Generator PLL, ISSCC Dig. Tech. Papers, pp , Feb [2] B. Razavi, Design of Analog Integrated Circuits, p. 515, McGraw- Hill, 2001.

3 Case5:08-cv PSG Document ISSCC 2004 Filed09/17/13 / February 18, 2004 Page3 / Salon of 119 / 4:45 PM Figure : DPLL block diagram. Figure : Logarithmic time digitizer (T2D) and Look Up Table (LUT). Figure : Digitally controlled oscillator (DCO) schematic. Figure : Measured DPLL divided-by-2 output waveform and histogram. Figure : Measured working region Schmoo plot with DPLL and logic core. Figure : Performance summary.

4 Case5:08-cv PSG Document Filed09/17/13 Page4 of 11 Figure : Chip micrograph.

5 Case5:08-cv PSG Document Filed09/17/13 Page5 of 11 Figure : DPLL block diagram.

6 Case5:08-cv PSG Document Filed09/17/13 Page6 of 11 Figure : Logarithmic time digitizer (T2D) and Look Up Table (LUT).

7 Case5:08-cv PSG Document Filed09/17/13 Page7 of 11 Figure : Digitally controlled oscillator (DCO) schematic.

8 Case5:08-cv PSG Document Filed09/17/13 Page8 of 11 Figure : Measured DPLL divided-by-2 output waveform and histogram.

9 Case5:08-cv PSG Document Filed09/17/13 Page9 of 11 Figure : Measured working region Schmoo plot with DPLL and logic core.

10 Case5:08-cv PSG Document Filed09/17/13 Page10 of 11 Figure : Performance summary.

11 Case5:08-cv PSG Document Filed09/17/13 Page11 of 11 Figure : Chip micrograph.