Dedication. To Mum and Dad

Transcription

1

2

3

4 Dedication To Mum and Dad

5 Acknowledgment

6 Table of Contents

7

8

9 List of Tables

10 List of Figures

11 A B A B 0 1 B A

12

13

14

15 List of Abbreviations

16 Abstract

17

18 Chapter1 1 Introduction 1.1. Motivation Figure 1. 1 The relative delay of the transistor, local, and global interconnect wires plotted versus process technology [1]

19 Figure 1. 2 Moore's gap; gap between the performance and the number of transistors

20 1.2. System in Package (SiP) Figure D ICs multilayer connected TSV [7]

21 1.3. Parallel vs. Serial On-Chip Communication Driver Repeaters Buffers Core1 Core2 Figure 1. 4 Parallel based communication

22 1.4. Thesis Organization

23 Chapter 2 2 On-Chip SerDes Transceiver Architectures and Signaling Schemes 2.1. Introduction Driver TX Line Buffer Core1 Serializer Deserializer Core2 Figure 2. 1 Main functional blocks of SerDes transceiver; it consists of Serializer, driver at the transmitter and buffer, deserializer at the receiver

24 2.2. Signaling Schemes scheme VDD scheme 2,DC 0 VDD/2VDD VDD/2 1 VDDVDD/2 VDD/2scheme 3 0 VDD/2 1 VDDVDD/2

25 CLK Data Encoded data Encoded data_bar Figure 2. 2 Scheme 1: conventional two-level signaling scheme CLK Data Encoded data Encoded data_ bar Figure 2. 3 Scheme 2: three-level DC preserving signaling scheme CLK Data Encoded data 2.3. Transmission Line Figure 2. 4 Scheme 3: three-level signaling scheme RC RLC RLC

26 RLC R LC Z 0 Z S Z L Figure 2. 5 Transmission line equivalent Z 0 = 1 + R L C tz (, ) = {(, ) } = 1 + = +

27 =, = 2 v = 1 VDD ws RLCZ 0 ws ws Figure 2. 6 Cross section of single ended transmission line Figure 2. 7 Cross section of differential ended transmission line

28 RC Transmission Line Matching Techniques Source Matching Technique ZsZ 0

29 DC DC Resistive Termination Technique l = = + R L R L DCAC

30 = + DC 2.4. Proposed SerDes Transceiver Architectures Scheme 1: Conventional Two-Level Code 6-8 Encoder Serializer Detector Deserializer 8-6 Decoder ADPLL (7GHz) Transmitter Receiver CDR (7GHz) Figure 2. 8 SerDes transceiver architecture scheme1

31 Encoder and Decoder 6 bits parallel data in 8 bits parallel data out Figure 2. 9 Proposed 6-8 encoder

32 Serializer Figure Conventional shift-register type Serializer [15]

33 DETFF: Double Edge Trigger Flip Flop FF: Flip Flop L: Latch M: MUX Figure Serializer block diagram Deserializer FF: Flip Flop L: Latch Figure Deserializer block diagram

34 Figure Deserializer waveforms

35 Clock and Data Recovery (CDR) Figure Eye diagram of the data, the Y-axis is the voltage and the X-axis is the time frequency lock

36 F ref Data F DCO Frequency Loop Phase Loop frequency lock FL UP/DN MUX PL UP/DN VCO F DCO Figure Conventional charge pump based CDR

37 All Digital CDR Proposed Architecture frequency lock Data Bang-Bang PD Deserializer UP,DN UP[7:0] DN[7:0] FSM + fraction3 / 1 st Order Fine tune / 4 Fine tune / 1 DCO Fref Frequency Acquisition Binary Search Frequency Lock Z -1 Coarse tune integer Fine tune Thermometer / 5 Encoder 24 / / 4 Thermometer Encoder 15 / Figure Proposed CDR block diagram

38 UPDN UP/DN

39 Bang-Bang Phase Detector Figure Linear Phase Detector: Schematic and Transfer function [18] Figure Bang-Bang Phase Detector: Schematic and Transfer function [18]

40 S0 S1,S2 UPS1 S0DN S1S2 UP DN UPDN UPDN Figure Proposed half-rate BBPD In-phase clock Quadrature clock Clock leading Data Clock lagging Data Figure Data sampled by the clock at 3 states Table 2.1 Different states of clock and data are indicated by UP and DN signals UP DN State

41 Digital Controlled Oscillator (DCO) Figure DCO Figure DCO tuning curves

42 Scheme 2: Three-Level code with Constant DC DC V DD /2 Transmitter Ro Ro Differential Transmission Line Receiver Figure SerDes transceiver architecture for 3 level signaling preserving the DC level in scheme 2

43 Three-level Encoder and Driver VDD/2 VDD/2 VDD/2 FF: Flip Flop L: Latch M: MUX FF L Data XOR CLK M FF Driver FF L M FF Figure Scheme 2: Three-level Encoder and driver

44 Z s Z 0 Figure The encoder internal signals and the transmission line input/output signals Transmission Line Design Z s Z 0 Z s Z 0

45 C H =54f C V =254f L=1.7 n R=40 Figure Scheme 2, source matching technique is used Figure cross section of differential transmission line and design parameters of scheme 2 RLC V C H CC v C H Z 0 v (1-e - ) (1-2e - )

46 Table 2.2 Design parameters of scheme 3 transmission line Parameter Symbol Value R L C sat Z 0 v t p Decoder 0 AB 1 A in Low Switching Threshold A in V th in_bar V th in_bar B A B Figure Low switching threshold inverters convert the three-level signals to two-level signal A and B Figure A and B are the output signals of the low switching threshold inverters; 0 represented by a pulse on A followed by a pulse on B, while 1 represented by a pulse on B followed by a pulse on A.

47 Phase Detector QAQB AQAB QBBA QAQB AB 0, BA Q Q Q Volt Q Time Figure Phase Detector Figure Simple Phase detector extract the clock and recover the data

48 Scheme 3: Three-Level Code Ro Transmitter Single-ended Transmission Line Receiver Figure Scheme 3 SerDes transceiver architecture for 3 level signaling

49 Driver and Three-level Encoder VDD/2 clk Data Encoded data clk clk V dd clk Figure Scheme 3: Three-level Encoder and driver Transmission Line Design Z o R L VDD/2

50 DC R LC V C H CC v C H C H =52.5fF C V =763.5fF L=1 nh R=18.2 Figure Scheme 3 transmission line termination resistance connected to VDD/2 source rather than ground Figure cross section of single ended transmission line Z 0 v R L

51 (mv) (mv) Figure Scheme 3, three-level code at the input and output of the transmission line Table 2.3 Design parameters of scheme 3 transmission line Parameter Symbol Value Detector AB

52 SR Latch Figure Scheme 3 simple detector Figure Detector at the receiver detects the 3 level code, extract the clock and recover the data 2.5. Calibration Technique Applied to Scheme 2 and Scheme 3

53 Figure Calibrated low switching threshold inverter Figure Calibrated high switching threshold inverter

54 2.6. A Comparison between the Three Discussed Signaling Schemes Point of comparison Scheme 1 (conventional scheme) Scheme 2 (proposed scheme) Scheme 3 (proposed scheme) Signaling scheme Transmission Line Matching technique Limitation on minimum frequency Bulky building blocks Jitter effect on data reliability Detector calibration Driver size Maximum frequency of operation (GHz) Maximum data rate (GHz) Power Design complexity Area

55 2.7. Simulation Results Scheme 2 Simulation Results (1-2e - )1-e - )=. Figure Eye diagram of the three-level code at the input of the transmission line Figure Eye diagram of the three-level code at the output of the transmission line Figure Eye diagram of the extracted clock from the phase detector Figure Eye diagram of the recovered data from the phase detector

56 Table 2. 4 Power Consumption of scheme 2 componnents in typical conditions prelayout Component Power (mw)

57 Scheme 3 Simulation Results Table 2. 5 Power Consumption of scheme 3 components in typical conditions Component Power (mw)

58 2.8. Layout Figure Serializer layout Figure Deserializer Layout

59 2.9. Design Comparison Table 2. 6 Design comparison of the proposed signaling techniques with other work in published literature This work Scheme 2 Scheme 3

60 3.1. Introduction Chapter 3 3 All Digital Phase Locked Loop V LPF = + V LPF F O V LPF K VCO

61 F ref V PD V LPF PD LPF VCO F out F div Divide by N Figure 3. 1 The conventional block diagram of PLL based frequency synthesizer = / = Acquisition Lock Time Acquisition Lock Range Jitter Phase noise

62 F Figure 3. 2 Jitter in time domain translated to phase noise in frequency domain Bandwidth Power Consumption Portability

63 3.2. Motivation for All Digital PLLs F ref PFD UP Dn I UP I DN Loop Filter V LF VCO F out F div Divide by N Figure 3. 3 Block diagram of charge pump based PLL

64 Analog PLL vs. Digital PLLs F ref V PD V LPF PD DLF DCO F out F div Divide by N Figure 3. 4 The block diagram of Digital PLL

65 Target Application Requirements Table 3.1 SerDes transceiver frequency synthesizer requirements Reference frequency (F ref ) Output frequency range Output frequency step Jitter Power & area

66 3.3. Bang-Bang ADPLL UP/DN UP/DN = F ref UP/DN BPD F div DLF D Prop bits Int bits 5 Z -1 4 DCO 1 Modulator 1 st order F out N Figure 3. 5 Block diagram of bang-bang ADPLL

67 Proposed BBADPLL Architecture frequency lock Frequency Acquisition Loop coarse bits_fl Frequency Locked Fine bits_fl5 1 4 F ref F div Phase Loop Fine bits_pl5 MUX 5 DCO F DCO N Figure 3. 6 Architecture of the proposed BBADPLL, it consists mainly of frequency acquisition loop and phase loop

68 BBADPLL Building Blocks N UP/DN UP/DN 5 D UP/DN Q 1 F div Frequency Detector Digital Loop Filter (DLF) coarse bits_fl Frequency Locked Fine bits_fl 5 Fine bits_pl 5 Fraction bits 4 1 MUX 4 5 Thermometer Encoder Modulator 1 st order coarse bits15 Fine bits Prop bits 3 bits 1 31 Digital Controlled Oscillator (DCO) F DCO N 5 Figure 3. 7 Detailed Block diagram of the proposed BBADPLL

69 Digital Controlled Oscillator (DCO)

70 Figure 3. 8 Block diagram of the proposed DCO Figure 3. 9 DCO cell schematic Figure Post-layout simulation results showing the output frequency curves for different coarse and fine words

71 = + + F out W Coarse W Fine K Coarse K Fine F o W Coarse 0W Fine 0 K Fine K fine Frequency Acquisition Loop NFAST/SLOW

72 FAST/SLOW F DCO Count Counter Enable RST D Q N + - FAST/SLOW Binary Search State Machine Coarse Bits Fine Bits Frequency Locked F ref Control Signals Generation Sample_count Figure Block diagram of the frequency detector Counter and Comparator

73 F ref Control Signals Generation Enable RST D D Q Q Enable_sync RST_sync F DCO Figure Frequency detector synchronizer used to resolve metastability, and reduce the period of undefined state Control Signals EnableRSTSample_Count EnableRST Enable 1 RST 0RST1 Enable Sample_Count F re

74 Table 3.2 Three states of the counter State Enable RST reset counting hold F ref Enable RST Counter status Count=0 Counting Hold Count=0 Counting Hold Sample_Count Comparator Count<N FAST/SLOW=1 Count>N FAST/SLOW=0 Figure Control signals of the counter; reset and enable signals, counter status and comparator output

75 Binary Search Finite State Machine F ref /3 S S1 S4S5 S9 Figure State machine of the binary search algorithm

76 Phase Loop Phase Detector UP/DN UP/DN 1 D Q Figure (a) Single flip flop act as binary phase detector (b) Output transfer function of BPD Frequency Divider N

77 D Q D Q D Q Figure Divide-by-five; frequency prescaler Sigma Delta Modulator N: integer fine bits Figure DCO dithering by changing the fine bits at high rate

78 = + ( + 1) + = + + NT N NT N+1 N+1 F DCO X n CarryCarry_bit 0100 carry Z -1 Figure Block diagram of modulator, it consists of adder and D-FFs

79 ¼ Table 3.3 Example illustrates the operation of 1st order modulatorwith fractional bits =0100=1/4 n X n X n-1 carry/ _bit Table 3.4 Example illustrates the operation of 1st order modulatorwith fractional bits =0110=3/8 n X n X n-1 carry/ _bit F DCO Digital Loop Filter (DLF)

80 F DIV F ref D DLF Z -1 Figure Block diagram of the digital loop filter UP/DN UP/DN DD

81 D D D Proposed BBADPLL Model ref UP/DN div X prop X int r W fine Z -1 Figure BBADPLL Model t () = + () o

82 = 1 () N () = 1 () ( ) X prop X int 0 / = 0 = 1 / = 1 1 / = 0 = 1 / = 1 X prop X int TsF ref F ref () = () (1 ) () = + 1 r

83 () () = 2 () () () = 2. (1 ) + (1 ) [] = 2 ( [] [ 1]) + [] [ 2] + 2 [ 1] [] = [] [ 1] K fine K fine

84 Figure phase error transient response for coarse word=1 Figure jitter Figure Figure 3. 24

85 K fine K fine = D Figure The effect of changing (a) =0.25, (b) =1, (c) =2 D

86 D,DK Fine,D 3.4. Simulation Results

87 DCO Frequency Curves and The Equivalent Power Consumption TT, 1V, 125c SS, 0.9V, 125c FF, 1.1V, 0c Figure DCO output frequency curves and power consumption for different coarse and fine words across PVT

88 ADPLL Closed Loop Simulation Results s Figure Closed loop post layout simulations for BBADPLL,D Table 3. 5 The closed loop simulation results at 7.5 and 10GHz

89 3.5. Layout Full Custom Blocks Floor Plan DCO PMOS control bits Transistors Frequency Prescaler Divide by 5 Clock Buffer DCO 3 stages Ring oscillator inverter based DCO NMOS Control bits transistors Figure ADPLL Floorplan

90 DCO, Buffer and Prescaler Layout Figure DCO and divide-by-five full custom layout

91 Digital Blocks Floor Plan Figure ADPLL digital blocks floor plan snapshot from SoC encounter

92 Layout Figure ADPLL digital blocks Layout

93 3.6. Design Comparison Table 3. 6 Design comparison of the proposed BBADPLL with other work in published literature This Work

94 4.1. Summary Chapter 4 4 Summary and Future Work

95 DC

96 VDD/2

97 4.2. Conclusion 4.3. Future Work

98

99 References International Conference in Computer Aided Design ICCAD Custom Integrated Circuits Conference (CICC), International Symposium on Circuits and Systems (ISCAS) EE Times, design article Design Automation Conference (DAC) IBM J. Res. & Dev Design Automation Conference (DAC) Proceedings of the IEEE

100 Custom Integrated Circuits Conference(CICC) et al. IEEE International Solid-State Circuits Conference (ISSCC) Proceeding of the 30th European Solid-State Circuits Conference (ESSCIRC) Custom Intergrated Circuits Conference (CICC) Digest of Technical Papers Symposium onvlsi Circuits, 2005 IEEE Custom Intergrated Circuits Conference (CICC) IEEEJournal of Solid State Circuits

101 IEEE Journal of Solid State Circuits IEEE Custom Intergrated Circuits Conference (CICC) Design Automation Conference (DAC), IEEE International of Solid-State Circuits Conference (ISSCC), Electronic Letters IEEE International Conference on Industrial Technology (ICIT) IEEE Journal of Solid-State Circuits

102 IEEE Journal of Solid-State Circuits IEEE Transactions on Circuits and Systems II IEEE Trans. on Communications International Conference on Electric Information and Control Engineering (ICEICE) 7th International Conference on ASIC IEEE Journal ofsolid-state Circuits

103 ,, IEEE Trans. on circuits and systems, IEEE Trans. on circuits and systems, IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Phase-Locking in High Performance Systems IEEE Asia Pacific Conference on circuits and systems IEEE International Symposium on Circuits and Systems

104 IEEE J. Solid- State Circuits IEEE Trans. on circuits and systems IEEE Trans. Circuits Syst. II Proceedings of the IEEE Custom Integrated Circuits Conference 2003 IEEE Transactions oncircuits and Systems II: Express Briefs IEEE J. Solid-State Circuits IEEE International Solid-State Circuits Conference (ISSCC)

105 IEEE International Solid-State Circuits Conference (ISSCC) IEEE International Solid-State Circuits Conference (ISSCC)