Chapter 2 Signal Conditioning, Propagation, and Conversion

Transcription

1 09/0 PHY 4330 Instrumentation I Chapter Signal Conditioning, Propagation, and Conversion. Amplification (Review of Op-amps) Reference: D. A. Bell, Operational Amplifiers Applications, Troubleshooting, and Design, Prentice Hall, Operational Amplifier (Op Amp) Terminology R out V a R in V out A(s)V a Fig. - Equivalent circuit of an op-amp. (a) Voltage gain ( 增益 ) A(s) is essentially constant over a certain frequency range, where s is the complex frequency. (i.e. s = j, j = ) (b) Upper frequency -- above which the gain begins to decrease appreciably. (c) Lower frequency -- below which the gain begins to decrease appreciably. The cutoff frequency (either upper or lower) is defined to be 3dB (i.e. gain is down to mid-frequency value) of its (d) Bandwidth ( 帶寬 ) -- the difference between the upper and lower cutoff frequencies. (e) Input (output) impedance ( 阻抗 ) -- the equivalent impedance seen by looking into the input (output) terminals. (f) Gain-bandwidth product -- the frequency where the open-loop voltage gain of the op amp is unity. Typical value is MHz. Remark: Characteristics of an ideal op-amp: Input impedance R in = Output impedance R out = 0 Voltage gain = Bandwidth =.

2 Table. Important parameters of selected op-amps. Next time add input impedance Type Supply voltage Max. power Open loop voltage Slew rate (V/ s) range (V) dissipation (mw) gain (db) LM348 0 to L65 6 to S 5 to LF356 Power supply: 0 V input impedance = 0 ; CMMR 00 db; voltage gain x0 8 ; slew rate 50 V/ s. OFFSET NULL 8 nc INV INPUT 7 V NON-INV INPUT 3 6 OUTPUT V 4 5 OFFSET NULL Fig. -B Pin assignment of op amp 74 and its nulling circuit. TOP VIEW NULL K V.. Single Pole Model of an Amplifier For the high-frequency region, an amplifier can be approximated by a simple low-pass circuit: R V o (s) V i (s) C Fig. - A simple low-pass circuit. gain sc So, V o(s) = V ( s) = V ( s) i i = A H(s)V i(s). sr C R sc It is called a single pole model since for s =, A H(s) has a pole, i.e. V o. R C

3 Putting s = j and c = R C A H( ) = c A H( ) = = j R C j c At the upper cut off frequency c, A H( c) =. Similarly, for the low-frequency region, an amplifier can be modeled by a high-pass RC circuit: V i (s) C c = R V o (s) R C Lower cut off frequency Fig. -3 A high-pass filter. Students are encouraged to work out the gain as a function of...3 Basic Op amp Circuits A. Inverting Input B. Non-inverting Input I I R R V o V x ~V i V i 3

4 ..4 Impedance Matching ( 匹配 ) Consider r = internal resistance of battery R L = load resistance r I R L We see that the circuit is best if R L = r. Most transducers have very high internal resistance, whereas most loads have relatively small resistance. So, we should use an op amp to match their impedances. Note: most transducers generate very small current or charge; that is why one needs an opamp with very high input impedance. R out r T R in R load r T = Internal resistance of transducer 4

5 . Adders and D/A (Digital to Analog) Converters.. Adder (Summing Amplifier) Fig. -8 An adder... Digital-to-Analog Converter (A) Weighted resistor type (WRDA) R V in n R 4R R V out Fig. -9 WRDA. (B) Resistor Ladder type 3R Node N- Node N- Node N-3 Node 0 R R R R R R R R R Vo LSB MSB 3 MSB MSB MSB - second most significant bit MSB 3 - third most significant bit V ref Fig. -0 D/A converter using R, R ladder. 5

6 (C) Weighted resistor type D/A (WRDA) versus resistor ladder type D/A (RLDA) In practice the number of bits (or resolution) is usually. Some high-end D/A converters offer 6-bit resolution or more. Typical resolution of a digital oscilloscope is 8-bit. (i) WRDA (assuming -bit resolution) If R = 0 4, the LSB would be x0 4 = 40.9 M The values of the resistors vary over a wide range. Several types of resistors (i.e. made of different materials) are likely to be needed to cover such a wide range. The obvious disadvantage is that the accuracy and stability would depend on the absolute accuracy of the resistors that are temperature dependent. The accuracy of different types of resistors may have different temperature dependence, and the accuracy of the D/A converter would be temperature dependent. The conversion rate is slow due to the high input impedance. (ii) RLDA One can use any convenient value for R between 5 k and 50 k ). Easily fabricated by thin film deposition techniques. The resistance of each resistor has almost the same temperature dependence. So, the net result, given by the ratios of the resistors, is almost independent of temperature. Conversion rate is faster because input resistance can be kept small...3 D/A Converter Terminology Resolution ( 分辨率 ) -- Maximum number of input bits that the converter is capable of handling. Example: -bit resolution = 4096 levels. Linearity -- Maximum deviation from the best straight line drawn through the staircase output waveform as shown in Fig. -, which is a result of incrementing the DAC sequentially through all its successive states. The maximum allowable deviation from the best straight line is ideally less than (/)LSB. Fig. - Linearity of a D/A output. 6

7 Offset ( 偏移量 ) -- Output of a DAC when the appropriate code for zero output (e.g in binary) is applied to the input. It is specified as a fraction of the LSB. An external control for adjusting the offset is usually available for most DACs. Settling time--time required for all transients to be sufficiently reduced while the output lies within some specified amount of its final value (Fig. -3). Determined by the types of switches, resistors, and amplifiers used. / LSB Fig. -3 Settling time of a DAC. Stability -- A measure of how stable the output is when the environmental conditions or the power supply voltage are changed. Determined by the reference voltage and the temperature stability of its active and passive components...4 Comparator and Integrator (A) Comparator Time V o (B) Integrator - 7

8 ..5 Analog to Digital (A/D) Converters Five types of A/D converters will be described: () Successive approximation () Single and dual-slope integration (3) Voltage comparator-counter loop (4) Multiple comparator type (5) Voltage-to-frequency conversion. () Successive approximation Shown in Fig. -4. A Start conversion pulse clears the output register and turns ON (logic ) its MSB so that the DAC gives half of a full-scale deflection, say 5 V for 0 V full-scale deflection. V out Start conversion MSB LSB Status MSB LSB Analogue reference Control logic Analogue input V in Fig. -4 An A/D converter based on successive approximation. This output is compared with the analog input V in, and if the latter is < 5 V, the comparator turns OFF (logic 0) the MSB of the output register via the control unit. If the analog input V in > 5 V, the MSB of output register is left ON. The next clock pulse turns ON the next significant bit of the output register via the shift register and its contribution of.5 V adds to the MSB bit if it is left ON. The comparator tests whether V in greater or less than the new total output of the output register V out. If V in > V out, comparator leaves the bit ON, If V in < V out, the bit is turned OFF. Process repeated n times for a n-bit converter, until the LSB has been compared. The clock then stops, to be restarted only by the next comparison pulse. The Status line changes state to indicate that V out is now a valid conversion. The accuracy, linearity, and speed of such a converter are determined by the properties of its DAC, its reference and the comparator. The settling time of the DAC and the response time of the comparator are considerably longer than the switching time of the digital elements. 8

9 This type of A/D converters is widely used for computer interfacing. In fact, the one that you will use in Experiment 4 makes use of successive approximation. The resolution could reach 6-bit. () Single and Dual Slope Integration Fig. -5 shows a single slope integration type A/D converter. The integrator and the counter initially reset via the logic control unit that initiates the integrator and counter simultaneously. The integrator generates a ramp while the counter is incremented, one LSB at a time, by the fixed frequency clock. When the ramp reaches a level equals to that of the input analog signal (V in), the comparator changes state and stops the counter. The content of the counter is then digital representation of V in (indicated by the state of the status terminal.) Fig. -5 A single-slope integration type A/D converter. R - C Clock Reset and start conversion V ref Integrator Analogue Input V in Comparator Logic Control unit Status Counter MSB LSB Disadvantages: Digital Output (i) Slow, because of large time constant involved, (ii) Resetting not very accurate, (iii) Linearity of ramp usually not good, (iv) Clock frequency likely to vary with temperature. 9

10 Improved Version (Dual Slope Integration) Some disadvantages of the single slope integration can be overcome by a dual-slope integration type A/D converter shown in Fig. -6. V in C - Intergrator Comparator V ref Logic Control Unit Reset Status Reset and start conversion Clock Input Counter Fig. -6 A dual slope integration type A/D converter. After an initial rest, the Start conversion pulse connects V in to the integrator via the logic control unit that simultaneously starts the counter. As soon as a preset count defining an integration time T is reached, the logic control unit switches the integrator input to a reference voltage V ref of appropriate polarity, so that the integrator output decreases at a constant rate. At the instance of switching, the counter is reset and starts a fresh count that stops when the comparator changes state, indicating that the integrator output ramp reaches zero. Let t be the time taken for the ramp to reach zero is, then V ref t = V int. The counter reading is proportional to t and is a digital representation of V in. So we see that: MSB (i) Operation independent of properties of integrator and frequency stability of clock, as long as they are constant during the conversion interval, which is easy to achieve. This is due to the fact that long term drifts in T and t cancel. (ii) Commonly used in digital voltmeters or multi-meters where slow conversion speeds are acceptable. LSB 0

11 (iii) High degree of rejection of line frequency (50 Hz) or any other fixed frequency interference can be achieved by suitable choice of T. Typical T is 0 ms. Remark: high resolution at moderate cost. (3) Voltage Comparator-Counter Loop Shown in Fig. -7. its principle is as follows. If the D/A output V out is < V in (the analog output), the counter counts up. If V out > V in, counter counts down. That is, the feedback loop tries to lock to V in continuously, and can give a valid Conversion complete only during the clock cycle immediately after the comparator has changed state. Can be used as a Sample and hold (see below) by stopping the count via the external control following a complete conversion. V in V out Comparator - DAC LSB Up-down Counter Up Down Clock External control Fig. -7 Voltage comparator-counter loop type A/D converter. (4) Multiple Comparator Type (Also known as Flash Converter) The fastest A/D converter available as depicted in Fig. -8. A series of n comparators C, C,..., C n, each with a successively smaller reference voltage, one LSB apart and starts with (/) LSB sorts the analog input into n thresholds. The role of the encoder will be clear after you have done the exercise. This type of converter is fast but very expensive since a large number of comparators are utilized. V in Analogue input R R R C C Encoder Coded digital output C n V ref R C N

12 Fig. -8 Comparators-encoder type A/D converter. (5) Voltage-to-Frequency Converter Shown in Fig. -9, a train of pulses is generated at a repetition rate proportional to the input analog voltage V in. A/D conversion is achieved by counting the number of pulses in a fixed time interval. V in is connected to an integrator that resets when the amplitude of its output ramp reaches a fixed reference voltage V ref of the comparator. The integrator is reset each time the comparator changes state and the pulse generated is fed to the counter via a gate that stays open for a fixed interval T. The repetition rate of these pulses is proportional to the magnitude of V in. Note: the pulse shaper shapes the triangular pulses to some appropriate shapes that can be counted by the counter. Analogue V in input R Comparator Pulse shaper Counter V out ref Gating interval T Fig. -9 A simple voltage-to-frequency type A/D converter. Vref Vref..6 Aliasing There is a very interesting phenomenon in A/D conversion known as aliasing discovered by H. Nyquist who made monumental contributions to electronics. Consider the following diagram showing that the analog signal to be recorded is sinusoidal (solid line) with a frequency much large the rate of A/D conversion (converted points are represented by the solid circles). Then the apparent frequency of the signal (represented by the dashed curve in the diagram) is then much less than the frequency of the input analog signal. This phenomenon has a very interesting connection with the reduced zone scheme in solid state physics where we are dealing with the relationship between a sound wave and a line of discrete atoms. (If you did not have a course on solid state physics, just ignore the last sentence.)

13 Nyquist Theorem In order to reproduce a signal accurately, the sampling rate should be larger than twice of the highest frequency component of the signal. Rationale: (Solid circles represent sampling points) Fig. 0 Aliasing due to under-sampling. Dashed curve: apparent signal; solid curve: signal to be recorded...7 Sample and Hold (S/H) Rationale S/H can be done digitally using the A/D converter shown in Fig. -7 or the analog circuit shown in Fig. -. When the switch S is closed, the capacitor C charges up exponentially to the input analog voltage V in via the buffer A i and the output follows the voltage across C, which is the Sample mode. When the switch S is opened at the Hold control input, the charges remain in C and represent the value of V in at the instant of the arrival of the control command, which is the Hold mode. S - - A i V C in Control Input Fig. - An analog sample and hold circuit. A o Output Ideal S/H output "Droop" Signal t Time Control Input 0 Sample Hold Hold Sample Time t is called the aperture time. *** END *** 3