6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits

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1 6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott

2 Recall Constant Envelope Modulation from Lecture 19 Baseband Input Baseband to RF Modulation Transmit Power Amp Transmitter Output Constant-Envelope Modulation Popular for cell phones and cordless phones due to the reduced linearity requirements on the power amp - Allows a more efficient power amp design Transmitter power is reduced

3 Frequency Shift Keying Transmit v(t) out(t) out(t) 1-1 Assume infinite bandwidth in this example S out (f) 2 f out(t) f o GHz Sends information encoded in instantaneous frequency - Can build simple transmitters and receivers Pagers use this modulation method Issue want to obtain high spectral efficiency - Need to choose an appropriate transmit filter - Need to choose an appropriate value of f

4 Transmit Selection S a (f) S Φmod (f) Φ mod (t) f 0 cos(φ mod (t)) sin(φ mod (t)) i t (t) q t (t) 0 0 S b (f) f f cos(2πf 2 t) sin(2πf 2 t) y(t) S y (f) -f o 0 f o f Recall from Lecture 19 that output spectrum is related in a nonlinear manner to transmit filter - Raised cosine filter is not necessarily the best choice We ll come back to this issue - Focus instead on choosing f

5 A More Detailed Model Assume DC gain = 1 cos(φ mod (t)) I(t) h 2T d Transmit f mod (t) 2π Φ mod (t) 1-1 T d for infinite transmit filter bandwidth h 2T d h 2T d T d T d sin(φ mod (t)) Q(t) hπ By inspection of figure The choice of f is now parameterized by h and T d - h is called the modulation index, T d is symbol period

6 MSK Modulation Q I Choose h such that the phase rotates ± 90 o each symbol period - Based on previous slide, we need h = 1/2 - Note: 1-bit of information per symbol period Bit rate = symbol rate

7 A More Convenient Model for Analysis Assume DC gain = 1 cos(φ mod (t)) I(t) T d x(t) 1 0 h 2T d Transmit f mod (t) 2π Φ mod (t) 1 T d h 2T d T d sin(φ mod (t)) Q(t) -1 for infinite transmit filter bandwidth h 2T d T d hπ Same as previous model, but we represent data as impulses convolved with a rectangular pulse - Note that h = 1/2 for MSK

8 Impact of Sending a Single Data Impulse Assume DC gain = 1 cos(φ mod (t)) I(t) T d x(t) T d Transmit f mod (t) 2π Φ mod (t) 1-1 T d for infinite transmit filter bandwidth 1 4T d 0 T d T d sin(φ mod (t)) Q(t) π/2 To achieve MSK modulation, resulting phase shift must be ± 90 o (i.e., π/4)

9 Include Influence of Transmit rect(t d,t) cos(φ mod (t)) I(t) x(t) 1 0 T d 1 4T d p(t) Transmit f mod (t) 2π Φ mod (t) 1-1 T d 1 4T d 0 Transmit filter bandwidth = B Hz T d T d sin(φ mod (t)) Q(t) π/2 For MSK modulation - Where * denotes convolution

10 Gaussian Minimum Shift Keying Definition - Minimum shift keying in which the transmit filter is chosen to have a Gaussian shape (in time and frequency) with bandwidth = B Hz Key parameters - Modulation index: as previously discussed h = 1/2 - BT d product: ratio of transmit filter bandwidth to data rate For GSM phones: BT d = 0.3

11 Project 2 Simulate a GMSK transmitter and receiver What you ll learn - How GMSK works at the system level - Behavioral level simulation of a communication system - Generation of eye diagrams and spectral plots - Analysis and simulation of discrete-time version of loop filter and other signals Note: you ll also be exposed a little to GFSK modulation - Popular for cordless phones - Similar as GMSK, but frequency is the important variable rather than phase Typical GFSK specs: h = 0.5 ± 0.05, BT d = 0.5

12 High Speed Data Links From Broadband Transmitter PC board trace Z o Package Interface Z in Amp In Clock and Data Recovery Data Clk Data Out Data In Phase Detector Loop Clk Out VCO A challenging component is the clock and data recovery circuit (CDR) - Two primary functions Extract the clock corresponding to the input data signal Resample the input data

13 PLL Based Clock and Data Recovery retimed PD Charge Pump Loop v(t) VCO Use a phase locked loop to tune the frequency and phase of a VCO to match that of the input data Performance issues - Jitter - Acquisition time - Bit error rate (at given input levels) Let s focus on specifications for OC i.e., 10 Gbit/s SONET

14 Jitter Generation retimed PD Charge Pump Loop v(t) VCO Definition - The amount of jitter at the output of the CDR when no jitter (i.e., negligible jitter) is present on the data input SONET requires - < 10 mui rms jitter - < 100 mui peak-to-peak jitter Note: UI is unit interval, and is defined as the period of the clk signal (i.e., 100 ps for 10 Gbit/s data rates)

15 Jitter Tolerance retimed PD Charge Pump Loop v(t) VCO Definition - The maximum amount of jitter allowed on the input while still achieving low bit error rates (< 10e-12) SONET specifies jitter tolerance according to the frequency of the jitter - Low frequency jitter can be large since it is tracked by PLL - High frequency jitter (above the PLL bandwidth) cannot be as high (PLL can t track it out) Limited by setup and hold times of PD retiming register

16 Example Jitter Tolerance Mask OC -192 Jitter Tolerance Mask Jitter Tolerance U.I. 15 UI 1.5 UI Acceptable Region CDR tested for tolerance compliance by adding sine wave jitter at various frequencies (with amplitude greater than mask) to the data input and observing bit error rate 0.15 UI 2.4 khz 24 khz 400 khz 4 MHz 100 MHz Jitter Frequency (Hz)

17 Jitter Transfer retimed PD Charge Pump Loop v(t) VCO Definition - The amount of jitter attenuation that the CDR provides from input to output SONET specifies jitter transfer by placing limits on its transfer function behavior from input to output - Peaking behavior: low frequency portion of CDR transfer function must be less than 0.1 db - Attenuation behavior: high frequency portion of CDR transfer function must not exceed a mask limit

18 Example Jitter Transfer Mask OC-192 Jitter Transfer Mask Maximum Allowed "Peaking" = 0.1 db Magnitude (db) Acceptable Region khz 100 khz 1 MHz 8 MHz 100 MHz Frequency (Hz) CDR tested for compliance by adding sine wave jitter at various frequencies and observing the resulting jitter at the CDR output

19 Summary of CDR Performance Specifications Jitter - Jitter generation - Jitter tolerance - Jitter transfer (and peaking) Acquisition time - Must be less than 10 ms for many SONET systems Bit error rates - Must be less than 10e-12 for many SONET systems

20 Phase Detectors in Clock and Data Recovery Circuits retimed PD Charge Pump Loop v(t) VCO Key issue - Must accommodate missing transition edges in input data sequence Two styles of detection - Linear PLL can analyzed in a similar manner as frequency synthesizers - Nonlinear PLL operates as a bang-bang control system (hard to rigorously analyze in many cases)

21 Popular CDR Phase Detectors Hogge Detector (Linear) Bang-Bang Detector (Nonlinear) retimed Reg Reg D Q D Q Reg Latch D Q D Q retimed Reg Latch D Q D Q Linear - Hogge detector produces an error signal that is proportional to the instantaneous phase error Nonlinear - Alexander (Bang-bang) detector produces an error signal that corresponds to the sign of the instantaneous phase error

22 A Closer Look at the Hogge Detector Hogge Detector (Linear) B Reg A C Latch D Q D Q retimed A(t) retimed B(t) C(t) Error output,, consists of two pulses with opposite polarity - Positive polarity pulse has an area that is proportional to the phase error between the data and clk - Negative polarity pulse has a fixed area corresponding to half of the clk period - Overall area is zero when data edge is aligned to falling clk edge

23 Example CDR Settling Characteristic with Hogge PD 0.6 Instantaneous Phase Error vs Time for CDR 1 (Hogge Detector) (Steady-State RMS Jitter = mui) Instantaneous Phase Error (UI) CDR tracks out phase error with an exponential transition response Jitter occuring at steady state is due to VCO and non-idealities of phase detector

24 Modeling of CDR with Hogge Detector Hogge Detector Φ data (t) Phase Sampler α 1 π Charge Pump i(t) I cp Loop H(s) v(t) VCO 2π K v s Φ out (t) α = transition density 0 < α < 1, = 1/2 for PRBS input Similar to frequency synthesizer model except - No divider - Phase detector gain depends on the transition density of the input data The issue of transition density - Phase error information of the input data signal is only seen when it transitions VCO can wander in the absence of transitions - Open loop gain (and therefore the closed loop bandwidth) is decreased at low transition densities

25 A Common Loop Implementation Φ data (t) Hogge Detector Phase Sampler Charge Pump Loop VCO 1 i(t) v(t) Φ α K out (t) 2π v π I cp H(s) s α = transition density 0 < α < 1, = 1/2 for PRBS input i(t) v(t) R 1 C 1 C 2 C = C 1 C 2 C 1 +C 2 H(s) = 1 s(c 1 +C 2 ) 1+sR 1 C 2 1+sR 1 C = 1+s/w z sc tot (1+s/w p ) Use a lead/lag filter to implement a type II loop - Integrator in H(s) forces the steady-state phase error to zero (important to minimize jitter)

26 Open Loop Response and Closed Loop Pole/Zeros Open loop gain increased 20log A(f) Evaluation of Phase Margin C Closed Loop Pole Locations of G(f) Im{s} B Dominant pole pair 0 db 120 o -140 o angle(a(f)) f z f p C B A f PM = 54 o for B PM = 53 o for A PM = 55 o for C Non-dominant pole A B C A A Re{s} o B -180 o C Key issue: an undesired pole/zero pair occurs due to stabilizing zero in the lead/lag filter

27 Corresponding Closed Loop Frequency Response G(w) Peaking caused by undesired pole/zero pair w cp w z 1 0 w z w o Frequency (rad/s) w Undesired pole/zero pair causes peaking in the closed loop frequency response SONET demands that peaking must be less than 0.1 db - For classical lead/lag filter approach, this must be achieved by having a very low-valued zero Requires a large loop filter capacitor

28 An Interesting Observation X(s) N A (s) D A (s) Y(s) N B (s) D B (s) Calculation of closed loop transfer function Key observation - Zeros in feedback loop do not appear as zeros in the overall closed loop transfer function!

29 Method of Achieving Zero Peaking retimed PD Charge Pump Loop v(t) VCO We can implement a stabilizing zero in the PLL feedback path by using a variable delay element - Loop filter can now be implemented as a simple integrator Issue: delay must support a large range See T.H. Lee and J.F. Bulzacchelli, A 155-MHz Clock Recovery Delay- and Phase-Locked Loop, JSSC, Dec 1992 Adjustable Delay Element

30 Model of CDR with Delay Element Φ data (t) Hogge Detector Phase Sampler VCO 1 i(t) v(t) Φ α K out (t) 2π v π I cp H(s) α = transition density 0 < α < 1, = 1/2 for PRBS input Charge Pump Loop K d s Note: K v units are Hz/V Note: K d units are radians/v Delay gain, K d, is set by delay implementation Note that H(s) can be implemented as a simple capacitor - H(s) = 1/(sC)

31 Derivation of Zero Produced by Delay Element Φ data (t) Hogge Detector Phase Sampler VCO 1 i(t) v(t) Φ α K out (t) 2π v π I cp H(s) α = transition density 0 < α < 1, = 1/2 for PRBS input Charge Pump Loop K d s Note: K v units are Hz/V Note: K d units are radians/v i(t) Loop H(s) v(t) VCO 2π K v s Φ out (t) i(t) Loop H(s) v(t) VCO 2π K v s Φ out (t) s 2πK v K d K d K v s 1+ 2π Zero set by ratio of delay gain to VCO gain

32 Alternate Implementation retimed PD Charge Pump Loop v(t) Adjustable Delay Element VCO -1 Can delay data rather than clk - Same analysis as before

33 The Issue of Data Dependent Jitter retimed Φ clk (t) PD Charge Pump Loop v(t) VCO For classical or Bulzacchelli CDR - Type II PLL dynamics are employed so that steady state phase detector error is zero Issue: phase detector output influences VCO phase through a double integrator operation - The classical Hogge detector ends up creating data dependent jitter at the VCO output

34 Culprit Behind Data Dependent Jitter for Hogge PD Hogge Detector (Linear) B C A(t) retimed B(t) C(t) A Reg Latch D Q D Q retimed The double integral of the pulse sequence is nonzero (i.e., has DC content) - Since the data transition activity is random, a low frequency noise source is created Low frequency noise not attenuated by PLL dynamics

35 One Possible Fix Hogge Detector (Linear) A(t) B 2 C D retimed B(t) C(t) Reg D Q A Latch D Q Latch D Q retimed D(t) Modify Hogge so that the double integral of the pulse sequence is zero - Low frequency noise is now removed See L. Devito et. al., A 52 MHz and 155 MHz Clockrecovery PLL, ISSCC, Feb, 1991

36 A Closer Look at the Bang-Bang Detector Bang-Bang Detector (Nonlinear) Reg D Q D Q Reg A Reg Latch D Q D Q B retimed C D A(t) retimed B(t) C(t) D(t) Error output consists of pulses of fixed area that are either positive or negative depending on phase error Pulses occur at data edges - Data edges detected when sampled data sequence is different than its previous value Above example illustrates the impact of having the data edge lagging the clock edge

37 A Closer Look at the Bang-Bang Detector (continued) Bang-Bang Detector (Nonlinear) Reg D Q D Q Reg A Reg Latch D Q D Q B retimed C D A(t) retimed B(t) C(t) D(t) Above example illustrates the impact of having the data edge leading the clk edge - Error pulses have opposite sign from lagging edge case

38 Example CDR Settling Characteristic with Bang-Bang PD 0.05 Instantaneous Phase Error vs Time for CDR 2 (Bang-Bang Detector) (Steady-State RMS Jitter = mui) Instantaneous Phase Error (UI) Time (Micro Seconds) Bang-bang CDR response is slew rate limited - Much faster than linear CDR, in general Steady-state jitter often dominated by bang-bang behavior (jitter set by error step size and limit cycles)

39 The Issue of Limit Cycles Bang-Bang Style Phase Detector Φ clk (t) Sense Drive v(t) VCO v(t) Φ clk (t) Bang-bang loops exhibit limit cycles during steadystate operation - Above diagram shows resulting waveforms when data transitions on every cycle - Signal patterns more complicated for data that randomly transitions For lowest jitter: want to minimize period of limit cycles

40 The Impact of Delays in a Bang-Bang Loop Bang-Bang Style Phase Detector Φ clk (t) Sense Delay Drive v(t) VCO v(t) Φ clk (t) v(t) Φ clk (t) Delays increase the period of limit cycles, thereby increasing jitter

41 Practical Implementation Issues for Bang-Bang Loops Minimize limit cycle periods - Use phase detector with minimal delay to error output - Implement a high bandwidth feedforward path in loop filter One possibility is to realize feedforward path in VCO See B. Lai and R.C Walker, A Monolithic 622 Mb/s Clock Extraction Data Retiming Circuit, ISSCC, Feb 1991 Avoid dead zones in phase detector - Cause VCO phase to wonder within the dead zone, thereby increasing jitter Use simulation to examine system behavior - Nonlinear dynamics can be non-intuitive - For first order analysis, see R.C. Walter et. al., A Two- Chip 1.5-GBd Serial Link Interface, JSSC, Dec 1992

42 Delay-Locked Loops Clock and Data arrive misaligned in phase Adjustable Delay Element PD Charge Pump Loop retimed v(t) adjusted Clock and Data are now re-aligned in phase In some applications you have a reference clock that is perfectly matched in frequency to data sequence - Phase mismatch is present due to different propagation delays between clock and data on the PC board A delay-locked loop limits adjustment to phase (as opposed to phase and frequency) - Faster, and much simpler to design than PLL structure

43 Some References on CDR s and Delay-Locked Loops Gu-Yeon Wei will discuss DLL s in his guest lecture Tom Lee has a nice paper - See T. Lee et. al., A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM, JSSC, Dec 1994 Check out papers from Mark Horowitz s group at Stanford - Oversampling data recovery approach See C-K K. Yang et. al., A 0.5-um CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery using Oversampling, JSSC, May Multi-level signaling See Ramin Farjad-Rad et. al., A 0.3-um CMOS 8-Gb/s 4- PAM Serial Link Transceiver, JSSC, May Bi-directional signaling See E. Yeung, A 2.4 Gb/s/pin simultaneous bidirectional parallel link, JSSC, Nov 2000

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