AN ABSTRACT OF THE THESIS OF

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2 AN ABSTRACT OF THE THESIS OF Brian George Drost for the degree of Master of Science in Electrical and Computer Engineering presented on June 3, Title: Time-Based Analog Signal Processing Abstract approved: Pavan Kumar Hanumolu As CMOS processes size continues to shrink, a number of factors limit the ability of analog circuit performance to scale with the process. These issues include smaller transistor intrinsic gains and lower supply voltages. However, scaling continues to increase the speed and decrease the power of digital circuits. In this thesis, an active time-based integrator is proposed to replace amplifiers. The integrator, implemented using highly digital ring oscillators, seeks to take advantage of benefits offered by technology scaling while negating the issues of low gain and low supply voltages. The proposed integrator topology is used in a 20MHz 4th order continuous-time analog filter. Designed in a 90nm CMOS process, the time-based continuous-time filter achieves superior noise and linearity performance compared to state-of-the-art conventional active RC filters in simulations.

3 c Copyright by Brian George Drost June 3, 2011 All Rights Reserved

4 Time-Based Analog Signal Processing by Brian George Drost A THESIS submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science Presented June 3, 2011 Commencement June 2012

5 Master of Science thesis of Brian George Drost presented on June 3, APPROVED: Major Professor, representing Electrical and Computer Engineering Director of the School of Electrical Engineering and Computer Science Dean of the Graduate School I understand that my thesis will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my thesis to any reader upon request. Brian George Drost, Author

6 ACKNOWLEDGEMENTS First, thank you to Dr. Pavan Kumar Hanumolu, my advisor. He provided the mentoring and resources that allowed my senior design group to tapeout a chip as undergraduates. Without this experience, I would not have focused my studies on integrated circuit design. I would also like to thank him also for his encouragement, patience, and time during my years as graduate student, and for allowing me to pursue the ideas published in this thesis. Second, I would like to thank some of my fellow electrical engineering graduate students. Thanks to Jon Guerber and Sachin Rao for listening to my ideas and answering my questions, to Brian Young whose work with replacing opamps with oscillators inspired this research, and to Mrunmay Talegaonkar, Karthik Reddy, Amr ElShazly, and Nima Maghari for assistance in taping out my chips. I d like to also give special thanks to Bangda Yang. He both worked with me on my initial research into power supply cancellation and was the one to invite me into that first project group under Dr. Hanumolu. Just as with Dr. Hanumolu, Bangda was instrumental in my path leading to this research. Lastly, I d like to thank my family. Thank you to my siblings for their friendship, but a special thanks to my mother, Monica, and father, Michael for their love and encouragement.

7 TABLE OF CONTENTS Page 1 Introduction Conventional Analog Signal Processing Techniques Conventional Uses of Ring Oscillators Ring Oscillators in Signal Processing Ring Oscillators as Quantizers Ring Oscillators as Pulse Width Modulators Ring Oscillators as Integrators Ring Oscillators Integrators Basic Operation of Ring Oscillators Phase-Locked Loop Based Integrator A Differential Ring Oscillator Integrator Phase Detectors in the Integrator Multi-Phase Integrators Modeling Multi-Phase PWM Signals Common Mode Issues Integrator Bandwidth and Tuning Building Networks of Integrators Ring Oscillator Modelling and Design Oscillator Design Requirements Noise in Ring Oscillators Jitter Versus Phase Noise Effect of Ring Length on Noise Performance Frequency and Voltage Gain of Inverter-Based Oscillators Current and Power Relationships in Inverter-Based Oscillators Linearity and Distortion Delay Cell Topology Design of the Integrator Ring Oscillators Choosing Transistor Lengths Choosing Transistor Widths

8 TABLE OF CONTENTS (Continued) Page Choosing the Number of Stages Oscillator Bandwidth and Parasitic Pole Ring Oscillator-Based Integrator Circuit Level Design Phase Detector Design Charge Pump Design Linearity and Distortion Issues Noise Issues Topology and Implementation Level Shifter Design Filter Design Using Ring Oscillator Integrators Improving Integrator Linearity with Resistors Performing Input Voltage-to-Current Conversion Output PWM-to-Voltage Conversion Bias/Reference Generation Design Overview Loop Compensation Block Descriptions Simulation Results Estimating Filter Nonlinearity Nonlinearity in a Frequency Independent Closed Loop Using Linear Analysis to Estimate Open Loop Distortion Using Linear Analysis to Estimate Closed Loop Distortion Using Linear Analysis to Estimate Distortion in a Network Filter Design Procedure System Level Design Circuit Level Design Simulated Performance Future Research and Improvements Frequency Feedback Integrator Tuning

9 TABLE OF CONTENTS (Continued) Page 6.3 Using Oscillator-Based Integrators in a Delta-Sigma ADC Motivation for Use as ADC Design Challenges

10 Figure LIST OF FIGURES Page 1.1 A common source amplifier and its small signal model A multiply by N charge pump phase locked loop Linear model of a multiply by N charge pump phase locked loop Linear model of a ring oscillator frequency quantizer Linear model of a ring oscillator phase quantizer Phase domain model of a voltage controlled ring oscillator Phase domain model of a current controlled ring oscillator A three stage single ended ring oscillator A four stage differential ring oscillator Simulated K V CO and K CCO versus supply voltage for an inverted based ring oscillators A single ended current mode oscillator based integrator A single ended current mode oscillator based integrator A differential current mode oscillator based integrator Simulated K V CO and K CCO versus supply voltage for a pair of inverted based ring oscillators An XOR gate used as a phase detector The output of an XOR phase detector with a phase error of pi/ The output of an XOR phase detector with a phase error of pi/4 (top) and pi/4 (bottom) overlaid an output with a phase error of pi/ The transfer characteristic of an XOR phase detector A differential current mode oscillator-based integrator using multiple oscillator phases Example PWM waveforms of different duty ratios

11 Figure LIST OF FIGURES (Continued) Page 2.16 Plot of average voltage of a PWM waveform versus duty ratio The spectrum of a pulse width modulated sine wave. The modulation frequency is 20 times the input frequency. Dithering noise is also added The sum of two PWM phases of a sine waves. The modulation frequency is 20 times the input frequency The spectrum of two PWM phases of a sine waves. The modulation frequency is 20 times the input frequency. Dithering noise is also added The sum of 12 PWM phases of a sine waves. The modulation frequency is 20 times the input frequency The spectrum of 12 PWM phases of a sine waves. The modulation frequency is 20 times the input frequency A single-ended ring oscillator-based integrator biased to the reference frequency A differential integrator with an open loop common mode A differential integrator with a closed loop common mode A block diagram of a biquad section. The biquad requires integrators and gain blocks A first order low pass filter implemented using the proposed integrator topology (shown single ended for simplicity) Block diagram showing the similarities between the proposed oscillatorbased integrator and a Gm-C integrator. Blocks of similar function are shown in the same color An example oscillator phase noise plot An inverter-based ring oscillator and its small signal model An inverter delay cell model that assumes the delay is caused by RC settling

12 Figure LIST OF FIGURES (Continued) Page 3.4 Schematic of the differential delay cell used in the proposed integrator s oscillators Small signal model of the proposed integrator. The oscillator is modeled as both a resistor and a capacitor One implementation of a two-state phase detector (SR flip-flop) Asymmetric and symmetric implementations of a CMOS XOR gate Output current waveforms for different input duty ratios from a charge pump with finite rise time Schematics of NMOS and PMOS source-switched charge pumps used in the integrator. Lengths that are not given are minimum. Common mode charge pumps use only the NMOS variety Simulated duty ratio to current transfer characteristic of the proposed charge pump topology (25 ua is the maximum current) Simulated charge pump current waveforms for different input duty cycles with a PWM frequency of 200 MHz (50 ua is the maximum current) Schematic of the level shifter. All devices are minimum length Level shifter output waveforms plotted versus time for various process corners Ring oscillator based integrator block diagram with linearity improving resistor Small signal model of ring oscillator integrator with linearity improving resistor. The oscillator resistance and added resistance appear in parallel Ring oscillator based integrator block diagram with voltage input Filter output stage used to convert multi-phase PWM waveforms to an analog voltage Schematic diagram of the bias/reference generator

13 Figure LIST OF FIGURES (Continued) Page 5.6 Schematic diagram of the phase frequency detector used in the bias generator Schematic diagram of the charge pump drivers. Cross-coupled resistors are used to align complementary signals Loop gain Bode plots for the bias generator across process and temperature corners Models of a nonlinear open loop system used to calculate distortion Model of a nonlinear closed loop system for the fundamental frequency Model of a nonlinear closed loop system for the second and third harmonic frequencies th order ring oscillator filter block diagram. Ring oscillator integrators are shown as integrators and charge pump groups are shown as gain blocks Simulated frequency response of the proposed filter Simulated cumulative output noise power versus frequency normalized to a full scale output Simulated filter differential output waveform for 20 MHz full scale input Simulated filter differential output spectrum for 20 MHz full scale input. No HD3 is visible, but additional tones are present due to multi-phase PWM currents Simulated filter differential output spectrum for two-tone input (19 MHz and 20 MHz). IM3 tones are visible A ring oscillator-based integrator with frequency feedback to improve linearity. It is shown single ended for simplicity A pulse generator-based linear frequency detector

14 Table LIST OF TABLES Page 4.1 Comparison table of XOR and two-state phase detectors Simulated performance summary of the proposed time-based filter Performance comparison with recent low pass filters of similar bandwidth (SNR is measured with noise in 1 MHz band)

15 Chapter 1 Introduction As CMOS process scaling continues, analog and mixed signal designers are struggling to take advantage of smaller transistor sizes. While scaling improves digital circuit performance by increasing speed and decreasing power consumption, it does not offer the same benefits to traditional analog circuits. Instead, the lower supply voltages and smaller amplifier gains make the design of precision analog circuits challenging. In this thesis, we propose a new approach that uses ring oscillators and other digital circuit blocks to implement analog circuits. By using blocks that take advantage of the process scaling, the proposed techniques allow analog circuit performance to continue to improve as process size shrinks. 1.1 Conventional Analog Signal Processing Techniques Conventional analog design usually relies on amplifiers that provide high gain. Because feedback is used so often in analog design, amplifiers are found in a wide variety of circuits. A few examples of circuits that often contain amplifiers are listed below: Delta/Sigma ADCs Pipeline ADCs

16 2 Analog Filters Linear Regulators CMOS RF Receivers While amplifiers are widely used, they suffer from an inability to scale well with process size. Amplifiers designed in CMOS processes use MOSFETs in their saturation mode of operation where the devices acts as variable current sources. Gain is produced by varying the transistor current and then running that current through a high resistance. This allows small changes in current to produce large changes in voltages. When capacitances, either intentional or parasitic, are added, the amplifiers bandwidth is limited. Smaller length transistors have less parasitic capacitances for the same transconductance (g m ), which can allow higher amplifier bandwidths. Figure 1.1: A common source amplifier and its small signal model

17 3 However, while bandwidth does scale with process, several other performance metrics do not. In the amplifier shown in Fig. 1.1, the gain is: A v = g m (r on + r op ) (1.1) If this amplifier has large gain, either the transconductance (g m ) or the output resistances (r on and r op ) must be large. An often used quantity is the MOSFETs intrinsic gain, which is g m r o. If a square law model is assumed, the intrinsic gain becomes: g m r o = 2µC ox W L I D ( 1 I D ) = 2µC ox W L I D (1.2) If the channel length modulation parameter (λ) is assumed to be inversely proportional to the length (L), then the intrinsic gain is proportional to the square root of the length. As lengths decrease due to process scaling, so does the intrinsic gain. When an analog designer attempts to take advantage of smaller lengths to increase amplifier bandwidths, this analysis shows that low frequency gains will suffer. Designers can compensate for this by doing one of two things: Increasing the number of stages Cascoding or gain boosting stages Increasing the number of stages makes the amplifier more difficult to compensate, which limits the bandwidth. This can make decreasing lengths counterproductive, as the compensation issues can cancel the improved bandwidth of using

18 4 smaller length. In addition, more stages usually means more power consumption when compared with a single stage amplifier. Cascoding or gain boosting can be used to increase the gain of a single stage arbitrarily high, but reduces the available output swing of the amplifiers. In deep submicron processes, low supply voltages can make these techniques impractical as stacking transistors will leave only a few hundred millivolts of headroom for the signal. For designs that use amplifiers, the combination of low intrinsic gains and low supply voltages has been a difficult design challenge to overcome. With no alternatives, designers are forced to use multi-stage designs despite their limitations. 1.2 Conventional Uses of Ring Oscillators Oscillators in general have a large number of uses in a variety of analog and digital circuits. In most digital circuits, a clock is required to synchronize the operation of the circuit. A low frequency clock can be generated directly from a quartz crystal. If a high frequency clock is needed, a low frequency clock must be multiplied using a phase locked loop (PLL) or another clock multiplier circuit. A PLL is a feedback circuit that tunes the frequency and phase of an oscillator to match a reference clock. PLLs are used in CMOS radios, serial links, and for clock generation for both analog and digital circuits. A block diagram of a conventional charge pump PLL is shown in Fig This PLL topology has four blocks: a phase detector (PD), a loop filter including a charge pump (CP/LF),

19 5 and a voltage controlled oscillator (VCO). Figure 1.2: A multiply by N charge pump phase locked loop PLLs are feedback loops that force the phase of the output clock to be aligned to the phase of the reference clock. This allows clock multiplication when a divider is inserted into the feedback path. It also allows the phase noise of the oscillator to be suppressed within the PLL s bandwidth. As with any feedback system, it is important to ensure the system is stable. The voltage controlled oscillator acts as a voltage to frequency converter, which is equivalent to a voltage to phase integrator. If the combination of the phase detector, charge pump, and loop filter produces a control voltage that is proportional to the phase error, then the PLL is stable, because the only phase shift is from the VCO s pole. A linear model of a PLL is shown in Fig. 1.3: However, the charge pump needs to provide an additional integrator to the loop to increase the locking range and reduce static phase offset. This contributes an additional pole, which would make the loop unstable without additional compensation. To remedy this problem, the loop filter must add a zero as well to cancel most of the phase shift caused by the charge pump pole. It is important to note

20 6 Figure 1.3: Linear model of a multiply by N charge pump phase locked loop that PLLs can be designed without the loop filter, but it limits their usefulness for frequency synthesis. The oscillator used in a PLL must be tunable. Usually it is a voltage controlled oscillator, whose frequency the feedback can adjust by varying a control voltage. Ring oscillators are a commonly-used type of VCO that use tunable delay elements. While an LC oscillator can achieve better noise performance, ring oscillators are smaller in area and have a wider frequency tuning range. The result is that ring oscillators are well suited for lower frequency, lower performance applications where area and tuning range are more critical than noise and power. For example, ring oscillators are commonly used for clock generation in digital systems where absolute timing accuracy is not required. Ring oscillators can also be used to characterize a process. If their delay is highly transistor-dependent, then variations in process will cause variations in the oscillators frequency.

21 7 1.3 Ring Oscillators in Signal Processing Several recent papers have proposed using ring oscillators outside of the frequency synthesis area. These papers use ring oscillators for performing an operation on an analog signal. At this point, ring oscillators have been used in two main applications: Pulse Width Modulators Quantizers Ring Oscillators as Quantizers Ring oscillator quantizers convert an analog voltage signal into a digital number. Two main techniques have been proposed to accomplish this: Frequency Quantizer Phase Quantizer The first technique utilizes the fact that the ring oscillators frequency can be changed with a voltage or a current as in a PLL. The relationship between the input voltage and frequency for many ring VCOs is monotonic and relatively linear, so the output frequency is approximately proportional to the input voltage. To quantize the frequency, the number of periods can be counted over a fixed time interval by counting either rising or falling edges. For example, a 1GHz oscillator has 1000 periods in a one microsecond time interval. If the number of periods

22 8 varies from 1000, then the input voltage must have changed. The result is that the counter s output is a quantized version of the input voltage. A great advantage of this technique is that the quantizer will provide first order noise shaping. This is the same technique delta-sigma ADCs use to achieve high accuracies without using high accuracy quantizers. Usually delta-sigma ADCs need a feedback digital-to-analog converter (DAC) and analog integrators, commonly implemented using opamps, but a ring oscillator used as a frequency quantizer needs neither. The noise shaping results from the quantizer reusing the quantization error from the previous conversion. Even though the quantizer only has the time resolution of an oscillator period, the oscillator itself is an analog circuit and its current phase is an analog value. At the instant of sampling, the oscillator will have completed an integer number of periods. The portion of the period currently in progress will give the oscillator a head start during the next sampling interval, effectively adding the quantization error from the previous sample into the next sample. Figure 1.4: Linear model of a ring oscillator frequency quantizer Another method of explaining this noise shaping is to look at the oscillator as a voltage to phase integrator. Then the quantization operation actually quantizers the phase and performs a differencing operation. As can be seen in Fig. 1.4, the

23 9 quantization error will be multiplied by (1 z 1 ), which first order noise shapes it. Later work improved on this technique by taking advantage of the multiple phases of ring oscillators [1]. A counter can be added to each phase and then summed to produce the digital output word. This improves the time resolution of the quantizer to a fraction of the oscillator s period. Further modifications have been made to decrease the quantizer s complexity by simplifying the frequency counter down to two flip-flops and a exclusive or (XOR) gate. If higher resolution is required, the output stream can be filter and decimated to take advantage of the quantizer s noise shaping property. The main disadvantage of this quantizer is the voltage-to-frequency nonlinearity of the oscillator. A nonlinear voltage to frequency conversion creates tones, which limits the effective resolution of the quantizer even when the output is decimated. Three techniques have been proposed to solve this problem: Embed the quantizer in a delta-sigma loop so that the loop gain suppresses the distortion [2]. Use two oscillators differentially to suppress the even order harmonics [3]. Use digital correction to compensate for the nonlinearity [3]. Each of these methods has its advantages and disadvantages, but the conclusion from this discussion is that oscillator nonlinearity is often a significant drawback of using oscillators for signal processing. This is certainly an issue that must be

24 10 addressed when using an oscillator for any sort of signal processing, not just as a quantizer. The second variety of ring oscillator quantizers is phase quantizers. This quantizer style was used in [4] as the quantizer in a delta-sigma ADC. These quantizers sample the oscillators state with flip-flops. Effectively, the phase is directly quantized, which removes the differencing operation and the noise shaping. The advantage is that the quantizer now performs an integration operation as shown in Fig If the quantizer is placed in a feedback loop, its own gain can be used to suppress its nonlinearity. This also allows for easier integration into a delta-sigma ADC; the quantizer is also the last integrator in the loop. Clearly, this topology must be used inside a loop while the frequency quantizer can be used as a standalone ADC. Figure 1.5: Linear model of a ring oscillator phase quantizer Ring Oscillators as Pulse Width Modulators Pulse width modulation is a technique for encoding an analog signal as the average of a two-level waveform. This means the waveform can only be high or low, like a digital signal, but the time it is high or low can be an analog value. If the

25 11 modulation frequency, the frequency at which the waveform alternates from high to low and back, is filtered out, the original analog waveform is recovered. Ring oscillators can be used to perform pulse width modulation (PWM) by comparing their output phase against a reference phase. The phase difference is also a time difference, which can be either the high or low time of the waveform. The modulation frequency will be the frequency of the reference. Ring oscillators act as integrators when converting a signal to phase, so using them to directly generate a PWM waveform will include an integration operation. As a result, the PWM generator in [5] uses feedback to change the circuits transfer function to remove the integration. While other methods exist for generating PWM waveforms, the biggest advantage of ring oscillators is that a multiple phase waveform can be easily created. Ring oscillators usually provide multiple phases, one from each stage in the ring. If these are compared with multiple reference signals, then multiple PWM waveforms are generated that are out of phase with each other. For example, a four phase PWM system would have each waveform 90 out of phase with the two adjacent phases. 1.4 Ring Oscillators as Integrators Many conventional analog circuits are opamp based. When high gain is required, the circuit must include opamps. Because opamps are often performing the role of an integrator, higher gain is preferred. The designer must make a trade-off

26 12 between the nonideality of finite DC gain and the penalties of increasing opamp s gain. Oscillators are true integrators with infinite DC gain, but have not been used as a purely analog integrator. Past designs that used ring oscillators for signal processing applications have focused on their use as blocks that have a more digital output, such as quantizers and PWM generators. If a ring oscillator-based analog integrator is developed, opamp integrators in a variety of applications could be replaced with oscillator integrators. Oscillators do not have a reduction in DC gain at smaller process sizes. In addition, as process size reduces, the delay of each stage in the ring can be reduced. This lets the oscillators quantizers time resolution scale with process, which allows its performance to also scale with process. In general, ring oscillators with delay elements based on transistors can have increased frequency and tuning range as the length of the transistors shrinks. As a consequence, a ring VCOs gain (the constant of proportionality between the input voltage and output frequency) will also increase as the transistors become smaller. Because VCOs can also be modeled as a voltage to phase integrator, their ability to scale with process allows higher unity-gain bandwidth, much like opamps. However, there is no need to consume voltage headroom through cascoding or gain boosting and there is no need to use multiple stages. Ring oscillators bandwidths scale with process, but their gain does not scale poorly like opamps. The goal of this work is to investigate using ring oscillators as analog integrators, not purely as quantizers. A proposed design is developed and simulated, which will be prototyped and tested at a later date. The hypothesis for this design

27 13 is that ring oscillator-based integrators can outperform opamp based designs when the processs minimum length is small. Overall, few transistors will be used in an analog manner as current sources in saturation. Rather, the majority of transistors will be used as switches similar to digital CMOS circuits.

28 14 Chapter 2 Ring Oscillators Integrators If ring oscillators are to be used to replace operational amplifiers as the active element in integrators, a circuit must be created that performs the same function as an opamp. While it has been shown that oscillators are true integrators with infinite DC gain, the problem is that ring oscillators are voltage-to-phase or currentto-phase integrators, but not voltage-to-voltage or current-to-current integrators. Additional circuitry must be added around the oscillators to convert back from phase to currents or voltages. 2.1 Basic Operation of Ring Oscillators Before discussing the proposed integrator, the basics of ring oscillators must be understood. To begin modeling ring oscillators in a way that can be used to design signal processing circuits with them, PLLs should be examined first. Because PLLs are a common circuit found in wide variety of applications, they are a heavily researched area which contains a large base of knowledge. PLLs are inherently nonlinear systems. A VCO is used to perform frequency modulation and then this clock signal is essentially demodulated by the phase detector (PD) when it is compared with the input clock. Analyzing the circuit completely in the voltage domain would be very complicated, so instead designers use a phase domain model.

29 15 The key change is that the output variable of the VCO becomes a phase variable, not a voltage variable. Usually, the phase variable (φ) represents the phase difference between the edge of the output clock and an ideal clock. For this reason, the phase difference and time difference between the edges is proportional: t = ( φ) T clk 2π (2.1) Because frequency is the derivative of phase, an ideal VCOs frequency is proportional to its input voltage. Usually the constant of proportionality is denoted by K V CO, or the oscillator gain. If the output variable is phase, then the VCO becomes a voltage-to-phase integrator: V in K V CO = f = dφ dt (2.2) φ = V in K V CO dt (2.3) Figure 2.1 shows the oscillator s s-domain representation. When the output is a phase, the oscillator performs an integration (denoted by 1/s in the s-domain model). This integration operation allows oscillators to perform a similar role as opamps, if the phase can be converted back to a voltage. The previous model is typically used in the design of PLLs because conventional designs generate a control voltage. However, some ring oscillators can also be modeled as using a control current. The current controlled oscillator (CCO) functions much the same, but with a different gain constant (K CCO ) as shown in

30 16 Figure 2.1: Phase domain model of a voltage controlled ring oscillator Fig Figure 2.2: Phase domain model of a current controlled ring oscillator Ring oscillators can be either single ended or differential. Single ended circuits are limited to an odd number of identical phases, because the entire ring must generate an 180 phase shift. The number of stages in an oscillator is defined as M [6]. A single ended oscillator produces M phases. An example of a three-stage single ended oscillator is shown in Fig Figure 2.3: A three stage single ended ring oscillator Differential oscillators have delay elements with both positive and negative inputs and outputs. The ring can now have an even number of stages and it produces 2M phases (or M pairs of complimentary phases). An example fourstage differential oscillator is shown in Fig. 2.4:

31 17 Figure 2.4: A four stage differential ring oscillator From the previous diagram, it can be seen that the total delay around the loop is M, (the number of delay stages for either single ended or differential topologies) multiplied by the delay of each element (t d ). Because each clock period requires two trips around the loop, one for the rising edge and one for the falling edge, the clock period is: T = 2Mt d (2.4) The oscillation frequency is the reciprocal of the period, which means that the oscillation frequency is inversely proportional to the number of stages used. f = 1 2Mt d (2.5) Equation 2.5 shows that the designer has two basic knobs to adjust the frequency of oscillation: the number of stages and the stage delay, (t d ). During operation, the number of stages can not be changed (in simple applications), so it is the delay that must be tuned. For perfect linearity, the stage delay must be inversely proportional to the controlling voltage or current. In reality, the de-

32 18 lay will never be perfectly inversely proportional, so the oscillator will have some nonlinearity in its transfer characteristic. The exact shape of the transfer curve depends upon the delay cell topology and will be discussed in more detail later. An example plot of K V CO and K CCO for an inverter based ring oscillator is shown in Fig Figure 2.5: Simulated K V CO and K CCO versus supply voltage for an inverted based ring oscillators

33 Phase-Locked Loop Based Integrator Phase-locked loops are phase input, phase output systems. However, internally most phase-locked loops perform a conversion to and from voltage or current. The oscillator inside a PLL is either voltage or current controlled, so the phase error must be converted to either a control voltage or current. Fig. 1.2, in the previous chapter, shows a conventional charge pump PLL block diagram. The phase detector (PD) and the charge pump (CP) convert the phase error between the input and feedback clocks to a current. The loop filter (LF) then converts the current to a voltage. This control voltage adjusts the frequency of the VCO to align the feedback phase with the input. In a ring oscillator integrator, phase detectors and charge pumps can also be used to perform a phase to current conversion as shown in Fig If the conventional PLL topology is rearranged, a current mode integrator can be realized. The input is fed directly to the CCO, which integrates the signal and produces an output phase. The output phase is compared against a reference and then the phase error is fed into a charge pump to produce an output current. Figure 2.6: A single ended current mode oscillator based integrator

34 20 By avoiding voltage domain signals, the only pole in the ideal model is the integrator pole. There are also no nodes that require large voltage swings. The linear model of this circuit is shown in Figure 2.7: Figure 2.7: A single ended current mode oscillator based integrator From the linear model, the integrator s transfer function is: H(s) = K CCOK P D I CP s (2.6) From the transfer function, it can be seen that this topology mimics the operation of a single-stage opamp with infinite DC gain. There is only one pole so no compensation is required to achieve a high phase margin. While this topology performs the integration function, it still has several issues that must be resolved before it can be used easily: The phase detector s output is a pulse-width modulated (PWM) signal. This will cause the output current to also be a PWM current instead of an analog current. The phase detector has a limited linear range. If the phase error exceeds that range, the integrator will stop functioning properly. If there is a static

35 21 frequency error between the CCO and reference clock, a phase error will accumulate and can eventually overflow the phase detector. The circuit is only single-ended. A differential version of this integrator could improve linearity and noise performance. It is not clear how this integrator can be put in feedback, which is required for use in analog filters or continuous time delta-sigma ADCs. In the following sections, each of these issues will be discussed in more detail and a solution will be proposed. 2.3 A Differential Ring Oscillator Integrator Differential circuits have a number of advantages over similar single ended topologies. If the circuit is truly symmetric, then the even order terms in the circuits transfer characteristic will be cancelled. This can eliminate the even order harmonics, greatly improving linearity. For opamps, the SNR can be improved as the differential output allows a quadrupling of the signal power at the output with only a doubling of the noise. Clearly there are advantages to using a differential topology. At this time, a truly differential ring oscillator integrator has not yet been developed. The quantizer used in [4] had a differential input, but the two inputs were not symmetric so an improvement in linearity is not guaranteed. The simplest approach to creating a differential circuit is to duplicate the integrator and add

36 22 the negative signal the 2nd integrator as shown in Fig. 2.8: Figure 2.8: A differential current mode oscillator based integrator Because this circuit does not have any inherent common mode rejection, it is pseudo differential. The common mode of the input is integrated along with the differential mode. It still enjoys the improvement in linearity as long as the positive and negative signal paths are matched. Fig. 2.9 demonstrates this improvement in linearity. This plot uses a pair of oscillators while Fig. 2.5 shows the same plots for only a single oscillator. The differential topology makes K V CO and K CCO even functions, so any odd terms in the single ended plots are removed. Because the linear term is usually the largest, its removal significantly reduces the variation in the oscillator gains as shown in the plot. Before moving on, there are several important points that this topology demonstrates. First, PLLs and the oscillators they utilize are inherently single-ended circuits. In clock generation, only the absolute frequency matters, not frequency

37 23 Figure 2.9: Simulated K V CO and K CCO versus supply voltage for a pair of inverted based ring oscillators or phase differences. However, phase detectors can measure phase differences, even if the frequency of both input clocks varies with time. This allows oscillators to be used in a pseudo differential fashion with the output being the phase difference between the oscillators, not the absolute phase. The second point is that this circuit s linear model remains unchanged from the single ended case. Each half of the integrator operates on half the differential input signal and creates half the differential output signal. The transfer function still matches equation 2.6.

38 Phase Detectors in the Integrator In both conventional charge pump PLLs (CPPLLs) and oscillator-based integrators, the combination of charge pumps and phase detectors performs phase-tocurrent conversion. For the PLL linear model, the two blocks are incorrectly assumed to convert a continuous phase to a continuous current. First, the phase detector only measures phase errors once (or maybe twice) each clock cycle. This leads to the commonly stated requirement that the PLL bandwidth must be 1/10 of the reference frequency. Second, the charge pump current is pulse width modulated. This leads to the issues of control voltage ripple and reference spurs. If these limitations of the linear model cause design challenges with PLLs, their effect on the performance of an oscillator based integrator should also be understood. The first issue, the sampled nature of phase detector, could also limit the performance of the integrator. The proposed topology is just a rearranged PLL, and just like in a PLL, the 1/10 bandwidth to reference frequency requirement still applies. It is important to realize that this requirement means: the bandwidth of the integrator must be less than 1/10 the rate at which phase is compared. The second issue is closely related to the first. The sampled nature of the phase detection prevents the output from being a continuous voltage or current. Instead, it is usually a PWM voltage. Let us consider the XOR gate, the simplest linear phase detector, as an example. A typical configuration of an XOR gate as a phase detector is shown in Fig The output is labeled D out because the output is a PWM waveform where the

39 25 Figure 2.10: An XOR gate used as a phase detector information is carried in its duty ratio (d) rather than in the analog voltage of the signal. The XOR gate will produce a 50% duty ratio when the inputs are out of phase by π/2 radians (90 ) as shown in the Fig Figure 2.11: The output of an XOR phase detector with a phase error of pi/2 The XOR function produces a 0 when both waveforms are either high or low. If only one input is high, it produces a 1. The result is that, at a phase error of π/2, the output goes high after an edge, either rising or falling, of φ 1. The output goes low after an edge on φ 2. So if the φ 1 waveform is shifted so its edges come earlier, the duty cycle will increase. The duty cycle will also increase if the φ 2 waveform is shifted so its edges come later. The duty cycle will decrease if φ 1 edges come later or φ 2 edges come sooner. Any change in phase error will cause a linear change in

40 26 the duty cycle. An example of this behavior is shown in Fig Figure 2.12: The output of an XOR phase detector with a phase error of pi/4 (top) and pi/4 (bottom) overlaid an output with a phase error of pi/2 If the XOR phase detector is analyzed in more detail, it can be determined that the linear range of the phase detector is from a phase error of 0 to π radians. Within that range, the phase error is proportional to the duty cycle of the output. From a phase error of π to 2π radians, the phase error is also proportional to the duty cycle, but the sign of the proportionality constant is opposite as shown in Fig When choosing a phase detector for an oscillator-based integrator, there are three important characteristics of the PD to consider:

41 27 Figure 2.13: The transfer characteristic of an XOR phase detector The rate at which phase is compared The linear range The phase detector gain (K P D ) The rate at which phase is compared sets a limit on the maximum bandwidth of the integrator. The linear range sets a maximum phase swing for the oscillators in the integrators. Lastly, the gain is required for determining the transfer function of the integrator. For the XOR gate, the phase is compared twice every clock cycle (as opposed to once which was assumed for the 1/10 requirement). The linear range is 0 to π and the PD gain (in duty cycle per radian) is 1/π. The performance of the XOR PD versus other PDs will be discussed later in the paper when the circuit level implementation is discussed. There are two points to take away from this discussion: First, a PD is only linear over a certain range and has nonlinearities that will affect the circuit performance. Second, a PD is a phase-to-duty cycle converter that only measures the phase error

42 28 a finite number of times per clock cycle. If the duty cycle is converted directly to current by the charge pumps, that current will also be a PWM signal. It would be preferable to both increase the number of times phase is compared per cycle and make the output current more closely resemble an analog current. 2.5 Multi-Phase Integrators The discussion of phase detectors leads to another modification to the integrator topology: making use of multiple phases. As discussed previously, adding additional phases to a ring oscillator that only burns dynamic power will not degrade its power efficiency. Therefore, generating many phases with a ring oscillator is simply a matter of adding more stages. For example, if the number of stages in a ring oscillator is doubled, the integrator will change in the following ways: The rate at which phase is compared is halved. The oscillator gain will be halved, causing the integrator bandwidth to be halved as well. The oscillators power efficiency remains constant. If the number of stages needs to be doubled, but the oscillator bandwidth needs to remain constant, then the delay cells should be modified. The oscillators period can be calculated by equation 2.5. To keep the period (and thus the frequency) constant when M is doubled, t dc (the delay cells delay) needs to be halved. This can usually be done by decreasing

43 29 transistor lengths. Essentially, the number of stages that can be used in an oscillator is only limited by the processs minimum length. Because ring oscillators can easily produce many phases, then these phases can be used by attaching one phase detector and charge pump per phase. A PWM waveform is generated from each phase detection producing multiple PWM phases. A differential oscillator-based integrator using multiple phases is shown in Fig Figure 2.14: A differential current mode oscillator-based integrator using multiple oscillator phases The performance of the integrator is improved in two ways when multiple phases are used: The phase error is detected M times more often. The output current is now the sum of multiple PWM signals, which makes it more closely resemble an analog waveform.

44 30 The first point allows the 1/10 requirement on the bandwidth to be bypassed. If a sufficient number of phases are used, the effect of sampling phase should no longer limit the design. The second point allows the effect of the PWM nature of the phase detector output to be largely ignored. This is not intuitively obvious, so a greater discussing of the theory of PWM is required. 2.6 Modeling Multi-Phase PWM Signals To review, pulse width modulation is a two-level modulation scheme where the data is contained in the moving average of the signal. The modulated signal is a square wave with potentially unequal high and low times. The square waves frequency or modulation frequency, f pwm, remains constant, but the ratio of the high time (t H ) and low time (t L ) variest. The sum of the high time and low time must equal the period, which is 1/f pwm. The duty ratio of duty cycle, d, is defined as the ratio of the high time to the period: d = t H T (2.7) The duty ratio can vary from 0 or 0% to 1 or 100%. A duty ratio of 0 would mean the signal was always low, while a duty ratio of 1 would mean the signal is always high. Several example PWM signals with varying duty cycles are shown in Fig The duty ratio is also related to average value of the waveform. For example, if the PWM signal is a voltage waveform, the average voltage over one cycle is:

45 31 Figure 2.15: Example PWM waveforms of different duty ratios V avg = t HV H + t L V L T = dv H + (1 d)v L (2.8) If the average voltage is plotted versus duty ratio, it can be seen that duty ratio and average voltage are linearly related as in Fig Figure 2.16: Plot of average voltage of a PWM waveform versus duty ratio Before discussing mult-phase PWM signals, it is important to discuss the type of pulse-width modulation generated from phase detectors. [7] describes two basic types of PWM: uniform sampling and natural sampling. Uniform sampling re-

46 32 quires the input signal to be sampled and held at a clock frequency of f pwm. This type of PWM generates harmonics of the input signal. The phase detector output is similar to natural sampling PWM, where the input is not sampled before modulation and no extra harmonics are generated (PWM tones are still generated). This is because the oscillator frequency changes continuously. In fact, an ideal oscillator s frequency responds instantly to changes in the control voltage or current. Therefore, changes in the control voltage within a PWM period affects the phase of the oscillator, which causes changes in the output duty cycle. The type of modulation also depends on which edges are affected by changes in the input [7]. For example, in leading edge modulation, the leading or first edge s position in the PWM period moves, but the trailing edge remains fixed. Phase detection between a variable frequency oscillator and a fixed frequency ideal clock results in either leading edge or trailing edge modulation. However, phase detection between two variable frequency oscillators results in modulation of both edges. One consequence of this difference is that single edge modulation only has one noisy edge while dual edge modulation has two noisy edges [7]. However, phase detecting two variable edges doubles the phase detector gain. When the PWM signals are combined with charge pumps, there is no difference in noise performance. Lastly, the term modulation index is defined in [7] to describe the peak-topeak swing in duty ratio. In the oscillator-based integrator, a larger modulation index means greater signal power and better SNR. However, the modulation index cannot exceed one, so the SNR can not be increased indefinitely by increasing the

47 33 modulation index. It is the duty ratio (or the moving average) that carries the signal information. The duty ratio becomes a function of time. If the modulation frequency is filtered out so that only the low frequency components of the waveform remain, the original un-modulated signal can be recovered. To demonstrate this, an example spectrum of a pulse width modulated sine wave is shown in Fig with a modulation index of 0.5 (duty ratio varies from 0.25 to 0.75): Figure 2.17: The spectrum of a pulse width modulated sine wave. The modulation frequency is 20 times the input frequency. Dithering noise is also added. The PWM spectrum has two components: the input signal tone and the modulation tones. The input signal tone can be seen in the previous figure as the lowest frequency spike. It is at the original frequency of 1/20. As expected, filtering out everything above a frequency of 1/20 would result in recovering the original sine

48 34 wave. The remaining tones are caused by the modulation. They appear in groups centered around integer multiples of f pwm. The amplitude of these tones decreases as the frequency increases. If these tones can be removed by some method other than filter, the modulated signal would more closely approximate the original signal. If multiple phases are used, some of the tones can be cancelled. The second phase is produced by comparing the original signal with a second triangular wave that is 180 out of phase with the first. When the second phase is added, the sum of the two phases will have three possible levels and have an effective modulation frequency of 2f pwm. From this argument, it is expected that only tones around even integer multiples of 2f pwm would remain. The total energy in the modulation tones should reduce by move than half, because the frequency and number of levels increased. This means both time and voltage resolution have been increased. As the Figs and 2.19 reveal, the sum of the two PWM phases results in a more sine-like waveform. Only the tones around even multiples of the modulation frequency still exist. If these tones amplitudes are compared with the single phase spectrum, it can be seen that their amplitudes are the same as the corresponding tone in the single phase case. In summary, the effect of pulse width modulation is reduced if multiple phases are used. Because multiple phases are easily generated with a ring oscillator, multiple PWM phases can be generated by comparing multiple phases of the oscillator with a multiple phase reference clock. The PWM signals generated by the phase detectors will be evenly spaced about 360, which is required for cancellation of

49 35 Figure 2.18: The sum of two PWM phases of a sine waves. frequency is 20 times the input frequency. The modulation PWM tones. This technique was used in the PWM generator in [5]. To recover the analog signal as much as possible, the multiple phases are summed in current mode by the charge pumps. In the proposed design, 12 phases were taken for each oscillator. The total output current of the charge pumps closely matches the equivalent demodulated signal because only tones around frequencies of 12f pwm should still exist. The output waveform from using 12 phases is shown in Fig In the simulation in Fig. 2.20, the output waveform now has 13 possible levels. Because the input amplitude is only 0.5, not all of these levels are exercised. However, the voltage between each level has still decreased. The increased number of phases causes the output waveform to more closely match the input sine wave.

50 36 Figure 2.19: The spectrum of two PWM phases of a sine waves. The modulation frequency is 20 times the input frequency. Dithering noise is also added. The spectrum of the sum of the 12 phases in Fig follows the expected result. Tones are only around 12f pwm. In addition to reducing the amount of PWM tones, moving the lowest frequency PWM tones to a higher frequency also makes filtering these tones easier. 2.7 Common Mode Issues In past oscillator-based designs, biasing the oscillator was a design challenge. The oscillator s center frequency needs to be the same as the reference frequency, but it also needs to be allowed to vary. A phase-locked loop can perform this function, but it will prevent the oscillators frequency from varying. This means the oscillator

51 37 Figure 2.20: The sum of 12 PWM phases of a sine waves. The modulation frequency is 20 times the input frequency. must operate in open loop when a signal is applied and biased beforehand. If the temperature changes, the circuit must be shut down and biased again. A technique used in [3] employs a replica oscillator locked to the reference frequency to generate the current bias for the oscillators as shown in Fig For the proposed oscillator-based integrator, biasing can be generated using a similar method. In common mode, the oscillators acts in an open loop manner. The oscillators will also act open loop in differential mode, but feedback networks can be added to close the differential mode loop while leaving the common mode loop open. In this case, no reference is needed and the phase detection is between phases of the two oscillators. Figure 2.23 shows an example topology of this type. However, moving to a differential design allows the differential mode operation

52 38 Figure 2.21: The spectrum of 12 PWM phases of a sine waves. The modulation frequency is 20 times the input frequency. to be separated from the common mode operation. This means a common mode feedback (CMFB) loop can be used to set the common mode frequency. Varying the common mode frequency does not affect the differential mode phase error, so it can operate continuously which removes any biasing issues discussed previously. In Fig. 2.24, CMFB is added. The phase errors from the two phase detectors are added to produce a common mode error signal (D out because it is a combination of PWM signals). Then, this is fed back through charge pumps to produce Icmfb, which is added to the input current at the oscillator. Using the linear model of the circuit, an expression for D out can be determined:

53 39 Figure 2.22: A single-ended ring oscillator-based integrator biased to the reference frequency D cmfb = K P D φ out+ φref + φ out φ ref 2 = K P D ( φout+ + φ out 2 ) φref (2.9) If D cmfb is forced to zero by the feedback, then: φ out+ + φ out 2 = φ ref (2.10) Because frequency is the derivative of phase, this also means: f out+ + f out 2 = f ref (2.11) The sum of the output frequencies is twice the common mode frequency, then f cm equals f ref. The CMFB will attempt to hold the average of the two frequencies at the reference frequency. Just as the CMFB in opamps, it operates continuously but does not interfere with the differential mode operation. As the temperature

54 40 Figure 2.23: A differential integrator with an open loop common mode changes, the CMFB will adjust the current to the oscillators. 2.8 Integrator Bandwidth and Tuning Besides being functional, the integrator needs to have a controllable and tunable bandwidth. The integrator s transfer function is given in 2.6. This leads to a unity gain bandwidth of: ω ugb = K CCO K P D I CP (2.12) Of the three terms, K P D is the only term not easily adjustable by the designer. It is determined by the type of phase detector used. Once a detector topology is chosen, it will not be able to be changed. On the other hand, I CP and K CCO can be altered. K CCO can be changed by adjusting the oscillator s biasing conditions

55 41 Figure 2.24: A differential integrator with a closed loop common mode (and also common mode frequency). I CP can be altered by changing the biasing of the current sources in the charge pump. While I CP and K CCO provide tuning knobs to adjust the bandwidth, it does not help the designer decide how the oscillator should be designed to achieve a particular bandwidth. For example, if I CP is chosen to be very large, then the charge pump may be able to draw all the current away from the oscillator, causing it to shut off. Clearly, this would cause massive distortion. In practice, I CP must be a percentage of the total oscillator current, Iosc, to keep the distortion below a required level. This keeps the oscillator operating in a particular range of frequencies where the linearity is high. This also means if the oscillator current is scaled, then I CP should be also be scaled such that the percentage variation in the oscillator current remains the same. This will keep the

56 42 oscillator nonlinearity constant, too. For cutoff frequency tuning, either I CP or K CCO could be used. However, it is unclear exactly how K CCO changes with the operating frequency of the integrators, so I CP is a better choice. The ability to tune I CP does not require any additional circuitry other than the ability to adjust the bias current to the charge pumps. This tunability does not add any additional nonlinearity as tuning often does in active RC integrators. Although tuning was not implemented on the simulated filter, a possible unity gain bandwidth sensor is discussed in the final section. 2.9 Building Networks of Integrators Integrators are almost never used open loop because they are unstable in the bounded-input bounded-output sense. A small DC input or offset will cause an integrator s output to increase or decrease indefinitely. In real integrators, this will cause the output to saturate or move outside its linear range. In analog filters or delta-sigma ADCs, the integrators must be connected in a configuration that can include both feedback and feedforward paths. An example of such an analog circuit is a biquad, where two integrators are used to produce a biquadratic transfer function. In order to implement a biquad structure with oscillator-based integrators, the outputs of the integrators must be able to be scaled and added with each other. The rearranged integrator has an input and an output in the duty cycle domain. From an implementation perspective, it is relatively easy to perform analog addition

57 43 Figure 2.25: A block diagram of a biquad section. The biquad requires integrators and gain blocks. and subtraction in the current domain. Using this approach, the outputs of the integrators in the biquad shown in Fig will be a multi-phase PWM voltage signal. The gain blocks will represent sets of charge pumps that can convert the voltage PWM signal to current PWM signals with the appropriate gain. Then these currents can be added or subtracted and fed into integrator blocks. Figure 2.26: A first order low pass filter implemented using the proposed integrator topology (shown single ended for simplicity) An example of a first order low pass filter is shown in Fig The oscillator and phase detector have a transfer function of:

58 44 H int (s) = K CCOK P D s (2.13) The closed loop transfer function can be calculated as: H CL (s) = K CP IN K CCOK P D s 1 + K CP F B K CCO K P D s = ( KCP IN K CP F B ) s K CCO K P D K CP F B (2.14) As expected, the transfer function shows this circuit is a first order low pass filter. To simplify the design of integrator networks, an analogy can be made to Gm-C integrators as shown in Fig The combination of the oscillator and phase detector replaces the capacitor. The charge pumps replace the Gm cells. Figure 2.27: Block diagram showing the similarities between the proposed oscillator-based integrator and a Gm-C integrator. Blocks of similar function are shown in the same color. With this analogy, networks of oscillator-based integrators can be built with the same design techniques as for Gm-C integrator networks. However, there is one difference that has been yet to be overcome: Gm-C filters can use capacitive coupling to bypass Gm stages and create biquads with two zeros. From a transfer function perspective, this puts an sc block in parallel with a Gm block, creating a fast path that bypasses the integration. Unfortunately, there is no good method

59 45 of replacing a K CP block with another block that performs differentiation. Some options are discussed later in the paper under future research chapter.

60 46 Chapter 3 Ring Oscillator Modelling and Design Of the major blocks in the integrator, the ring oscillator has the largest impact on the performance. The oscillators are generally the dominant noise contributors and their nonlinearity degrades distortion performance. The oscillators must be designed carefully in order to maximize performance while minimizing power. Before discussing the circuit level implementation of the oscillators in the proposed integrators, it is instructive to analyze the behavior and tradeoffs related to the ring oscillators. 3.1 Oscillator Design Requirements Ring oscillators have long been used in phase locked loops (PLLs) and other frequency synthesizers, and previous analyses focused on these applications. When using ring oscillators as signal processing elements, some of the requirements are same as frequency synthesizers while some differ. Examples of requirements that are common to the two applications are: Wide tuning range Low noise (output referred for PLLs) Low power

61 47 Low supply noise sensitivity In addition to these requirements, using ring oscillators for signal processing also requires: Controllable gain High linearity For frequency synthesizers, the performance is measured at steady state, so oscillator nonlinearity is usually not an issue. Oscillator nonlinearity affects the loop dynamics of the circuit, but unless it causes very large changes in the oscillator gain, it generally has negligable effect on performance metrics such as jitter or phase noise. In signal processing applications, the nonlinearity can distort the signal, which decreases the signal-to-distortion ratio. In the following sections, the relationship between these requirements will be examined. It should be expected that power and noise are inversely proportional, but it is unclear how linearity can be traded off versus noise performance or power consumption. It is also unclear what should be changed within the oscillator to make these tradeoffs. 3.2 Noise in Ring Oscillators Phase is a measure of the random variation in the phase variable at the output of a VCO. Because phase is proportional to time, phase noise is proportional to timing noise. This allows timing jitter to be calculated from phase noise.

62 48 The output phase noise of ring oscillators has been analyzed in a number of papers including [6] and [8]. For most CMOS oscillators, the phase noise has two major regions. At low frequencies, the phase noise rolls off at a rate of 30 db/decade. At higher frequencies, the phase noise changes to a 20 db/decade roll off. In most cases, a white noise region exists at very high frequencies. An example phase noise plot is shown in Fig Figure 3.1: An example oscillator phase noise plot While this noise profile may appear substantially different from opamps, it is in fact actually very similar. The phase noise is the output-referred noise of the oscillator measured in the phase domain. If an opamp had infinite DC gain, the output referred noise profiles would have the same shape. In both cases, white noise and 1/f noise sources are being integrated adding a 20 db/decade roll off. If the phase noise is input referred, altering it to voltage noise, it becomes white with a 10 db/decade roll off at low frequencies due to 1/f noise.

63 Jitter Versus Phase Noise Jitter and phase noise are often used interchangeably. Lower phase noise means lower timing jitter and vice versa. However, there are several important differences. First, jitter is related to time, not phase. Second, jitter is a time measurement, so it is not dependent on the clock frequency. When a clock is passed through an ideal (no noise) divider, the phase noise decreases by 6 db, but the jitter remains the same. The formula for converting phase noise to jitter (Equation 3.1) also reveals this. T j = 0 S φ df 2πf (3.1) The numerator calculates the amplitude of the phase variation, and then is divided by the angular frequency to convert from phase to time amplitude. The conclusion from what is discussed here should be the following: time noise should be used to compare ring oscillators, not phase noise. The following formula is an oscillation frequency independent measure of noise efficiency of an oscillator: P owerefficiency = 0 S t df P = 0 S φ df (2 π f) 2 P (3.2) If power efficiency is used to compare the noise performance of oscillators, it should be independent of the oscillation frequency and the power consumption. Sending the output through a divider will not change an oscillator s power efficiency. However, the number of delay cells, the delay cell topology, and the

64 50 operating point of the oscillator may still affect the noise performance Effect of Ring Length on Noise Performance Altering the number of stages in an oscillator performs a function similar to a divider. [8] showed that jitter in ring oscillators is independent of the number of stages. This can be explained by the fact that two oscillators with the same delay stages with the same input will have the same number of stage transitions in a given period of time. Because jitter is accumulated with each transition, the total jitter accumulated should be the same. If the jitter is unaffected by the number of delay stages, then the phase noise should be inversely proportional to the ring length. Longer rings have lower frequencies, which means the same jitter produces less phase noise. Simulation comfirms this. The decrease in frequency by adding stages cancels the improvement in phase noise to result in the same jitter. So doubling the number of stages is equivalent to dividing the output clock by 2x from a phase noise perspective. However, the number of stages can affect the power efficiency. This depends on how the power consumption of the oscillator changes with the number of stages. For an oscillator that draws only dynamic power, the power consumption can be estimated as: P = MfC DC V 2 (3.3) If equation 2.5 is used to substitute for the oscillation frequency, f, then the

65 51 power consumption becomes: P = MC DCV 2 Mt DC = C DCV 2 t DC (3.4) Even as M varies, the total power consumption remains unchanged. This means for oscillators that draw dynamic power, the number of stages does not affect power consumption. Because the number of stages also does not affect jitter, the power efficiency is also not affected. A different result occurs for oscillators that draw static current. The power consumption is: P = MI DC (3.5) Here the power consumption is proportional to the number of delay cells. This means the power efficiency of this class of oscillators is inversely proportional to the number of delay cells. An explanation for this is that all of the delay cells draw power, even when they are idle and not involved in switching. To reiterate these findings: Dynamic power oscillators power efficiency is unaffected by the number of stages. Static power oscillators power efficiency is inversely proportional to the number of stages. The previous conclusions are extremely important when considering ring oscillator-

66 52 based designs that require multiple phases. Static power oscillators are most efficient when a small number of delay elements are used. This means there is a loss in performance when a large number of delay cells is used. Therefore, for the proposed integrator topology, static power delay cells should be avoided. 3.3 Frequency and Voltage Gain of Inverter-Based Oscillators Inverter-based ring oscillators generally have high power efficiencies due to large swings and consuming mainly dynamic power. Fig. 3.2 below shows a simple ring oscillator which is controlled by altering its supply voltage, V. This configuration is used in the proposed integrator topology. For small signal analysis, the oscillator can be represented as a resistor. Figure 3.2: An inverter-based ring oscillator and its small signal model The first question is: what it the oscillator s gain (either K V CO or K CCO )? [6] used a model of current source charging a capacitor, but this leads to a very nonlinear voltage to frequency characteristic. Simulation shows that K V CO is actually more linear than predicted in this analysis. An alternative is to assume that the

67 53 transistors in the inverter delay cell act as resistors as shown in Fig The delay t DC now results from the RC time constant of the inverter. Figure 3.3: An inverter delay cell model that assumes the delay is caused by RC settling The load capacitance of each stage is the input capacitance of the next stage plus any extra capacitance due to parasitics or additional circuitry attached to the oscillator. This total capacitance is denoted as C DC, or the delay cell capacitance. The resistors can be approximated as being proportional to the on resistances of the MOSFETs when V DS is 0. This should be a decent approximation for showing the relationships between quantities, but cannot be used to accurately predict the oscillator s frequency. If the MOSFETs are assumed to be square law devices, then the on resistance is:

68 54 The g m in equation R on = µc ox W 1 (V L GS V T ) = 1 (3.6) g m 3.7 is the equivalent saturation transconductance. This leads to the following relationship for the stage delay: t DC C DC g m (3.7) From equation 2.5, a proportional relationship for the oscillation frequency can be derived: f g m = µc W ox (V V L T ) (3.8) MC DC MC DC This analysis shows that the oscillation frequency is proportional to V, which is the voltage across the oscillator. This means that a purely square law analysis predicts a constant K V CO and a perfectly linear VCO. In addition, C DC can be approximated as being proportional to the gate capacitance of the MOSFETs in triode: W LC ox. Equation 3.8 is then modified to become: f µ(v V T ) ML 2 (3.9) The result is that the frequency can be modified by only five quantities: The mobility of the devices The threshold voltage of the devices

69 55 The lengths of the devices The number of stages The voltage across the oscillator Mobility and threshold voltages are difficult to change, but the designer can choose the device lengths, the number of stages, and the voltage operating point. Because K V CO is the derivative of the frequency with respect to the control voltage, a relationship can be derived for it: K V CO µ ML 2 (3.10) The conclusion of this analysis is that a square law model predicts an oscillator with the following relationship: f = K V CO (V V O ) (3.11) In this case, V O is the voltage at which the oscillator begins to oscillate. From equation 3.9, it is expected this voltage is approximately equal to the threshold voltage of the devices. While, K V CO is clearly not linear, it provides a decent approximation for deriving several other relationships.

70 3.4 Current and Power Relationships in Inverter-Based Oscillators 56 When a delay stage has a rising edge, it draws power from the supply. Any capacitance at the switching node must be charged. For each clock period, the power drawn by the oscillator is given by equation 3.3. Because P = IV, the current drawn by the oscillator is: I = MfC DC V (3.12) Equation 3.11 can be used to replace f or V, resulting in the following relationships: ( ) f I = K V CO MC DC V (V V O ) = MfC DC + V O K V CO (3.13) Clearly, the oscillator current has a nonlinear relationship with both frequency and voltage. This means the small signal resistance of the oscillator will change at different operating points. The following plot of a simulated oscillator shows that the voltage to current conversion is much less linear than the voltage to frequency conversion, which implies that the current to frequency conversion will also be nonlinear. The oscillator resistance is the derivative of the voltage across the oscillator with respect to the oscillator current. The first step in deriving an expression for the resistance is to differentiate the relationship between current and voltage.

71 57 di dv = K V COMC DC (2V V O ) = 1 R (3.14) Then the reciprocal of equation 3.14 is taken to find the small signal resistance: R = 1 K V CO MC DC (2V V O ) (3.15) As expected, the oscillator appears as a nonlinear small-signal resistor. In a case with no frequency variation, the result would have been the same as a switched capacitor resistor. The last and perhaps most important relationship for the oscillator-based integrator is the current gain. This is also expected to vary with input current even if the voltage gain is constant. This can be found using the following relationship: K CCO = df di = df dv This leads to an expression for K CCO : dv di = K V COR (3.16) K CCO = 1 MC DC (2V V O ) (3.17) This result is noteworthy because the current gain is not dependent on any device parameters except for the delay cell capacitance. Because this capacitance is created from MOSFET parasitic capacitances, it is related to the size of the devices, but not the mobility. From this analysis, there are several important conclusions:

72 58 K CCO will not be constant even if K V CO is. The small-signal resistance is also variable. This is equivalent to saying the oscillator is a nonlinear resistor. 3.5 Linearity and Distortion Before beginning to estimate distortion generated by the oscillator s nonlinearity, there are two important assumptions. First, the nonlinear terms should be significantly less than the fundamental or the equations used will not be accurate. Second, the nonlinearity should be soft so that small signals see a more linear transfer characteristic. This second assumption also must be true for small-signal analysis to be a valid estimate. The first step in estimating distortion is to approximate the transfer characteristic as a polynomial. The origin should be around the point which the input sine wave will vary about. From this point, [9] gives equations for determining the ratio of the 2nd and 3rd harmonics to the fundamental (HD 2 and HD 3 ): HD 2 = a 2 2a 1 U (3.18) HD 3 = a 3 4a 1 U 2 (3.19) The a-terms are the polynomial coefficients and U is the input signal amplitude. These equations demonstrate two important trade-offs:

73 59 Every 6 db increase in the input swing increases HD 2 by 6 db. Every 6 db increase in the input swing increases HD 3 by 12 db. Because input swing plays a large role in noise performance, a better signalto-noise ratio (SNR) can be traded for a lower signal-to-distortion ratio (SDR) or vice versa. So for a differential circuit where HD 3 is dominant, SNR can be traded off for SDR at a rate of one to two (in decibels). For an oscillator, the nonlinearity is in the voltage to frequency or current to frequency conversion. This makes the nonlinearity appear at the input of the oscillator because it is the input swing that determines how much nonlinearity is exercised. At the output of the oscillator, the variable is phase. Phase has no limits to its value (without a phase detector), so there is no output nonlinearity in the oscillator. In the proposed integrator, the phase detector can add nonlinearity if its linear range is exceeded. This is an important difference from opamps. Opamps have both input and output nonlinearity. The input nonlinearity is caused by the nonlinear voltage to current transfer characteristics of the input transistors. The output nonlinearity is caused the current to voltage transfer characteristic, which is due to nonlinear transistor output resistances. Output nonlinearities are dependent on the output swing and are not affected by only reducing the input swings. In chapter five, when nonlinearity is examined more closely, it will be shown that input nonlinearity is usually easier to mitigate compared to output nonlinearity. To predict the distortion produced by the oscillator, simulation is used. The

74 60 complex operation of the transistors in the oscillator make estimating the nonlinearity impossible using the simplistic analysis described in the last two sections. Once one simulation is completed and the size of HD 3 recorded, the distortion can be estimated when varying the input amplitude using the rules mentioned above. In the proposed integrator, the input amplitude is set by the size of the input charge pumps and the modulation index. Larger charge pumps allow for a larger current swing, which results in a larger frequency swing. The modulation index is the peak-to-peak duty ratio swing. Theoretically, this can be as large as one, but in real circuits nonlinearity will be introduced when the duty ratio is near zero or one. As a result, the modulation index must be smaller than one, which means only a percentage of the maximum charge pump current swing will be used. While both of these knobs can adjust the input swing, which can be used to modify the distortion produced by the oscillator, it also modifies the SNR of the integrator. 3.6 Delay Cell Topology For dynamic power only ring oscillators, the only design choices that affect the power efficiency is the delay cell topology and the operating point. The delay cell topology has the largest impact on power efficiency. Besides having good noise performance, a high K V CO is desired. An oscillator with higher K V CO will allow a smaller change in the voltage for the same change in frequency, which improves linearity. The larger gain also causes the phase noise, which is output referred, to appear smaller when input referred.

75 61 A basic CMOS inverter ring is the simplest and, from simulation, the most power efficient oscillator that can be controlled from its supply. Its downside is that it limits the ring to an odd number of phases, so complementary phases are not available. It is preferable to have complementary stages to make level shifting and phase detection easier. If a differential ring oscillator is required, there are two delay cell topologies that have been used in past designs: Pseudo differential inverters with feedback latch Pseudo differential inverters with feedforward resistors Simulation showed that the feedforward topology used in [10] is more power efficient than latch based delay cells. In feedback, the main inverters must overcome the latches to switch a delay cell. The contention causes extra power consumption while both the latch and inverter are contributing noise. The feedforward topology avoids that problem. Instead, the feedforward paths should just be large enough to ensure that the oscillator does not latch up, so they should not reduce the power efficiency greatly. The cross-coupled feedforward resistors are implemented with transmission gates. This allows the feedforward resistance to vary with R on of the main inverters, which reduces the chance that the oscillator will latch up at a corner due to the resistors becoming too strong or too weak. A schematic of the delay cell is shown in Fig. 3.4.

76 62 Figure 3.4: Schematic of the differential delay cell used in the proposed integrator s oscillators. 3.7 Design of the Integrator Ring Oscillators Given the chosen delay cell topology, there are still several design knobs within the delay cell: Ratio of inverter size to resistor size Ratio of PMOS size to NMOS size Transistor lengths Transistor widths The first two items do not have a large impact on performance unless a very poor design choice is made. The inverters are chosen to have widths twice as large

77 63 as the resistors to ensure that the inverter is stronger, but also that the resistors are large enough to ensure that the oscillator does not latch up. The PMOS are also chosen to be twice as large as NMOS, because in the process used this approximately balances their on resistances Choosing Transistor Lengths The transistor lengths are a more challenging design choice. Although lengths do not have a significant effect on power efficiency calculated from thermal noise, larger length transistors have reduced flicker noise, which makes using a few slow stages appealing (assuming enough phases are available for the multiple phase integrator). From equation 3.9, length has a large impact on the oscillator frequency. Because f and K V CO are approximately proportional, equation 3.10 shows that the length also impacts K V CO. Given that a minimum number of phases are required, there is a maximum delay cell length that can achieve a chosen K V CO and provide that many phases. However, choosing the largest acceptable length can lead to slow rise times that add extra delay and affect the performance of the phase detectors following the oscillator. If each delay stage with the largest possible length is replaced with more than one delay stage using smaller lengths, then the same delay, frequency, and oscillator gain is achieved, but with faster rise times. A tradeoff must be made between rise times and flicker noise. For simplicity, the transmission gates and the inverters use the same length transistors.

78 Choosing Transistor Widths Transistor widths have very little effect on power efficiency, but can be used to scale the oscillator s noise. It also has minimal effect on K V CO and the oscillation frequency as shown by equations 3.9 and If the widths are doubled, the capacitances are twices as large, which means twice as much charge is used each cycle. The result is that the power consumption doubles, but the noise power is cut in half. This means scaling widths in an oscillator is very similar to scaling widths in an opamp (if the bandwidth is kept constant). Larger widths mean more power consumption and less noise. This allows integrators to be scaled according to their noise transfer functions. If the integrator s noise is suppressed to some degree by the circuit, then smaller widths can be used and power can be saved. Scaling of the charge pumps is also required, but it does provide the designer a degree of freedom. To ensure that the oscillators match each other, the same delay cell topology is used with the same length transistors. The only difference is the transistor widths Choosing the Number of Stages The final step in the oscillator design is to choose the number of delay stages. This choice already had to be made when choosing the lengths so that the final K V CO is appropriate. In the simulated filter design, 24 stage oscillators were used. Each stage produces two phases, which means 48 phases were available. Only 24 of those phases were used. The phase detectors require complementary pairs of phases, so

79 65 there are 12 phase detectors using two phases each. 3.8 Oscillator Bandwidth and Parasitic Pole In phase domain analysis for PLLs, VCOs are treated as an ideal integrator. This assumes that the voltage to frequency or current to frequency transfer characteristic is instantaneous. In reality, capacitances cause poles that limit the oscillator s bandwidth. It has already been mentioned that an inverter-based ring oscillator functions similar to a switched capacitor resistor. Looking from either supply, the oscillator appears as both a resistor and a capacitor as shown in Fig Figure 3.5: Small signal model of the proposed integrator. The oscillator is modeled as both a resistor and a capacitor.

80 66 Even ignoring all other parasitic capacitances and resistances, there will be a second pole: ω p2 = 1 R osc C osc (3.20) The majority of the parasitic capacitance is the capacitance at the output of the delay cells being connected to the supply. At any given time in a differential (even number of phases) oscillator, half of the delay cell outputs are connected to the supply. In other words, the PMOS transistors are low resistance effectively shorting their output to their supply. This leads to the following estimate for the oscillators total capacitance looking from either ground or the supply: C osc = MC DC (3.21) There is no half factor because the number of delay cells is M and a capacitance from each delay cell is connected to either the supply or ground at any given time. If the previous equation is combined with equation 3.15 and 3.20, then a new expression for the oscillator s second pole can be derived: ω p2 = K V CO (2V V O ) (3.22) This result shows an important conclusion: the parasitic pole scales with K V CO. Because K V CO is approximately proportional to both the common mode frequency and the oscillator bandwidth, the second pole will scale with the oscillator bandwidth. This has both negative and positive effects. As a positive effect, the scaling

81 67 will allow this pole to move to higher frequencies when higher bandwidth oscillators are used in higher frequency designs. The negative is that the pole will always cause some degradation in the phase of the integrator, which must be compensated for in most designs. This pole is usually three to ten times the unity gain bandwidth of the integrator, which causes significant phase shift. The only knob to vary the ratio of the second pole to K V CO is the second term of equation 3.22, (2V V O ). However, the designer is limited in changing this quantity because increasing the voltage increases the operating frequency, which results in more power consumption in phase detectors and charge pumps. It also increases the voltage across the oscillator, which can be a problem for some low supply designs.

82 68 Chapter 4 Ring Oscillator-Based Integrator Circuit Level Design After having described how the ring oscillator-based integrator works at a conceptual level, the actual circuit implementation must be developed. There are four basic blocks that must be designed for the integrator: Ring Oscillator Phase Detector Charge Pump Oscillator Buffer/Level Shifter The previous chapter discussed the design of the ring oscillators in the integrators. In this section, the design choices and trade-offs of each of the remaining blocks will be discussed. 4.1 Phase Detector Design The phase detectors used in the integrators have two main requirements: Low power High linearity (in the full scale range)

83 69 Because the phase detector is essentially a digital block, low power means less capacitance switching each clock cycle. This results in two conclusions: the phase detectors should use minimum size devices and a simple topology will most likely result in the lowest power. Three main types of phase detectors are used in PLLs: Three-state phase-frequency detectors (PFD) Two-state phase detector XOR phase detector In PLLs, three-state PFDs are the most commonly used because they capture large frequency errors and also are designed to keep the pulse-widths as small as possible. When the phase error is zero, which is the middle of a three-state PFDs linear range, it outputs two short pulses. When the phase error is less than zero, the up outputs pulse widths increases. When the phase error is more than zero, the down outputs pulse width increases. This can reduce the amount of time the charge pumps are on when a PLL is locked and thus reduce charge pump noise. In the oscillator-based integrator, the fact that the operation of the PFD changes in the middle of its linear range can lead to degraded linearity. For example, mismatches in charge pump currents can cause the gain of the PFD and charge pump combination to be different whether the phase error is positive or negative. In addition, the three-state PFD is a more complicated circuit and will usually draw more power than simple phase detectors.

84 70 Table 4.1: Comparison table of XOR and two-state phase detectors. Linear Range Lock Point Gain Output Frequency Two-State 2π π 1 XOR π π 2 2π 1 π f in 2f in The remaining two options are phase only detectors. They both output only a single PWM signal, which means the center of the linear range is a 50% duty cycle. Table 4.1 gives a comparison between the two phase detectors. The main difference between the two phase detectors is that there is an effective clock division by 2 between the XOR PD and the two-state PD. This results in the two-state PD having half the gain and output frequency of the XOR PD. A lower output frequency will reduce the power consumed in switching the charge pumps, but it comes with a 2x reduction in gain. The best method for counteracting this decrease in gain is to halve the number of stages in the oscillator. The end result would be that the output frequency and gain would remain constant. One possible benefit of using a two-state phase detector is that an oscillator with half as many stages would consume less area. Another benefit is that the lower gain allows the bandwidth of the integrator to be 2x smaller compared to the second pole. This reduces the phase shift that must be compensated for. However, another significant consideration is power consumption. Typically, two-state PDs are implemented as a combination of two flip-flops and an XOR gate, which forms a set-reset flip-flop, as shown in Fig. 4.1: If complementary outputs are preferred, two XOR gates are needed to produce the two output signals. An XOR phase detector requires only the XOR gates,

85 71 Figure 4.1: One implementation of a two-state phase detector (SR flip-flop). so a two-state PD requires an additional two flip-flops. Comparable designs will have the same output frequency, so the XOR PD is lower power. The question is whether the second pole or the power consumption is a greater problem. In the proposed design, the oscillators phases are compared with each other, so the gain of the integrator is double compared to when they are compared with a reference. This means the second pole is a greater problem and a two-state phase detector must be used. Both phase detector designs rely on CMOS XOR gates. Fig. 4.2 shows two implementations of an XOR gate. The asymmetric case has different rise and fall times for each input, so the symmetric version is preferred to ensure that each input is treated identically. The symmetric version uses twice as many transistors, but those transistors can be half the size. The second XOR gate (really an XNOR

86 72 Figure 4.2: Asymmetric and symmetric implementations of a CMOS XOR gate. gate) to produce the complementary output can be implemented by switching the complementary phases for one of the two inputs. For example, a and a n can be swapped. 4.2 Charge Pump Design The charge pumps used in this design must convert a digital PWM voltage waveform into a PWM current waveform. Because the topology uses multiple PWM phases, the combined output currents from a set of charge pumps will resemble an analog waveform as described in the discussion on multiple phase PWM signals. Because charge pumps are implemented by switching currents, the transfer

87 73 characteristic of a charge pump should be very linear if properly designed. The higher the percentage of the time that the current source is on, the higher the average output current. The entire topology relies on highly linear charge pumps. The charge pumps form the feedback networks, which sets the low frequency linearity for the circuit. Ideally, the charge pumps would instantly transition from no current to their on current. In reality, the transition will take a finite time. In addition, glitches may occur. Both of these effects can potentially degrade the charge pump transfer function linearity. Also, low output resistances in the charge pumps can reduce linearity in a manner similar to current DACs. In general, these are the traits that are desired in a charge pump topology: Fast transition time No glitches Low power consumption Good matching (for current accuracy) High output resistance Linearity and Distortion Issues The charge pumps are required to be highly linear because they limit the maximum linearity of the integrators in feedback. However, the operation of charge pumps

88 74 is inherently linear as it ideally has ownly two operating points (on and off). The average output current, I out is simply the maximum output current, I CP, multiplied by the input duty ratio, d. However, there are several effects than can compromise this high linearity. First, finite rise times and glitches can cause nonlinearity in the duty ratio to current transfer characteristics at very low or high duty ratios. Fig.?? shows an example of this effect. When the current pulse becomes small enough that the current has not completely settled to its final value when another transition occurs, then the average current I out does not change linearly with the input duty ratio. Figure 4.3: Output current waveforms for different input duty ratios from a charge pump with finite rise time. For example, lets assume a charge pump s current transitions linearly as shown in Fig. 4.3 with a percentage of the period called d t. If the input duty ratio is 50%, then the output current will be 0.5I CP because any current lost in a rising edge is cancelled with the current gained in the falling edge. For any case where d in is greater than d t and less than 1 d t, I out still equals di CP. However, when the input duty ratio is outside that range, the charge pump is

89 75 no longer linear. When the duty ratio is less than d t, the duty ratio to current transfer characteristic becomes: I out = d2 ini CP d t (4.1) Clearly, the charge pump should not be used when a pulse width is less than one transition time if high linearity is desired. Realistic charge pumps do not have linear transitions. Rather the transition is more complicated and may settle exponentially near the end. Nonlinearity will occur when a transition comes when the charge pump has not completely settled. If the settling error is small, then the additional distortion will also be small, but it will still limit the charge pump linearity. Charge pumps also often switch with glitches. Because the input of the charge pump is a PWM signal, a rising and falling edge occurs each PWM period. Therefore, a rising and falling edge glitch occurs each period. If extra charge Q rise and Q fall is injected, then the transfer characteristic becomes: I out = d in I CP + f pwm (Q rise + Q fall ) (4.2) As long as Q rise, Q fall, and f pwm are constant, only a constant offset term is added. However, if the pulse widths are short, like the previous discussion, the glitch charge may change with the duty ratio. This leads to degraded linearity. The last issue that may impact linearity is output resistance. Most charge pump topologies off resistances are different than their on resistances. Often this is

90 76 because the charge pump is open circuited when off. For analysis, it is easier to use on conductance, G on, and off conductance, G off. The average output conductance is then calculated by taking the time weighted average of the conductances. G out = d in G on + (1 d in )G off (4.3) If the on and off conductances are not equal, the average conductance will change with the charge pump s input. This conductance appears in parallel with any conductance at the output of the charge pump. For the oscillator-based integrator, this conductance is usually negligable compared to the conductance of the oscillator. Both conductances are nonlinear and the oscillator conductance dominates, so it is the oscillator s nonlinearity that causes the majority of the distortion. However, if the designer is not careful, the charge pumps can also contribute nonlinearity Noise Issues Like any circuit block containing active elements, the charge pumps will contribute noise. In fact, charge pump noise can be compared with conventional Gm blocks that adjust an output current. Assuming the noise is mostly produced by a single MOSFET current source, the noise current is: i 2 n = 4γk B T g m (4.4)

91 77 If the MOSFET is approximately a square law device, then g m is equal to 2I CP /V ov, which allows equation 4.4 to be modified: i 2 n = 8γk BT I CP V ov (4.5) To gain insight into the charge pump design, a relationship needs to be derived to show how the noise performance varies with I CP and V ov. The maximum signal power is I 2 CP /8 (I CP is the peak-to-peak current swing), so an approximate SNR expression can be derived: SNR = I2 CP 8i 2 n = I CP V ov 64γk B T (4.6) Both I CP and V ov appear in the numerator. SNR is expected to scale with I CP, because it is common for noise performance to scale with power consumption. However, increasing V ov does not require any additional power. The conclusion is that the overdrive voltage on the current sources in the charge pump should be increased until headroom becomes a constraint. This is different from amplifiers, where the input transistor needs a high g m, so a smaller overdrive is preferrable for noise Topology and Implementation A wide variety of topologies have been used in PLLs. A simple MOSFET current source can be switched on or off by placing the switches at either the gate, source,

92 78 or drain. This leads to the gate-switched, source-switched, and drain-switched topologies. Another option is to use a differential pair structure. In this topology, the current source is never turned off. Instead, the current is steered in one of two directions. Lastly, the current source can be replaced with a resistor to create a switched-resistor topology. Source-switched charge pumps were ultimately chosen because they can be driven directly with rail-to-rail inputs and they can be single-ended, which is needed for common mode feedback. Differential charge pumps must be driven with smaller input swings if small glitches are desired. Unfortunately, sourceswitched charge pumps have lower output resistance and the current source must be turned on and off. Because switching the current source results in charging and discharging its parasitic capacitances, the length of the transistor is limited to maintain high speed and low power consumption. However, this comes at the cost of matching. The final charge pump design is modified to improve speed and reduce glitching. An additional switch is added to shut the transistor off quickly. The source voltage only needs to change enough to reduce V GS below V T, so the source voltage is only changed by a few hundred millivolts. The schematic of a NMOS and PMOS charge pump is shown in Fig Because the charge pump needs to be scaled to implement different coefficients in a network of integrators, all of the transistor widths can be scaled to generate the desired I out. In the proposed integrator, the biasing current for the oscillators is generated

93 79 Figure 4.4: Schematics of NMOS and PMOS source-switched charge pumps used in the integrator. Lengths that are not given are minimum. Common mode charge pumps use only the NMOS variety. from the common mode feedback charge pumps. These are single-ended NMOS pumps. The differential mode pumps use both NMOS and PMOS. This allows improved noise performance over using NMOS current sources. The same charge pump gain can be produced with half the static current and noise. In addition, either a PMOS or NMOS transistor is always on. This means the variation in the output resistance between the two charge pump states is reduced, which also reduces any potential nonlinearity. Fig. 4.5 shows a typical charge pump linearity curve. The output is the average output current I out. The analog output is generated by having continuous control over the input PWM s duty ratio. This changes the high and low times in an analog manner. The figure demonstrates how linear a charge pump is, although nonlinearity on the level of 60 or 70 db can not be seen in this plot.

94 80 Figure 4.5: Simulated duty ratio to current transfer characteristic of the proposed charge pump topology (25 ua is the maximum current). Fig. 4.6 shows the output waveforms of a 25 µa charge pump. The maximum and minimum duty ratios must be set so that the current has time to stabilize to its final value (when either off or on) before it can be switched again. If this is not done, the charge pump will contribute nonlinearity. This is because I out is the average current delivered during a PWM clock cycle. If the on or off times become too small, I out will not change linearly with the input duty ratio. Because charge pump linearity is used in the feedback network, charge pump nonlinearity will limit the distortion performance at low frequencies for a network of integrators. It is therefore important the linearity be as high as possible.

95 81 Figure 4.6: Simulated charge pump current waveforms for different input duty cycles with a PWM frequency of 200 MHz (50 ua is the maximum current). 4.3 Level Shifter Design One disadvantage of controlling ring oscillators with the delay cell supply voltage is that the output swing of the oscillator changes with the supply. The swing range is also typically much less than the rail-to-rail voltage of the chip. In order for CMOS digital circuits to be used as phase detectors, the phases of the oscillator must be level shifted to rail-to-rail swings. The level shifter topology chosen is a differential topology, which draws no static

96 82 current. Its schematic is shown in Fig By using a differential oscillator, complementary phases are available to the level shifter. Because the oscillator output swing is from V DD to a lower control voltage, PMOS input transistors can be used. However, NMOS can not be used as the oscillator phases never drop to a low enough voltage to turn them off. To deal with this issue, a cross-coupled NMOS latch is used on level shifter s pull down network. An additional NMOS transistor is placed in series with the latching transistors. This transistor s gate is connected to the low swing input. While this transistor may not turn off when the input swings low, its drain to source resistance will increase, which will help break the latch. Figure 4.7: Schematic of the level shifter. All devices are minimum length. The outputs of the cross-coupled latch stage are buffered by inverters. Because

97 83 the latches produce waveforms that do not necessary cross at midrail, the inverter drive strengths are skewed. This helps move the crossover point back towards midrail. Fig. 4.8 shows that the output waveforms cross near midrail even at different process corners. Because the level shifter s delay is small and its noise is not accumulated like the oscillator, the level shifter s noise contribution is negligable. Therefore, the level shifter uses minimum size devices to reduce power consumption. Figure 4.8: Level shifter output waveforms plotted versus time for various process corners.

98 84 Chapter 5 Filter Design Using Ring Oscillator Integrators With the integrators circuit level design complete, the next step is to incorporate the integrators into the filter. Several problems still exist. First, filters are voltageinput and voltage-output circuits. The integrators are PWM-input and PWMoutput circuits. The input and output of the filter must be designed to perform an extra conversion. Second, the filter itself has not been designed. The gain coefficients between the integrators are not known, the oscillators have not been scaled for noise, and the extra phase of the integrators has not been compensated for. Also, the effect on the oscillator nonlinearity has not been accounted for. All of these design issues must be dealt with before an analog filter using ring oscillators can be implemented. 5.1 Improving Integrator Linearity with Resistors For this filter design, two problems still exist with the basic ring oscillator integrator. First, the linearity is not as high as needed. Second, the second pole is at too low of a frequency to compensate easily. One solution to both problems is to add a resistor between the supply nodes of the oscillators as shown in Fig These resistors appear only in the differential mode small-signal circuit in parallel to the oscillators resistances as seen in the small signal model shown in Fig. 5.2.

99 85 Because the nonlinearity is mostly caused by the nonlinearity of Rosc, the parallel combination of the two resistances appears more linear and the linearity of the complete integrator will be improved. This improvement is still limited by K V CO nonlinearity, but not K CCO nonlinearity. Figure 5.1: Ring oscillator based integrator block diagram with linearity improving resistor. Besides improving the linearity, the resistance at the supply node, V in, will be reduced. Because R dm will add very little additional capacitance, the second pole of the oscillator will move to a higher frequency. This reduces the need to compensate for the second pole s phase shift. However, this same effect reduces the oscillator bandwidth by reducing the effective oscillator gain. K CCO is K V CO R osc in the conventional case, so the new integrator transfer function will be (ignoring the 2nd pole):

100 86 Figure 5.2: Small signal model of ring oscillator integrator with linearity improving resistor. The oscillator resistance and added resistance appear in parallel. H(s) = K V CO(R osc R dm 2 )K P D I CP s (5.1) The decrease in bandwidth can be compensated for by increasing I CP. The effect on linearity from adding this resistor is similar to the effect of degeneration as shown in [9]. The linearity improvement from the resistor is greater than the linearity decrease from increasing I CP, so from a purely distortion perspective, adding the resistor improves performance. The effect on noise must also be considered. From an input-referred perspective, the resistor should not affect the contribution from the charge pumps. Adding the resistor will add extra noise, but the signal power can also increase when the charge pump current is scaled to keep the bandwidth the same. If these were the only effects, the SNR would improve if the charge pumps were scaled to keep the bandwidth constant. Unfortunately, the oscillator phase noise actually degrades

101 87 when the resistors are added. The reason for this degradation is not completely understood, but it seems to be related to the resistance of the oscillators supply node. The result is that the oscillator noise becomes the dominant noise source when the resistor is added. As an example, if R dm is chosen to be equal to R osc, the charge pump current must be doubled to keep the integrator bandwidth constant. There is a large decrease in the third harmonic (greater than 10 db), but the SNR of the integrator degrades by about 3 db. 5.2 Performing Input Voltage-to-Current Conversion In the integrator design described in section three, the input to an integrator is a set of charge pumps controlled by a multiple phase PWM signal. For the first integrator in the filter, the input should be a voltage. The oscillators are operated as current controlled oscillators and the subtraction needed for feedback is done in the current domain. What is required is a highly linear voltage-to-current converter block. Fortunately, a resistor can perform such a conversion in a highly linear fashion. If the input charge pumps for the first integrator are replaced with two resistors as shown in Fig. 5.3, then voltage swings on one end of the resistors will cause the current through the resistors to change proportionally. At the other end of the resistor, the voltage is held constant because it is tied to the effective virtual ground of the integrator. The current through the resistor will then be:

102 88 I in = V in R in (5.2) The resistor can then be sized to provide the same range of input currents as the equivalent charge pump. This allows the input charge pump in the standard design to be replaced with an equivalent block. Figure 5.3: Ring oscillator based integrator block diagram with voltage input. The resistors do cause a change in the output resistance at the virtual ground node, which is the same effect that the linearity improving resistors caused. This effect will cause a reduction in the K CCO of the oscillators and cause the first oscillator not to match the others. To ensure the oscillators match each other, resistors must be added to each integrator. Once the resistors are added, the final integrator transfer function becomes:

103 89 I in = K V CO ( Rosc R dm 2 R in ) KP D sr in (5.3) 5.3 Output PWM-to-Voltage Conversion The output of the last integrator is a multiple phase PWM voltage signal. This can easily be converted to a PWM current signal with charge pumps, but in this case it needs to be converted to a voltage. Similar to the input, the conversion can be done in a highly linear fashion using resistors. Charge pumps convert the PWM voltage signal to a current signal, and the current is driven into resistors, which converts the current to voltage. Of course, this requires an additional stage at the output of the filter to perform this conversion. This output stage should be capable of producing large output swings to improve the noise performance. In the proposed prototype, this stage also drives the output off-chip. Source-switched or differential charge pumps can be used in the output stage, but because high output resistance is not required, there is a better alternative. Each PWM phase drives an inverter. A resistor is attached to the output creating a switched resistor charge pump as shown in Fig The resistors both act as part of the charge pump and the current to voltage converter. This topology allows nearly rail-to-rail swing while achieving higher noise performance than other charge pump topologies.

104 90 Figure 5.4: Filter output stage used to convert multi-phase PWM waveforms to an analog voltage. 5.4 Bias/Reference Generation In addition to the main signal path, a bias or reference generator is needed. In the case where common mode feedback is used, a reference clock with multiple phases must be generated to be compared with the phases of the oscillators in the integrators. In the case where no common mode feedback is present, the current sources that control the current to the oscillators must be biased so that the oscillators operate near the intended common mode frequency. Both circuits require a PLL loop to lock a replica oscillator to the appropriate frequency Design Overview Whether CMFB is used or not, the bias or reference generator must lock a replica oscillator to a particular frequency. The conventional charge pump PLL provides a simple method to accomplish this. An FLL can also perform this function because

105 91 the precise phase of the replica does not matter, but designing a frequency detector is a greater challenge than a conventional three-state PFD (phase-frequency detector). Any error in the frequency detector can also cause the loop to lock at the wrong frequency. This circuit has a number of outputs: The biasing voltage for the common mode current sources or charge pumps. The supply voltage of the oscillator. For the reference generator only: reference phases to be compared with integrator phases. The biasing voltage is the voltage that is fed to the common mode current sources (these can be within the charge pumps). With no CMFB, the integrator oscillators should be biased to the same frequency as the replica. With CMFB, the charge pumps should operate at 50 The other two outputs are more straightforward. The oscillator supply voltage is useful for characterizing the process and the oscillators. It can also be used to eliminate most of the V ds mismatch when biasing the differential mode charge pumps. The reference phases are used for phase comparison with the output phases of the integrator oscillators. Ideally, the phases are evenly spaced, but supply voltage ripple and delay stage mismatch can cause different phase spacing.

106 Loop Compensation A CPPLL topology is used, so there are two integrators in the loop which generate two low frequency poles. As with conventional PLLs, a zero must be added to stabilize the loop. Usually, this zero is added by placing a resistor in the loop filter. The charge pump current produces a proportional voltage change across the resistor. However, because this path is proportional to the phase error, a PWM voltage waveform is produced because the charge pump current is a PWM waveform. This creates the majority of control voltage ripple in CPPLLs. For this circuit, ripple can affect the integrators performance. To avoid this issue, there is no loop filter resistor. Instead, a topology similar to [11] is used. The proportional path is created by having a different charge pump directly connected to the oscillator s supply node. This bypasses the pole in the integral charge pump and adds a zero. These charge pumps are also biased with the output bias voltage, so that these charge pumps always control a percentage of the oscillators total current. A block diagram of the bias generator is shown in Fig Block Descriptions The core of both the reference or bias generator is the replica oscillator. Just as all of the integrators use scaled version of the same oscillator topology, the replica also matches the integrator oscillators. When CMFB is used, the integrator oscillators are biased entirely with charge pumps. When no CMFB is used, the oscillators are biased with fixed MOSFET current sources. For the replica, no matter which

107 93 Figure 5.5: Schematic diagram of the bias/reference generator. scheme is used, current sources in combination with the proportional path charge pumps are used for biasing. This is because only a single reference clock phase is given as input, so there are no additional phases with which to compare against. The charge pumps are all a source-switched topology identical to the integrator charge pumps. The proportional path charge pumps are NMOS only, just as any CMFB charge pumps are. The integral path charge pump uses both NMOS and PMOS and is biased from an external reference. The PFD is a typical three state pass transistor design. Its schematic is shown in Fig The reset delay is designed to be long enough to avoid any dead time issues. Because complementary waveforms are needed to operate the charge pumps, an inverter produces the UP and DN signals. After the inverter, a structure similar to the oscillator delay cell aligns the two waveforms using cross-coupled transmission gates. The schematic of the drivers is shown in Fig. 5.7.

108 94 Figure 5.6: Schematic diagram of the phase frequency detector used in the bias generator Simulation Results In the proposed design, no CMFB is used so this block functions only as a bias generator. Phase spacing and jitter are not important, but the oscillator needs to match the integrator oscillators. The main concern is the bandwidth and phase margin of the loop. Fig. 5.8 shows the Bode plots for the circuit at various process corners.

109 95 Figure 5.7: Schematic diagram of the charge pump drivers. Cross-coupled resistors are used to align complementary signals. 5.5 Estimating Filter Nonlinearity The section in chapter three that discussed nonlinearity describes the oscillator s open loop behavior. When a filter is designed from a network of integrators, the linearity of the circuit is affected by the integrator transfer functions and the feedback. Understanding how these things modify the nonlinearity is important to designing an optimal filter Nonlinearity in a Frequency Independent Closed Loop Feedback can be used to improve the linearity of a nonlinear block if the feedback network is linear. In the case of the proposed integrator topology this is true. A charge pump forms the feedback, and it is a very linear duty cycle to current converter. Assuming the feedback is perfectly linear, [9] derives the following equations: HD 2 = a ( ) ( ) 2 1 U 2a T 1 + T (5.4)

110 96 Figure 5.8: Loop gain Bode plots for the bias generator across process and temperature corners. ( HD 3 = 1 a 3 4 a 1 (1 + T ) ( a2 a 1 ) ) 2 ( ) 2 2T U (5.5) (1 + T ) T In these equations, T is the loop gain. If (a 2 /a 1 ) 2 is assumed to be much smaller than a 3 /a 1 and the loop gain is large, then the equations become: HD 2 = a ( 2 1 2a 1 T ) ( ) U T (5.6)

111 97 HD 3 = ( a3 4a 1 T ) ( ) 2 U (5.7) T So, when choosing the loop gain, the following trade-offs apply: Every 6 db increase in the loop gain decreases HD 2 by 12 db. Every 6 db increase in the loop gain decreases HD 3 by 18 db. This shows that increasing loop gain is more effective at improving linearity than decreasing signal swing. However, this still does not provide a system for estimating the linearity of a system where both input amplitude and loop gain are functions of frequency Using Linear Analysis to Estimate Open Loop Distortion The equations for the closed loop distortion terms are derived through a somewhat lengthy process and there is a lack of an intuitive understanding as to why the trade-off from loop gain is different from the trade-off with signal swing. The feedback network cancels a portion of the input signal before going into nonlinear block, which should result in the same improvement in linearity. In response to these limitations, the question is can basic linear analysis be used in combination with the open loop HD2 and HD3 equations? Here is the proposed method: 1. Solve for signal amplitude at all nodes at the input frequency, ω.

112 98 2. Use the open loop distortion equations to calculate the harmonics produced at each nonlinear block. Assume the gain of the distortion block is 1 for the fundamental (a 1 = 1). 3. Use superpositioning and solve for signal amplitudes at the harmonics 2ω and 3ω. The distortion terms calculated in the previous step appear as ideal sources. Figure 5.9 shows the model used for an open loop system. Figure 5.9: Models of a nonlinear open loop system used to calculate distortion.

113 99 When the block has a frequency independent gain, each distortion component is scaled by the same amount. HD 2 and HD 3 at the output are the same as at the input. However, when the gain varies with frequency, HD 2 and HD 3 can be different at the output as the input. For example, an integrator would see a 6 db decrease in HD 2 and a 9 db decrease in HD 3 due to the fact that the integrators gain is lower at high frequencies. The harmonics get filtered more than the fundamental Using Linear Analysis to Estimate Closed Loop Distortion The technique described in the previous section can be applied to closed loop systems as well. The difference is that the signal that produces the distortion is not the input, but the error signal. Figure 5.10 shows a closed loop system with the error voltage v e shown. Figure 5.10: Model of a nonlinear closed loop system for the fundamental frequency. The nonlinearity is assumed to be at the input of the block. The feedback system has an open loop gain of H(j) and a feedback factor of f. The loop gain is given by:

114 100 H LG (jω) = fh(jω) (5.8) For this system, the closed loop gain is: H CL (jω) = fh(jω) 1 + fh(jω) (5.9) The error transfer function can also be easily calculated: V e V in = H e (jω) = fh(jω) (5.10) From this transfer function, the amplitudes of the harmonics can be calculated from the equations 3.18 and V e2 = a ( 2 2a 1 V e3 = a ( 3 4a fh(jω) fh(jω) ) 2 V 2 in (5.11) ) 3 V 3 in (5.12) When the loop gain is large, the nonlinear terms produced are attenuated by the loop gain. This is due to the input to the nonlinear block, V e, which is smaller in amplitude and exercises a smaller portion of the nonlinear transfer characteristic. To determine the nonlinearity at the output of the system, models must be created for the second and third harmonic. These are shown in Fig Notice that in these models, there is no input to the system at the second or third harmonic frequencies. Instead, the distortion produced by the nonlinearity

115 101 Figure 5.11: Model of a nonlinear closed loop system for the second and third harmonic frequencies. is added at the same location as the input signal. From the error node, the fundamental sees the open loop gain, but the distortion sees the closed loop gain. It will be shown that this difference adds the extra 1/T term seen in equations 5.6 and 5.7. From these models, the harmonic amplitudes at the output can be calculated: V out2 = H(2jω) 1 + fh(2jω) V e2 (5.13) V out3 = H(3jω) 1 + fh(3jω) V e3 (5.14) If the equations for the harmonics produced at the error node are combined with the error to output transfer functions and divided by the fundamental frequency s closed loop gain, the final equations for HD 2 and HD 3 are:

116 102 V out2 = V out3 = ( a 2 2a 1 H(jω) ( a 3 4a 1 H(jω) fh(jω) fh(jω) ) ( ) H(2jω) V in (5.15) 1 + fh(2jω) ) 2 ( ) H(3jω) Vin 2 (5.16) 1 + fh(3jω) These equations are valid for frequency dependent gain, unlike the equations derived in [9]. If the loop gain is replaced by T, these equations simplify to equations 5.6 and 5.7. From these equations three effects can modify the closed loop distortion: Loop gain reduces the error signal amplitude, reducing distortion by reducing the amount of nonlinearity that is exercised. Loop gain adds extra linearity because the distortion is fed back. The open loop system s transfer function can affect nonlinearity by scaling the fundamental differently than the harmonics Using Linear Analysis to Estimate Distortion in a Network In a more complicated system where there are multiple nonlinear blocks, this system can still be applied. The process is as follows: 1. Determine the harmonic coefficients for the nonlinear blocks (a 1, a 2, and a 3 ). 2. Determine the amplitudes at all nodes in the system with nonlinearity present at the fundamental frequency.

117 Calculate the distortion produced by each nonlinearity using the open loop equations. 4. Create models for the harmonics of interest. The nonlinearities produces become sources. 5. Calculate the fundamental and harmonic amplitudes at the output and use these amplitudes to calculate HD 2 and HD 3. In the case of oscillator-based integrators, the main nonlinearity is at the input of the oscillator when current is converted to frequency. To determine the SDR, the amplitude at the inputs of the oscillators should be calculated. Then these can be used to calculate the distortion produced. The distortion terms are then multiplied by the transfer function from the input of the oscillator to the output of the system. 5.6 Filter Design Procedure The last section described a method for estimating the linearity of a network of integrators, but other constraints must also be taken into account when designing a filter. For example, the integrators must be scaled for optimal noise performance. The filter coefficients must also be scaled to maximize the swing at the output of each integrator. This section briefly desribes the design steps taken to design a filter utilizing oscillator-based integrators.

118 System Level Design The first step is to create an unscaled filter design. Assuming that the order, type, and topology of the filter is known, the gain coefficients can be synthesized. For this design, a 4th order Butterworth low pass filter is implemented as a cascade of two biquads. The biquad topology was chosen after automating the design process and then comparing the results for a number of topologies. A cascade of biquads had the best combination of noise and linearity performance. The final filter topology is shown in Fig As part of synthesizing the filter, the phase shift caused by the second pole in the integrators must be accounted for. The details of the compensation process are not described in this thesis, but it involves finding the location of the poles when compensated (including extra poles added by the integrator second pole), and then working backwards to find the filter gain coefficients. This technique has been tested through simulation and provided the correct transfer function, assuming that the extra poles do not make implementing the intended filter impossible. At this point, the value of the gain blocks in the filter topology are known, but no limits has been placed on the swing range at the outputs or inputs of the integrators. The input swing is limited to keep the distortion below the required level, but should also be as large as possible to improve noise performance. When an appropriate input swing range is found, the bandwidth of the integrators should be chosen such that a full scale input swing will create a full scale output swing near the filter cutoff frequency. Some adjustment may be necessary to find the

119 105 Figure 5.12: 4th order ring oscillator filter block diagram. Ring oscillator integrators are shown as integrators and charge pump groups are shown as gain blocks. optimal integrator bandwidth. This process ensures that an output swing within the allowable range will not cause an input swing outside of the allowable range. Therefore, only the output swing needs to be dynamically scaled. Also, all of the integrator bandwidths are the same, which allows the oscillators within the integrators to utilize scaled versions of the same delay cell. The output swing is physically limited between a duty ratio of 0 and 1, but

120 106 it should be limited to an even smaller range of duty ratios to avoid short pulse widths. Dynamic range scaling is performed to ensure that the output swing is always within the tolerable range. This requires some modifications of the filter coefficients and can have a significant impact on noise and linearity performance Circuit Level Design The system level design now needs to be converted to actual circuitry. The block themselves have already been designed, but they must be appropriately sized. The first step is to scale the integrator size to optimize the circuit s noise performance. When an integrator is scaled, both the oscillator size and the charge pumps are scaled together. This maintains the same gain coefficients, but reduces noise and increases power consumption. In order to know how to scale the integrators, noise transfer functions are calculated from each integrator to the output and then integrated to compare the integrated noise contributions of each integrator. Integrators with larger noise contributions are scaled larger until the power-noise product for the filter is minimized. With the size of the integrators known, it is also known what the full scale input current swing is. For example, a 1x integrator may have an input current range of 1 ma peak to peak. This is determined by simulation by trading off noise and linearity. Higher swings into the same integrator contribute more nonlinearity but have better SNR. A 2x integrator would then have an input range of 2 ma peak to peak.

121 107 A gain block of value one entering an integrator represents a set of charge pump (or input resistor) that provides the full scale current. Each set of charge pumps has one pump for each of the multi-phase PWM signals, so each pump s current is usually on the order of tens of microamps. The widths are scaled to scale the charge pump appropriately. Once the input resistor current swing is known, their value can also be calculated using 5.2. The last step in the design is to add buffers between the phase detector outputs and the charge pumps. The charge pumps often control large currents, so the charge pump switches are relatively large. The phase detector cannot directly drive these switches without compromising rise and fall times, so inverters are added to keep transistion times low. 5.7 Simulated Performance The low pass filter is implemented in a 90 nm CMOS process. While the maximum supply voltage of the process is 1.2 V, low threshold voltages allow the oscillators to operate at much lower voltages. For this reason, the design is able to operate at a supply of 0.9 V without compromising performance while reducing power consumption. This is especially beneficial for the phase detectors and charge pump drivers that consume dynamic power, but do not have a large impact on noise performance. The simulated performance of the filter is shown in Table 5.1 and the filter s frequency response is shown in Fig The filter is able to achieve 65.1 db

122 108 Table 5.1: Simulated performance summary of the proposed time-based filter Measurement Simulated Result Filter Type Technology Supply Voltage Input Swing Output Swing Power Consumption SNR HD3 4th Order Butterworth LP 90-nm CMOS 0.9 V 1.2 Vpp Differential 1.5 Vpp Differential 16.4 mw 65.1 db (total noise) 72.2 db (inband noise) 85.2 db (in 1 MHz band) MHz SNR total integrated noise and 72.2 db including only inband noise with less than 20 mw of power consumption. At the same time, the HD3 term at 20 MHz full scale input is 75.4 db below the fundamental. The cumulative noise power normalized to a full scale input is shown in Fig Because of the small lengths used in the oscillator, flicker noise dominates into the MHz range. At that point, thermal noise becomes dominant and ultimately contributes the majority of the noise power. The calculated noise power in a 1 MHz band used in the performance tables is calculated from thermal noise only so it can be compared with other filters. The proposed filter is compared against other recent analog filter publications in Table 5.2. Comparatively, the proposed filter achieves a lower power-snr product than all of these state-of-the-art designs. It also operates at a lower supply and

123 109 Figure 5.13: Simulated frequency response of the proposed filter. achieves superior linearity than all comparable designs. One difference is that the other filters used types with sharper roll-off, while this design used a Butterworth topology. However, Chebyshev or Elliptic filters can be designed by changing the filter coefficients and adding feedforward paths to generate zeroes. In fact, the filter implemented in [12] uses no feedforward capacitive paths and can be directly converted to an oscillator-based topology. The output waveform with a full scale 20 MHz input is shown in Figs The spectrum of this waveform is shown in There is no third harmonic, so

124 110 Figure 5.14: Simulated cumulative output noise power versus frequency normalized to a full scale output. an IM3 simulation using input tones of 19 MHz and 20 MHz was conducted. The output spectrum of this simulation is shown in The PWM tones are approximately 16 times the oscillator common mode frequency, which is expected. These tones can easily be filtered out by the filtering of the stages or by adding less precise RC filtering at the output. There are also some additional tones are also present near the band edge. The most likely explanation for these tones is the mixing of the multi-phase PWM signals and the oscillators switching operation. However, these tones are below the -70 db level, but in future

125 111 Table 5.2: Performance comparison with recent low pass filters of similar bandwidth (SNR is measured with noise in 1 MHz band). This Work Order Tech. VDD BW IM3 SNR Power (V) (MHz) (db) (db) (mw) 4 90-nm (20 MHz) [12] um (6 MHz) [13] um (1.5 MHz) [14] um N/A [15] um 1 10 N/A [16] um (3 MHz) [17] um (5 MHz) N/A 20.7 designs more work may need to be done to minimize them.

126 Figure 5.15: Simulated filter differential output waveform for 20 MHz full scale input. 112

127 113 Figure 5.16: Simulated filter differential output spectrum for 20 MHz full scale input. No HD3 is visible, but additional tones are present due to multi-phase PWM currents.

128 Figure 5.17: Simulated filter differential output spectrum for two-tone input (19 MHz and 20 MHz). IM3 tones are visible. 114