ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS
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1 ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS ROBERT BOGDAN STASZEWSKI Texas Instruments PORAS T. BALSARA University of Texas at Dallas WILEY- INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION
2 CONTENTS PREFACE xiii 1 INTRODUCTION Frequency Synthesis / Noise in Oscillators / Frequency Synthesis Techniques / Frequency Synthesizer as an Integral Part of an RF Transceiver / Transmitter / Receiver / Toward Direct Transmitter Modulation / Frequency Synthesizers for Mobile Communications / Integer-N PLL Architecture / Fractional-./V PLL Architecture / Toward an All-Digital PLL Approach / Implementation of an RF Synthesizer / CMOS vs. Traditional RF Process Technologies / Deep-Submicron CMOS / Digitally Intensive Approach / System Integration / 27 VII
3 Vill CONTENTS System Integration Challenges for Deep-Submicron CMOS / 29 2 DIGITALLY CONTROLLED OSCILLATOR 2.1 Varactor in a Deep-Submicron CMOS Process / Fully Digital Control of Oscillating Frequency / LCTank / Oscillator Core / Open-Loop Narrowband Digital-to-Frequency Conversion / Example Implementation / Time-Domain Mathematical Model of a DCO / Summary / 51 3 NORMALIZED DCO 3.1 Oscillator Transfer Function and Gain / DCO Gain Estimation / DCO Gain Normalization / Principle of Synchronously Optimal DCO Tuning Word Retiming / Time Dithering of DCO Tuning Input / Oscillator Tune Time Dithering Principle / Direct Time Dithering of Tuning Input / Update Clock Dithering Scheme / Implementation of PVT and Acquisition DCO Bits / Implementation of Tracking DCO Bits / High-Speed Dithering of Fractional Varactors / Dynamic Element Matching of Varactors / DCO Varactor Rearrangement / Time-Domain Model / Summary / 74 4 ALL-DIGITAL PHASE-LOCKED LOOP 4.1 Phase-Domain Operation / Reference Clock Retiming / Phase Detection / Difference Mode of ADPLL Operation / Integer-Domain Operation / Modulo Arithmetic of the Reference and Variable Phases / Variable-Phase Accumulator (PV Block) / 89
4 CONTENTS ix 4.5 Time-to-Digital Converter / Frequency Reference Edge Estimation / Fractional Error Estimator / Fractional-Division Ratio Compensation / TDC Resolution Effect on Estimated Frequency Resolution / Active Removal of Fractional Spurs Through TDC (Optional) / Frequency Reference Retiming by a DCO Clock / Sense Amplifier-Based Flip-Flop / General Idea of Clock Retiming / Implementation / Time-Deferred Calculation of the Variable Phase (Optional) / Loop Gain Factor / Phase-Error Dynamic Range / Phase-Domain ADPLL Architecture / Close-in Spurs Due to Injection Pulling / PLL Frequency Response / Conversion Between the s- and z-domains / Noise and Error Sources / TDC Resolution Effect on Phase Noise / Phase Noise Due to DCO SA Dithering / Typell ADPLL / PLL Frequency Response of a Type II Loop / Higher-Order ADPLL / PLL Stability Analysis / Nonlinear Differential Term of an ADPLL / Quality Monitoring of an RF Clock / DCO Gain Estimation Using a PLL / Gear Shifting of PLL Gain / Autonomous Gear-Shifting Mechanism / Extended Gear-Shifting Scheme with Zero-Phase Restart / Edge Skipping Dithering Scheme (Optional) / Summary / 155
5 X CONTENTS 5 APPLICATION: ADPLL-BASED TRANSMITTER Direct Frequency Modulation of a DCO / Discrete-Time Frequency Modulation / Hybrid of Predictive/Closed PLL Operation / Effect of FREF/CKR Clock Misalignment / Just-in-Time DCO Gain Calculation / GFSK Pulse Shaping of Transmitter Data / Interpolative Filter Operation / Power Amplifier / Digital Amplitude Modulation / Discrete Pulse-Slimming Control / Regulation of Transmitting Power / Tuning Word Adjustment / Fully Digital Amplitude Control / Going Forward: Polar Transmitter / Generic Modulator / Polar TX Realization / Summary / BEHAVIORAL MODELING AND SIMULATION Simulation Methodology / Digital Blocks / Support of Digital Stream Processing / Random Number Generator / Time-Domain Modeling of DCO Phase Noise / Modeling Oscillator Jitter / Modeling Oscillator Wander / Modeling Oscillator Flicker (1//) Noise / Clock Edge Divider Effects / VHDL Model Realization of a DCO / Support of Physical K oco / Modeling Metastability in Flip-Flops / Simulation Results / Time-Domain Simulations / Frequency-Deviation Simulations / Phase-Domain Simulations of Transmitters / Synthesizer Phase-Noise Simulations / Summary / 212
6 CONTENTS XI 7 IMPLEMENTATION AND EXPERIMENTAL RESULTS DSP and Its RF Interface to DRP / Transmitter Core Implementation / IC Chip / Evaluation Board / Measurement Equipment / GFSK Transmitter Performance / Synthesizer Performance / Synthesizer Switching Transients / DSP-Driven Modulation / Performance Summary / Summary / 227 APPENDIX A: SPURS DUE TO DCO SWITCHING 228 A.l Spurs Due to DCO Modulation / 229 APPENDIX B: GAUSSIAN PULSE-SHAPING FILTER 232 APPENDIX C: VHDL SOURCE CODE 237 C.l DCO Level 2 / 237 C.2 Period-Controlled Oscillator / 239 C.3 Tactical Flip-Flop / 241 C.4 TDC Pseudo-Thermometer Output Decoder / 243 REFERENCES 247 INDEX 253
ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS
ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS ROBERT BOGDAN STASZEWSKI Texas Instruments PORAS T. BALSARA University of Texas at Dallas A JOHN WILEY & SONS, INC., PUBLICATION ALL-DIGITAL FREQUENCY
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