Design and Implementation of High-Speed CMOS Clock and Data Recovery Circuit for Optical Interconnection Applications. Seong-Jun Song. Dec.

Transcription

1 MS Thesis esign and Implementation of High-Speed CMOS Clock and ata Recovery Circuit for Optical Interconnection Applications Seong-Jun Song ec. 20, 2002 oratory, epartment of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST) Seong-Jun Song 1

2 Outline! Introduction! Motivation! Problem efinition! Proposed 1/8-Rate CR! Building Blocks! Measurement Results! Conclusion & Further Works Seong-Jun Song 2

3 Introduction Optical Input ata Noise Corrupted ata Boosted ata Recovered Clock Retimed ata Recovered Clock Pre Amp Post Amp AGC* * AGC : Automatic Gain Control ecision Circuit Clock Recovery Circuit 1:4 EMUX Freq. ivider Network Interface Framer Seong-Jun Song 3

4 Motivation Long-Haul Applications (SONET, Gigabit Ethernet) Short-Haul Applications (Backplane, Chip-to-Chip) III-V, Si Bipolar, SiGe HBT Very high-speed Inherently low noise # High cost # High power consumption # Not compatible with other technologies CMOS Low cost High level of integration Low power consumption # Less speed # High noise The Solution is Novel CR Architecture and Circuit Techniques In CMOS!!! Seong-Jun Song 4

5 Outline! Introduction! Motivation! Problem efinition! Proposed 1/8-Rate CR! Building Blocks! Measurement Results! Conclusion & Further Works Seong-Jun Song 5

6 Generic CR Configuration Clock and ata Recovery (CR) Pre Amp Post Amp AGC ecision Circuit Clock Recovery Circuit 1:4 EMUX Freq. ivider Network Interface Framer Edge Edge etector etector Phase Phase etector etector Loop Loop Filter Filter VCO VCO PLL-Based Clock Recovery Circuit Seong-Jun Song 6

7 Performance Limitation of 0.25-µm CMOS * Max. Oscillation Frequency (GHz) Max. Performance 2GHz (2-Gb/s) A Number of elay Stages elay elay elay Simple VCO * M. Fukaishi, et al., JSSC, ec. 1998! Simulation result for 0.25-µm CMOS differential ring oscillators with resistive loads and isolation buffers Seong-Jun Song 7

8 Substrate Noise Effect of VCO Pre Amp Noise-Sensitive Analog Blocks Post Amp VCO CR 1:4 EMUX Si Substrate VCO Switching Noise Substrate noise voltage f * * M. van Heijningen, et al., JSSC, Aug Seong-Jun Song 8

9 Conventional CR Techniques (1/2)! Full-Rate Clock Technique * # Full-rate clock frequency (4GHz) # Impossible to design VCO * M. Soyuer, et al., JSSC, ec ata CK ! Half-Rate Clock Technique ** # Half-rate clock frequency (2GHz) # Close to performance limitation # ifficult to design VCO ** M. Rau, et al., JSSC, July 1997 ata CK Seong-Jun Song 9

10 Conventional CR Techniques (2/2)! Oversampling Technique * uarter-rate clock frequency (1GHz) Easier to design VCO # Highly clock phase resolution # uantization jitter # Extra decision logic ata CK 0 CK 1 CK * C.-K. Yang, et al., JSSC, May 1998 Seong-Jun Song 10

11 Outline! Introduction! Motivation! Problem efinition! Proposed 1/8-Rate CR! Building Blocks! Measurement Results! Conclusion & Further Works Seong-Jun Song 11

12 Proposed CR Technique! 1/8-Rate Clock Technique * 1/8-rate clock frequency (0.5GHz) Very easy to design VCO No quantization jitter No extra decision logic Can do 1:4 EMUX # Complex design ata CK * S.-J. Song, et al., ESSCIRC, Sept * S.-J. Song, et al., to be published for JSSC, July 2003 CK 1 CK 2 CK 3 Seong-Jun Song 12

13 Proposed 1/8-Rate CR Architecture Conventional Full-Rate CR Proposed 1/8-Rate CR ecision Circuit Clock Recovery Circuit 1:4 EMUX Freq. ivider Merging 1/8-Rate CR Circuit Multiple Funtional Blocks A Single Functional Block! Proposed 1/8-rate CR circuit can achieve higher speed operation, lower power consumption, and smaller area. Seong-Jun Song 13

14 Proposed 1/8-Rate CR Circuit NRZ ata (4-Gb/s) 6-Bit Coarse Control Word in CC [5:0] 6 CK 0 1/8-Rate Phase etector Performing 1:4 EMUX CK 1 CK 2 CK 3 VCO (0.5GHz) T CT Charge Pump LPF ata Output Buffers :4 emultiplexed ata (1-Gb/s) Clock Output Buffers CK 0 CK 1 CK 2 CK 3 Four Half-uadrature 1/8-Rate Clocks (0.5GHz) Seong-Jun Song 14

15 Outline! Introduction! Motivation! Problem efinition! Proposed 1/8-Rate CR! Building Blocks! Measurement Results! Conclusion & Further Works Seong-Jun Song 15

16 Choice of VCO Configuration Ring Oscillator LC Oscillator elay elay elay Wide tuning range ifferent phase clock generation # Low center frequency # Low factor # High phase noise & jitter High center frequency High factor Low phase noise & jitter # Narrow tuning range # Large area Seong-Jun Song 16

17 Choice of Inductor Load Spiral Inductor Load Active Inductor Load V C C V C L 1 g m ω osc 1 LC 1 V C ω osc 1 LC g m I # Low factor (3~5) # Large area # ependent on process # ifficult to design Moderately high factor (>>10) Small area Easy to design # Noise caused by resistor and MOS Seong-Jun Song 17

18 Voltage-Controlled Oscillator * CC : uty Cycle Correction CK 0 CK 0 CK 1 CK 1 CK 2 CK 2 CK 3 CK 3 Feedback Isolation Buffers with CC * elay elay elay elay Fine Control Coarse Control 6! Four half-quadrature phase clocks! elay stage with active inductor load! CC for using both rising and falling edges of clock Seong-Jun Song 18

19 Bandwidth Extension Feedback Isolation Buffer Resistive Feedback V in V out V in V out uty-cycle Correction High CMRR Feedback (a) Block iagram (b) Transistor-Level Implementation Seong-Jun Song 19

20 Single elay Stage of the VCO M 9 Active Inductor Load R 1 R 2 M 10 M 11 M 12 V out M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 8 V in V fine_ctrl 6-Bit Coarse Control Word 6 32I 16I 8I 4I 2I I R 3 R 4 6-bit igital Coarse Tuning Folded ifferential Fine Tuning ω = ω + K V K N for N = 0,..., 63 osc FR VCO_Fine fine_ctrl + VCO_Coarse Seong-Jun Song 20

21 1/8-Rate Linear Phase etector Four emultiplexed ata ( 0 ~ 3 ) CK 0 CK 1 in CK 2 CK 3 ata & Clock Transition (CT) etector CT 0 CT 1 CT 2 CT 3 ata & Clock Transition (CT) Generator T To Charge Pump CT! Three tasks! ata Transition etection! Linear phase error detection! ata regeneration! ata demultiplexing! No systematic offset! Employing proposed folded current-mode logic family (-latch, MUX, and XOR) Seong-Jun Song 21

22 1/8-Rate Linear P Characteristic ata 250ps CK ata-ck delay V CT - V T (mv) Locking Point ata to CK delay (ps) Seong-Jun Song 22

23 Current-Mode Logic (CML) Conventional CML -Latch Proposed Folded CML -Latch CK CK High speed operation Low power consumption # High supply voltage # Need for level shifter Higher speed operation Low supply voltage No need for level shifter Wide input/output range # High power consumption # Large area Seong-Jun Song 23

24 Proposed Folded CML Family * Folded MUX * Folded XOR * = CK + CK = A B + A B = A B B B CK A * S.-J. Song, et al., to be published for JSSC, July 2003 Seong-Jun Song 24

25 Fully ifferential Charge Pump CMFB * * CMFB : Common-Mode Feedback LPF V ctrl T CT T CT V ctrl Seong-Jun Song 25 t

26 Outline! Introduction! Motivation! Problem efinition! Proposed 1/8-Rate CR! Building Blocks! Measurement Results! Conclusion & Further Works Seong-Jun Song 26

27 Chip Microphotograph VCO 1/8-Rate Phase etector Performing 1:4 EMUX CP LPF! 0.25-µm Standard CMOS! 0.9 x 1.0 mm 2 Seong-Jun Song 27

28 Test Fixture Four 0.5GHz Recovered Clock Out Gold Wire Bonding 4-Gb/s ata In Four 1-Gb/s Recovered ata Out FR-4 PCB Seong-Jun Song 28

29 Measured Recovered Clock! For PRBS input data at 4-Gb/s, 10 db/div 1MHz offset 47ps pk-pk 5.2ps RMS 1 MHz/div 100 ps/div Seong-Jun Song 29

30 Measured Eye iagrams PRBS ata Input (4-Gb/s) Four Recovered ata Output (1-Gb/s) V: 200 mv/div, H: 200 ps/div in 1/8-Rate CR Circuit CK 0 CK 1 CK 2 CK 3 Four Recovered Clock Output (0.5GHz) V: 200 mv/div, H: 200 ps/div V: 200 mv/div, H: 500 ps/div Seong-Jun Song 30

31 Recovered Clock and ata! For PRBS input data at 4-Gb/s, 200 mv/div 1-Gb/s emultiplexed Recovered ata ( 0 ) 0.5GHz Recovered Clock (CK 0 ) 500 ps/div Seong-Jun Song 31

32 Measured VCO Characteristic ifferential Fine Tuning 6-Bit igital Coarse Tuning Measured VCO Frequency (MHz) ωosc I ifferential Fine Control Voltage (V) Measured VCO Frequency (MHz) ωosc I Bit Coarse Control Word (N)! K VCO_Fine = 75 MHz/V! Fine Tuning Range = 70 MHz (14%)! K VCO_Coarse = 2.5 MHz/Word Step! Coarse Tuning Range = 150 MHz (30%) ω = ω + K V K N for N = 0,..., 63 osc FR VCO_Fine fine_ctrl + VCO_Coarse Seong-Jun Song 32

33 Performance Summary NRZ ata Rate Recovered Clock Recovered ata Capture Range VCO Fine Tuning Gain Phase Noise at 1-MHz offset Clock Jitter for PRBS BER for PRBS Power issipation (excluding output buffers) Supply Voltage Active Area Technology 4-Gb/s 0.5 GHz Four 1-Gb/s 16 MHz 75 MHz/V -112 dbc/hz 5.2 ps RMS < mw 2.5 V 0.9 x 1.0 mm µm standard CMOS Seong-Jun Song 33

34 Proposed Performance Index! From O. T.-C. Chen, et al., JSSC, Jan. 2002,! Frequency index in PLL is derived by Technology 1.8 V F = F 0.35µ m Supply Voltage (MHz)! By taking account into power consumption in CR circuit,! Proposed performance index in CR circuit can be expressed as Normalized ata Rate = Technology 70 mw 0.25µ m Power Consumption Supply Voltage ata Rate 2.5 V (Gb/s) Seong-Jun Song 34

35 Performance Comparison Reference CR Technique Normalized ata Rate ata Rate Power Consumption Supply Voltage Technology [1] Full-Rate Clock 1.12-Gb/s 1-Gb/s 300 mw 5 V 0.6-µm CMOS [2] Half-Rate Clock 1.08-Gb/s 1.25-Gb/s 150 mw 3.3 V 0.35-µm CMOS [3] Half-Rate Clock 1.27-Gb/s 10-Gb/s 285 mw 1.8 V 0.18-µm CMOS [4] Half-Rate Clock 2.17-Gb/s 1-Gb/s 85 mw 3.3 V 0.5-µm CMOS [5] Half-Rate Clock 2.62-Gb/s 6-Gb/s 83 mw 1.8 V 0.18-µm CMOS [6] 3x-Oversampling 0.76-Gb/s 4-Gb/s mw 3.3 V 0.5-µm CMOS [7] 3x-Oversampling 2.29-Gb/s 5-Gb/s 153 mw 2.5 V 0.25-µm CMOS [8] 2x-Oversampling 2.47-Gb/s 4-Gb/s 84 mw 1.93 V 0.24-µm CMOS This Work 1/8-Rate Clock 4-Gb/s 4-Gb/s 70 mw 2.5 V 0.25-µm CMOS Normalized ata Rate = Technology 70 mw 0.25µ m Power Consumption Supply Voltage ata Rate 2.5 V (Gb/s) Seong-Jun Song 35

36 Normalized Performance Comparison Normalized ata Rate (Gb/s) Full-Rate Clock Half-Rate Clock Oversampling 1/8-Rate Clock 0 [1] 1 [2] 2 [3] 3 [4] 4 [5] 5 [6] 6 [7] 7 [8] 8 This 9 10 CMOS CR Circuits Work 50% Increase [1] H. Wang, et al., ISSCC, 1999 [2] K. Iravani, et al., CICC, 1998 [3] J. E. Rogers, et al., ISSCC, 2002 [4] M. Rau, et al., JSSC, July 1997 [5] K. Nakamura, et al., SOVC, 1998 [6] C.-K. Yang, et al., JSSC, May 1998 [7] S.-H. Lee, et al., JSSC, ec [8] M.-K.E. Lee, et al., SOVC, 2002 Seong-Jun Song 36

37 Outline! Introduction! Motivation! Problem efinition! Proposed 1/8-Rate CR! Building Blocks! Measurement Results! Conclusion & Further Works Seong-Jun Song 37

38 Conclusion! A high-speed and low-power CR circuit has been introduced :! Exploiting 1/8-rate clock technique! Using a 0.25-µm standard CMOS technology! Single functional block merging clock recovery circuit, decision circuit, divider, and 1:4 EMUX! The proposed CR demonstrates 4-Gb/s and 70mW operation suitable for low cost optical interconnection applications. Seong-Jun Song 38

39 Further Works! Fully Integrated Frequency-Locked Loop! Broadband frequency detection! Improvement of BER! To improve SNR! To improve Clock Jitter Characteristic! Need for etailed Mathematical Analysis Seong-Jun Song 39

40 Supplemental Materials Seong-Jun Song 40

41 Operation of 1/8-Rate P (1/4) in CK 0 CK 1 CK 0 CK 2 CK 3 CT CK 1 CT in CT CT CK 2 T CT CK Seong-Jun Song 41

42 Operation of 1/8-Rate P (2/4) in CK 0 CK 1 CK 0 CK 1 in CK 2 CK 3 ata & Clock Transition (CT) etector CT 0 CT 1 CT 2 CT 3 CK 2 CK 3 CT 0 CT 1 CT 2 CT 3 T CT Seong-Jun Song 42

43 Operation of 1/8-Rate P (3/4) in Four emultiplexed ata ( 0 ~ 3 ) CK 0 CK 1 CK 0 CK 1 in CK 2 CK 3 ata & Clock Transition (CT) etector CT 0 CT 1 CT 2 CT 3 CK 2 CK 3 CT 0 CT 1 CT 2 CT 3 T CT Seong-Jun Song 43

44 Operation of 1/8-Rate P (4/4) in Four emultiplexed ata ( 0 ~ 3 ) CK 0 CK 1 CK 0 CK 1 in CK 2 CK 3 ata & Clock Transition (CT) etector CT 0 CT 1 CT 2 CT 3 ata & Clock Transition (CT) Generator T CT CK 2 CK 3 CT 0 CT 1 CT 2 CT 3 T CT Seong-Jun Song 44

45 Example in CK 0 CK 1 CK 2 CK 3 CT 0 CT 1 CT 2 CT 3 T CT Seong-Jun Song 45