A Modular All Digital PLL Architecture Enabling Both 1-to-2 GHz and 24-to 32-GHz Operation in 65nm CMOS

Transcription

1 A Modular All Digital PLL Architecture Enabling Both 1-to-2 GHz and 24-to 32-GHz Operation in 65nm CMOS A. V. Rylyakov 1, J. A. Tierno 1, D. Z. Turker 2, J.-O. Plouchart 1 H. A. Ainspan 1, D. J. Friedman 1, 1 IBM T.J. Watson Research Center, Yorktown Heights, NY 2 Texas A&M University, College Station, TX 1

2 Outline Introduction DPLL architecture and digital design details DCO designs Measurement results Conclusion 2

3 Introduction/Motivation Modular DPLL architecture demonstrated Realization in 2 GHz ring-based and 6 GHz, 11 GHz, and 32 GHz LC-DCO-based designs Core loop elements common to all Custom elements per design restricted to Fractional-N capability added to ring design Extra dividers added to LC-DCO designs to bring feedback clock within usable frequency range 3

4 Modular Digital PLL Architecture early/late reference 8 BB-PFD LF ΣM coarse inc/dec dither 2 3 DCO with row/col controls output phold 1/N 1/M clkg 1/16 or 1/ ΣM ring-dco version LC-DCO versions Common core digital components used in multiple designs 4

5 Late 2 Loop Filter +I +P+I -P-I -I Realized Transfer Functions 1 integral: 1 X 1 z -1 1 proportional: (1 z -1 ) X 1 z P = Proportional constant I = Integral constant Inc Dec Fractional Frequency 8-bit arithmetic realized using Kogge-Stone adder Merging proportional, integral paths simplifies DPLL logic 5

6 A7 B7 8-bit Parallel (Kogge-Stone) Adder Carry generation K K K K K K K K K K K K A0 B0 K K K K K K K K K K Maps A, B to generate (g), propagate (p) signals Carry operator g i,p i g j,p j K K K K C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 K g,p g = g i + g j p i p = p i p j (Brent-Kung) Universal block, used in: Loop Filter Integrator Feedback Divider Σ Accumulators 6

7 Divider ΣΜ vs DCO ΣΜ Requires explicit 8-bit adders Requires signed arithmetic Pipelining requires careful latency matching for proper noise shaping Uses DCO as an adder Generates DC offset (invisible due to loop action) Dithering outputs are applied in parallel with matched delays N+FN+(z -1-1)*e 1 N+FN+(z -1-1) 2 *e 2 N + Z -1 + DCO + Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 FN e1 + Z-1 + Z-1 e e1 2 + Z-1 + Z-1 e 2 7

8 DPLL Internal Clocking Multi-modulus divider phold clkg divided clkg +1 const Timing diagram output* clkg phold divided clkg *6/11/32 GHz LC-VCO cases phold is a masking signal divided clkg is compared with reference in PFD const can be updated between phold rising edges 8

9 Modular DPLL Architecture: Annotated +I +P+I -P-I + -I reference early/late BB-PFD LF + + coarse 8 3 ΣM inc/dec dither 2 DCO with row/col controls output phold 16 8 ΣM ring-dco version 1/N + 1/M clkg 1/16 or 1/4 LC-DCO version output clkg phold 9

10 coarse <1:8> 5-Stage Ring DCO inc/dec dither <1:3> output row+1 2 top rows row 8 coarse rows col inv_on rows 1 to 8 main array inc/dec shift control columns 1 to 40 Target frequency range: 1 to 2 GHz Target K DCO < 10 MHz / inverter 10

11 row/ column logic shift control inc/dec 32 GHz LC DCO Topology coarse <1:4> cap_hi <1:24> dither <1:3>, inc/dec VDDA <1:4> Circled elements differ between 32 and 6/11 GHz VCOs [as do L, C values] <1:24> <1:5> VDDA Varactor: NFET output CML I REF to 1/16 divider output_b 11

12 row/ column logic shift control inc/dec 6, 11 GHz LC DCO Topology coarse <1:4> cap_hi <1:48> dither <1:3>, inc/dec VDDA <1:4> Circled elements differ between 32 and 6/11 GHz VCOs [as do L, C values] <1:48> Varactor: accumulation-mode <1:5> VDDA output CMOS I REF to 1/4 divider output_b 12

13 Ring DCO: Open Loop Tuning Curves Frequency [GHz] C 100 C V DDA = 0.8V C 100 C V DDA =1.2V 0 1/4 1/2 3/ /4 1/2 DCO Main Array Fill Factor* K DCO = 2.6 MHz/inverter at 0.8V, 100 C K DCO = 6.1 MHz/inverter at 1.2V, 25 C 3/4 1 *Array Fill Factor = On-state inverters / Total number of inverters 13

14 Ring-DPLL: Period Jitter Histogram Average period: ps (2.06 GHz, N = 160) Jitter: 1.0 ps rms, 16.6 ps peak-to-peak (3.8 million cycles) Linear scale Time [ps] 14

15 Fractional-N Period Jitter Histograms Reference clock: MHz VDDA=VDD=1.1V, 15mA, 25 C N =79.996, 2 nd order ΣM N =79.996, 1 st order ΣM N =80 Number of counts Time [ps] Measured period jitter at 2.06 GHz (1 million cycles) N=80: 1.1 ps rms, 16.3 ps pk-to-pk N=79.996, 1 st order ΣM: 1.2 ps rms, 21.7 ps pk-to-pk N=79.996, 2 nd order ΣM: 1.5ps rms, 25.8 ps pk-to-pk 15

16 Ring-DPLL Dynamics Time, 2 ms span N = 97 N = 103 N jumps from 103 to MHz reference I = 2-8 Frequency: 1.5 GHz center, 110 MHz span 16

17 Ring-DPLL Dynamics II Time, 2 ms span N = 97 Frequency: 1.5 GHz center, 110 MHz span N = 103 N jumps from 103 to MHz reference I = 2-6 increase in integration constant reduces relock time 17

18 Ring-DPLL Dynamics III One coarse row is switched off Time, 1.8 ms span DPLL relocks to the original frequency by populating an extra row in the main array Frequency: 2.0 GHz center 110 MHz span 18

19 Time, 1.8 ms span Ring-DPLL Dynamics IV Same experiment repeated at lower center frequency One coarse row is switched off Frequency: 1.9 GHz center Frequency: 2.0 GHz center 110 MHz span 110 MHz span 19

20 Ring-DPLL Dynamics V Time, 2 ms span N = 103 One coarse row is switched off and N jumps from 103 to 97 N = MHz reference I = 2-8 Frequency: 1.5 GHz center, 110 MHz span 20

21 32 GHz LC-DCO Tuning Curves C 85 C Frequency [GHz] K DCO =76 MHz per varactor 24 LC-DCO, 1.5V 0 1/4 1/2 3/4 1 DCO Main Array Fill Factor 21

22 -20 Spectrum of 32 GHz Output Power [dbm] Frequency [GHz] Span: 200MHz. Resolution bandwidth: 10kHz. 22

23 LC-DPLL Phase Noise Plot at 32 GHz -70 Power [dbc/hz] E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency Offset [Hz] measured at VDDA=1.5V (36mA), VDD=1.3V (12.2mA), 25 C, 2 GHz reference 23

24 6 and 11 GHz DCO Tuning Curves Frequency [GHz] V, 100 C 1.3V, 25 C K DCO =9.5 MHz / /2 1 DCO Main Array Fill Factor 1 K DCO =15.6 MHz 24

25 6 and 11 GHz DPLL Phase Noise 4.8 GHz, 1.2V, 25 C 10 GHz, 1.3V, 25 C Power [dbc/hz] E+04 1.E+05 1.E+06 1.E+07 1.E E+04 1.E+05 1.E+06 1.E+07 1.E+08 Frequency Offset [Hz] 25

26 32 GHz LC-DPLL Die Photograph LC-DCO Digital CMOS Core CML Prescaler Output Driver 26

27 DPLL Performance Summary 3-stage ring DPLL 1 5-stage ring DPLL LC-tank DPLL CMOS Technology 65nm SOI 65nm bulk 65nm bulk Area 200 µm X 150 µm 180 µm X 270 µm 240 µm X 350 µm DCO 18.0 mw 11.4 mw 54 mw Power Logic at 4 GHz 15.6 mw at 2 GHz 8.3 mw at 32 GHz mw at 4 GHz at 2 GHz at 32 GHz Tuning Range 0.5 GHz 8 GHz 0.5 GHz 4.4 GHz 24 GHz 32 GHz Phase Noise dbc/hz at 4 GHz -80 dbc/hz at 2 GHz -97 dbc/hz at 32 GHz 1 ISSCC 2007, A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS ADPLL in 65nm SOI 2 Including the 1/16 pre-scaler and the output driver 3 At 1 MHz offset 27

28 Conclusion Modular All-Digital PLL architecture demonstrated on 4 different design points: 2 GHz (ring-dco) and 6,11 and 32 GHz (LC-DCO) Common core digital blocks shared between designs, easily mapped to different technologies Ring-DPLL tuning range and period jitter performance adequate for ASIC and microprocessor clocking applications LC-DPLL phase noise affected by limit cycle, typical of bangbang digital PLLs 28