A DPLL-based per Core Variable Frequency Clock Generator for an Eight-Core POWER7 Microprocessor

Transcription

1 A DPLL-based per Core Variable Frequency Clock Generator for an Eight-Core POWER7 Microprocessor José Tierno 1, A. Rylyakov 1, D. Friedman 1, A. Chen 2, A. Ciesla 2, T. Diemoz 2, G. English 2, D. Hui 2, K. Jenkins 1, P. Muench 2, G. Rao 2, G. Smith 2, M. Sperling 2, K. Stawiasz 1 1 IBM Thomas J. Watson Research Center 2 IBM Systems and Technology Symposia on VLSI Technology and Circuits

2 Outline POWER7 Architecture DPLL Design DPLL Measurements Conclusions / Acknowledgements Slide 1

3 POWER7 Microprocessor Architecture 1 Core Core Core Core PBus DPLL x 8 Core Core Core Core Eight cores and their associated L2 and L3 caches connected to each other through an asynchronous, memory coherent bus Each core can run at its own speed Core frequency is centrally managed to optimize for performance / power dissipation / etc. 1 R. Kalla POWER7: IBM s Next Generation POWER HOT Chips 2009 Tech. Digest Slide 2

4 Detail of POWER7 Micrograph: One Core 10 mm 5.5 mm L2 Cache Core 350 µm x 200 µm DPLL L3 Cache + Interconnect Slide 3

5 Microprocessor Frequency Control Performance Counters Environmental Sensors OS/Software Requests Freq1 Power Manager Freq2 Freq3 FreqN The power manager takes input from environmental sensors, performance counters, and software requests, and continuously adjusts the frequencies of each core All is done transparently with respect to code execution DPLL DPLL DPLL DPLL Clocks to Cores Slide 4

6 Microprocessor Frequency Management Effective power / frequency management requires frequency changes without interrupting code execution Large, uninterrupted frequency range (100 s of MHz to multiple GHz) necessary to go from low frequency idling modes to high frequency turbo modes Smooth frequency transitions without any missing clock cycles to avoid power supply drops caused by di/dt and other transients in the clock distribution network No undershoots in cycle time, under any circumstances Support for frequency spreading Slide 5

7 DPLL Fits the Bill Nicely Lower area than an APLL: We want at least one PLL per core, for independent frequency control Overall push to reduce the amount of analog contents in the processor DPLL uses same digital methodology (verification, timing analysis, manufacturing test) as the rest of the microprocessor Slide 6

8 DPLL Architecture 2 Programmable Voltage Regulator Reference Clock PFD Early/ Late 2 Fast/Slow 2 PI Loop Filter Proportional Bypass Integer Control 9 Fract. Control 8 DCO Control Feed- Forward Σ Row 16 Col 24 Dither 3 DCO 1/2/4 Output Divider 2/4/8 Prescaler Output Clock New Components Multiplier 8 8 Slew-rate Multiplier Filter Fractional Multiplier 10 Clock-gating signals Frac-N Σ Integer Multiplier 6 3 Multi-modulus Feed-back Divider Feedback clock, to all digital logic 2 J.A. Tierno et al A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI IEEE JSSC, Vol. 43, Issue 1, pp , Jan Slide 7

9 Three-stage Digitally Controlled Ring Oscillator: Wide Dynamic Range Some inverters are turned off Some inverters are turned on Phase 0 Phase 1 Phase 2 Output frequency a function of the fraction of enabled inverters Dynamic range: From 800 MHz to 15 GHz Voltage regulator guarantees good jitter performance Slide 8

10 DCO Voltage Regulator The DCO uses an on-chip programmable voltage regulator Insulates the ring oscillator from the noisy power supply, greatly reducing the jitter of the RO Allows centering the range of the ring oscillator across process corners The DCO voltage regulator is the only analog component in the DPLL Slide 9

11 Bang-bang Self-timed PFD Reset Ref Clk R Mutex Ref First FB Early FB Clk R FB First Ref Early A first Ref Edge FB Edge C A B first B Ref Clk Ref Faster W FB Clk FB Faster Slide 10

12 Frequency-proportional Output of the PFD Ref Clk FB Clk Ref Edge Ref Faster A pulse is generated in Ref Faster every time that Ref Clk gains one full cycle w.r.t. FB Clk The pulse rate in Ref Faster is the difference in frequencies between Ref Clk and FB Clk This pulse is used by the loop filter to quickly sweep in frequency while the PLL is out of lock When the PLL is in lock, neither Ref Faster nor FB Faster generate any pulses Slide 11

13 Loop Filter with Frequency Ramp Tracking x k_prop Ref Early x k_int DCO Control Ref Faster x k_freq FB Faster x k_freq FB Clk During frequency acquisition, Ref Faster and FB Faster are active, and quickly drive DCO Control close to its final value (k_freq >> k_int) During phase acquisition, Ref Faster and FB Faster are inactive, and the loop filter dynamics are set by k_int and k_prop Slide 12

14 Slew-rate Controlled Frequency Ramp This DPLL is part of the power management infrastructure in POWER7, and can be used to change the frequency of operation of each core independently, and without stopping code execution While changing frequency, no short cycles should be generated No overshoot in frequency (undershoot in cycle time) can ever happen Constant df/dt insures constant di/dt on the power supply Slide 13

15 Frequency Filter / Ramp Generator Mult_acc 14 Mult_in Shift and Pad 14 a a>b Comp b a<b dec inc Mult_out to Frac-N Σ Frequency filter generates a ramp of multipliers by incrementing / decrementing the multiplier at a steady rate Multiplier slew-rate is controlled by changing the rate of a divided clock 14 Filter Bypass Mult_slew DPLL Clk 8 %N Clock Divider Slide 14

16 POWER7 DPLL Testing Test fixture used for electrical characterization of POWER7 DPLL. The aluminum cooling plunger and blue cooling lines supply refrigerated water to cool the chip package Slide 15

17 Measured Frequency: Slew-rate Controlled Frequency Ramp Frequency Ramp Frequency (GHz) MHz/uS 70 MHz/uS 17.5 MHz/uS Time (us) Slide 16

18 Measured Cycle-time: End-of-ramp Transient Frequency Acquisition DCO Tcycle Step (~ 2 ps) Tcycle (ns) Phase Acquisition MHz/us Lock Time (us) Slide 17

19 Spread Spectrum Tracking Spreading: +/- 50 khz Output Frequency: 4 GHz DPLL tracks without losing lock Slide 18

20 Measurements Summary Parameter Tuning Range Period Jitter Long Term Jitter Frequency Slew- Rate Area Power Value Continuous 800 MHz to 15 GHz achievable over PVT 1 ps 4 GHz 100 ps 4 GHz 140 MHz/µs to 600 khz/µs 200 µm x 175 µm 200 µm x 175 µm 30 5 GHz Comments Output frequency is divided by two 200 MHz reference 200 MHz reference 200 MHz reference Digital Logic + DCO Voltage regulator DCO running at 10 GHz, 200 MHz reference Slide 19

21 Conclusions / Acknowledgements We designed a compact, efficient all-digital PLL in 45 nm SOI, used to set per-core frequency in an 8-core POWER7 microprocessor The PLL can be used to change the operating frequency of the core while instructions are executing A specially designed PFD provides extra outputs that are used by the loop filter to track a fast frequency ramp without making the system unstable Acknowledgments: This material is based upon work supported by the Defense Advanced Research Projects Agency under its Agreement No. HR Slide 20

22 Backup Slides Slide 21

23 Ref Clk FB Clk Ref Edge FB Edge Reset Ref First Bang-bang PFD Timing Diagram Bang-bang PFD detects arrival order and keeps it stable for one reference or divided clock cycle Output is re-sampled with a delayed version of FB_Clk before being used in loop filter Slide 22

24 DPLL Clocking DCO output Reference Clock Clock Pre-scaler Div 1/2/4 0 Clock Bypass 1 Clock Distribution to all internal logic Grid Clock Phase Holds Grid Clock Phase Hold Qualified Grid Clock To ease data transfer timing constraints, clocks in the DPLL digital logic are derived from the pre-scaled DCO output Multiple phases/frequencies are obtained by using enables to select one edge out of many Slide 23

25 25 Measured Period Jitter Period Jitter RMS (ps) Clock Frequency ( MHz ) Sub-ps RMS period jitter at the high end of the scale Very few inverters enabled at the low end of the scale; period jitter increases accordingly Slide 24