ISSCC 2006 / SESSION 4 / GIGABIT TRANSCEIVERS / 4.1

Transcription

1 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / A 0Gb/s 5-Tap-/4-Tap-FFE Transceiver in 90nm CMOS M. Meghelli, S. Rylov, J. Bulzacchelli, W. Rhee, A. Rylyakov, H. Ainspan, B. Parker, M. Beakes, A. Chung, T. Beukema, P. Pepeljugoski,. Shan, Y. Kwark, S. Gowda, D. Friedman BM, Yorktown Heights, NY To support the high bandwidth requirements of many systems such as servers or data communication routers, low-power smallarea /O solutions are needed for serial chip-to-chip communications at line rates beyond 0Gb/s []. These /Os must be capable of supporting low-cost package and board technologies that may introduce large signal degradation through bandwidth loss, reflection, and crosstalk. n this paper, a 90nm CMOS 0Gb/s transceiver is presented. The efficient implementation of a scheme in the receiver and of a FFE scheme in the transmitter allows NRZ data transmission and avoids the complexity and power consumption of a multilevel data-transmission design []. The transceiver design follows the basic architecture of the 0.3µm CMOS 6.4Gb/s SerDes core presented in [3]. The main design enhancements are related to the reduction of the response time and the improvement of the timing-recovery precision. Also, a more power-efficient half-rate TX architecture is adopted. As shown in Fig. 4.., the TX consists of a first multiplexing stage that retimes 4 single-ended quarter-rate data inputs and generates two differential half-rate even and odd data streams. These are shifted one U with respect to each other then interleaved together to form the st tap of the FFE, and successively shifted by a U then interleaved again together to form the 3 remaining taps. The 4 taps have maximum weights of {0.5,, 0.5, 0.5} with a resolution of {4, 6, 5, 4} bits respectively. The maximum main tap output amplitude is.v ppd. Figure 4.. shows the TX output eye diagram of a packaged part with -5% equalization on the st post-cursor compensating for diode capacitance and the extra 4dB of losses of the package and evaluation board. A breakout test site of the TX is described in detail in [4]. The RX block diagram is shown in Fig A T-coil compensation network is used to mitigate the effect of the diode capacitance on S. n order to ensure linear operation of the, a VGA regulates the data swing at the slicer to about 0.6V ppd (below -db compression point). The VGA is designed to have 6dB of gain range and handle up to.v ppd data input swing. Besides ensuring that the analog front-end of the receiver has a wide linear range of operation and 5GHz or higher 3dB bandwidth, the most challenging part in the design is to guarantee that the voltage at the slicer input (where weighted post-cursors, i.e., previously received data bits, are fed back and summed) has settled sufficiently before the data decision is made. f a classical fullrate approach is used, the feedback-loop delay including the settling time needs to be less than one U or 00ps at 0Gb/s. To ease this requirement and at the same time achieve lower power consumption, a half-rate clock with speculative feedback on the first post-cursor and dynamic feedback on the remaining taps has been implemented (Fig. 4..3). The feedback loop delay is designed so that % settling accuracy is achieved within U. The clock-recovery circuit operates on the non- equalized data signal and uses an Alexander-type half-rate phase detector. The early/late phase detector output is digitally filtered to generate increment/decrement signals that control a high-precision phase rotator. This phase rotator (Fig. 4..4) operates from two half-rate differential clock phases, and Q. t switches the polarity of the,q phases (quadrant selection) and uses a 4b CM interpolator to achieve 6 phase positions within each quadrant. The phase interpolator uses a 5-cell current-steering DAC plus two additional fixed-current cells of half size to realize interpolation ratios varying from 0.5:5.5 to 5.5:0.5. Avoiding zero-value interpolation weights allows the rotator to step across each quadrant boundary by changing phase polarity only (no change in interpolation ratio). The 5 cells of the DAC are not uniform; instead, their relative sizing is optimized for best rotator linearity, with the largest cells being switched near the quadrant boundaries. Rotator linearity is also improved with the use of slew-ratecontrolled buffers, which make the rotator inputs more sinusoidal. The rotator achieves a measured min-to-max step ratio better than :. A link demonstrator C is implemented and packaged in a plastic BGA module to conduct various link experiments. The C (Fig. 4..5) consists of two RX pairs and two TX pairs, each pair being either externally or internally clocked, and is configured through a parallel-port interface. The on-chip clock generation circuit consists of a full-rate C-VCO-based P operating from 9GHz to 3.4GHz. The jitter generation is <0.7ps rms (f c /667 00MHz noise integration bandwidth) and the transfer bandwidth lies between to 3MHz. t draws 30mA from an on-chip voltage regulator that generates a.v low-noise supply from.8v. The power consumption of one TX/RX pair and one P is 300mW (.V ppd TX data ouput swing). The link experiments presented in this paper are performed using the RX and TX pairs clocked by the on-chip Ps at the nominal data rate of 0Gb/s. n a first experiment, a 6-inch Tyco legacy backplane channel with 4dB losses at 5GHz is successfully equalized using a stand-alone module mounted on a socketed evaluation board and used in a serial loop-back configuration. Evaluation board, plastic module, and coaxial cabling bring the total losses to 33.5dB (from the C TX output back to the RX input). After the fixed transmitter FFE taps are configured for the channel and the has adapted, the bathtub curve of the equalized serial data stream is measured. To that end, the tap optimization loop is halted and the position of the phase rotator providing the data sampling clock (-clock) is externally controlled. As shown in Fig. 4..6, the equalized-signal horizontal eye opening is % at 0-9 BER. Finally, in another experiment, two modules directly soldered on a board are serially connected to each other through different channels. Figure 4..7 shows the horizontal eye openings at 0Gb/s and 0-9 BER for 0, 5, and 0-inch trace lengths with different via-stub configurations. Acknowledgments: The authors acknowledge funding support from the MPO; contract H C-090. They also wish to thank M. Sorna, S. Zier, P. Metty and K. Heilmann from BM Fishkill for their important support. References: [] Common Electrical /O (CE) Electrical and Jitter nteroperability Agreement for 6+ Gbps and + Gbps /O, Optical nterconnect Forum, CE-0.0, Feb., 005. [] J.. Zerbe, et al., Equalization and Recovery for a.5-0gb/s -PAM/4-PAM Backplane Transceiver Cell, EEE J. Solid-State Circuits, vol. 38, no., pp. -30, Dec., 003. [3] M. Sorna, et al., A 6.4Gb/s CMOS SerDes Core with Feedforward and Decision-Feedback Equalization, SSCC Dig. of Tech. Papers, pp. 6-63, Feb., 005. [4] A. Rylyakov, et al., A ow-power 0 Gb/s Serial ink Transmitter in 90-nm CMOS, EEE CSCS, pp. 89-9, Nov., EEE nternational Solid-State Circuits Conference / EEE

2 SSCC 006 / February 6, 006 / :30 PM V DDA =.V 50 V DD =.0V DACs & Bias Control V DDA =.V /4 / /4 x 4x x x Out-P Out-N (0Gb/s) ink = 'TX module - evaluation board - 4-inch coax' (.5Gb/s) D 0 D D D 3 V DDO =.0V (5Gb/s) 4: MUX sgn - sgn 0 sgn sgn 00 mv/div 7 ps/div 4dB losses at 5GHz C (5GHz) Figure 4..: Transmitter block diagram. Figure 4..: 0Gb/s packaged transmitter output eye diagram. From P (5GHz) n_p n_n (0Gb/s) Vcm 50 T-Coil Compensation Network V DD =V V DDA =.V VGA C- C-Q - control Phase rotator P P Q Phase Edge :8 detector Block Amp Q- control Tap weights CDR 8:6 CM CMOS 8 Amp Edge V DDO =V D 0 D D D 3 (.5Gb/s) SEWBUF SCK- SCK-Q PO 4 ZP ZN latch latch latch h-5 Tap-feedback and weighting latch latch latch Tap weights CK- CK-Q SEW 4 SEW DAC NT VB 30 Fixed cell 5-cell current-steering DAC 5 Figure 4..3: Receiver block diagram. Figure 4..4:,Q phase rotator schematic. ink Demonstrator Floorplan Rx RX Rx RX Rx RX Rx RX Tx Rx ink= TX module--inch coax-6-inch Tyco channel--inch coax-rx module P External External P CDR ogic Registers Parallel Port nterface Pre -drivers, DACs & 50 drivers 4: MUX mux 4-tap gen. Current Bias 8:6 Clk4 50 driver :8, Amp, Phase Edge align Rotator clk clk buf buf / : D drivers Current Mirrors & DACs Clk4 50 Drv VGA / Tcoil.00E+00.00E-0.00E-0 Bathtub Curves Bathtub Curve Vcm gen..00e-03.00e-04.00e-05 P C -VCO Phase ocked oop Clk dist west Voltage regulator VCO Cal P -Ref Clk dist east Band - gap BER.00E-06.00E-07.00E-08.00E-09.00E-0.00E-.00E phase position Phase Position Figure 4..5: ink demonstrator floorplan and layout details. Figure 4..6: Equalized 6-inch tycolegacy backplane channel. 006 EEE nternational Solid-State Circuits Conference / EEE

3 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. ink: TX module-trace-rx module (inch) 5GHz losses Number of vias 3.8mm via stubs /.8mm via stubs /.8mm via throughs 0 (#) db / 0 / 0 0 (#) 0dB 0 / / 0 5 5dB 4 / / % 0 5dB 0 / 0 / Horizontal Eye Openning (0-9 BER) 50.00% 40.00% 30.00% 0.00% 0.00% +FFE FFE 0.00% 0" (#) 0" (#) 5" 0" ink Figure 4..7: Chip-to-Chip link equalization experiments. 006 EEE nternational Solid-State Circuits Conference / EEE

4 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. V DDA =.V 50 Out-P V DD =.0V DACs & Bias Control V DDA =.V /4 / /4 x 4x x x Out-N (0Gb/s) V DDO =.0V (.5Gb/s) D 0 D D D 3 (5Gb/s) 4: MUX sgn - sgn 0 sgn sgn C (5GHz) Figure 4..: Transmitter block diagram. 006 EEE nternational Solid-State Circuits Conference / EEE

5 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. ink = 'TX module - evaluation board - 4-inch coax' 00 mv/div 4dB losses at 5GHz 7 ps/div Figure 4..: 0Gb/s packaged transmitter output eye diagram. 006 EEE nternational Solid-State Circuits Conference / EEE

6 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. From P (5GHz) n_p n_n (0Gb/s) Vcm 50 T-Coil Compensation Network V DD =V V DDA =.V VGA C- Phase rotator P P Phase detector Block C-Q Q - control Q- control Edge Amp :8 Tap weights CDR 8:6 CM CMOS 8 Amp Edge V DDO =V D 0 D D D 3 (.5Gb/s) latch latch latch h-5 Tap-feedback and weighting Tap weights latch latch latch Figure 4..3: Receiver block diagram. 006 EEE nternational Solid-State Circuits Conference / EEE

7 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. ZP ZN SCK- SCK-Q SEWBUF PO 4 CK- CK-Q NT 30 SEW 4 SEW DAC VB Fixed cell 5-cell current-steering DAC 5 Figure 4..4:,Q phase rotator schematic. 006 EEE nternational Solid-State Circuits Conference / EEE

8 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. ink Demonstrator Floorplan Rx RX Rx RX Rx RX Rx RX Tx Rx P External External P CDR ogic Registers Parallel Port nterface Pre -drivers, DACs & 50 drivers 4: MUX mux 4-tap gen. Current Bias 8:6 Clk4 50 driver :8, Amp, Phase Edge align Rotator clk clk buf buf / : D drivers Current Mirrors & DACs Clk4 50 Drv VGA / Tcoil Vcm gen. P C -VCO Phase ocked oop Clk dist west Voltage regulator VCO Cal P Clk dist east -Ref Band - gap Figure 4..5: ink demonstrator floorplan and layout details. 006 EEE nternational Solid-State Circuits Conference / EEE

9 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. ink= TX module--inch coax-6-inch Tyco channel--inch coax-rx module BER BER Bathtub Curves.00E+00.00E-0.00E-0.00E-03.00E-04.00E-05.00E-06.00E-07.00E-08.00E-09.00E-0.00E-.00E phase position Bathtub Curve Phase Position Figure 4..6: Equalized 6-inch tycolegacy backplane channel. 006 EEE nternational Solid-State Circuits Conference / EEE

10 SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. ink: TX module-trace-rx module (inch) 5GHz losses Number of vias 3.8mm via stubs /.8mm via stubs /.8mm via throughs 0 (#) db / 0 / 0 0 (#) 0dB 0 / / 0 5 5dB 4 / / % 0 5dB 0 / 0 / Horizontal Eye Openning (0-9 BER) 50.00% 40.00% 30.00% 0.00% 0.00% +FFE FFE 0.00% 0" (#) 0" (#) 5" 0" ink Figure 4..7: Chip-to-Chip link equalization experiments. 006 EEE nternational Solid-State Circuits Conference / EEE