100 Gb/s: The High Speed Connectivity Race is On

Transcription

1 100 Gb/s: The High Speed Connectivity Race is On Cathy Liu SerDes Architect, LSI Corporation Harold Gomard SerDes Product Manager, LSI Corporation October 6, 2010

2 Agenda 100 Gb/s Ethernet evolution SoC challenges and solutions to drive 4x25 Gb/s Ethernet High Speed Serial link system design Summary 2

3 SerDes SerDes Contemporary 100 Gb/s Ethernet with 10 Gb/s SerDes 100 Gb/s Media Access Controller (MAC) 20 differential pairs per interface 100 Gb/s Physical Coding Sublayer (PCS) Optional Forward Error Correction (FEC) 10x10 GbE 20 virtual lanes 2:1 bit multiplexer 10 x 10 Gb/s SerDes 10 physical lanes Challenges for 10 x 10 Gb/s implementation implies high cost Uses many package and/or connector pins Complicates board routing and more high speed signal layers Limits ASIC and faceplate port densities Large number of pairs cabling to terminate implies higher cost Large outer diameter implies heavy, inflexible cable Today s 100 Gb/s Ethernet built from 10 lanes of 10 Gb/s SerDes 3

4 SerDes SerDes SerDes SerDes Industry Trend for High Speed Serial Link System Merging Gb/s serial electrical links IEEE 100GbE, OIF CEI 28G-SR/25G-LR, 32GFC, Infiniband EDR Lower-cost, more manageable cable assemblies Common form-factors and connector technologies 10x10 GbE 4x25 GbE 4 x 25 Gb/s is the natural evolutionary step for 100 Gb/s Ethernet 4

5 SerDes SerDes SerDes SerDes Path from 10x10 Gb/s to 4x25 Gb/s: Challenges 10x10 GbE Challenges Lossy links and noisy environment Need High speed circuit design at Gb/s Technology and implementation limitations Large channel counts (~200) in SoCs 4x25 GbE - 32dB IL at 5GHz - 30dB Xtalk BladeSystem Legacy Channels already present significant 10 Gb/s! 5

6 SerDes SerDes SerDes SerDes Path from 10x10 Gb/s to 4x25 Gb/s: Solutions 10x10 GbE 4x25 GbE Addressed Challenge High-Loss Channel High-Loss and Noisy Environment Noisy Environment Technology and Circuit Limitations Large Channel Counts All Solution Space Alternative Signaling Format Beyond NRZ ADC + DSP-based SerDes Architecture FEC and Noise Cancellation Innovative Circuit Implementation Advanced SoC Integration Joint System-Design Optimization 6

7 FEC FFE DFE System Interface SerDes Architecture Evolution Industry trends are to consider alternative signaling formats beyond NRZ like Multi-level or Multi-band for 25G+ long reach application Low power and high speed interleaved ADC technology enables DSP architecture to extend equalization capability Forward Error Correction (FEC) and crosstalk cancellation to further improve SNR ADC 1 Analog Filter AGC ADC 2 Analog Front End ADC n Interleaved ADC Timing Recovery Digital Domain Reference: Liu et al, Comparison of signaling and equalization schemes in high speed SerDes (10-25Gbps) DesignCon

8 Implementation Challenges for Building a 25G SerDes Challenge Requirements Constraint Signal Integrity RL of 12.5GHz Low power Tx Driver Bandwidth 18.75GHz Low power Signal Dynamic Range Scaling 30dB Linearity 28nm CMOS device 0.85V Ultra-low PLL Random Jitter 250fs (rms) Low power Circuit innovations required to tackle 25G SerDes challenges Reference: Wu et al, A 2x25Gb/s Deserializer with 2:5 DMUX for 100Gb/s Ethernet applications ISSCC

9 Circuit Innovation to Tackle Implementation Challenges (I) Source-Series Terminated (SST) driver with a bridge inductor CMOS differential circuit provides Ultra-high bandwidth for 25 Gbps signal processing Bridge inductor mitigates return loss degradation from I/O capacitance SST Driver with Inductor TX Return Loss Simulation of 16G-LR driver Without Inductor 8dB RL 25 Gbps With Inductor Blue: without inductor Black: with inductor and power mesh Pink: with inductor SST driver simulations on LSI 16G-LR SerDes meet 8dB RL 25 Gbps 9

10 Data Alignment Decoding Bubble Correction Circuit Innovation to Tackle Implementation Challenges (II) ADC-based SerDes for 25Gbps Serial link with alternative signaling 12.5Gs/s 6-bit low-power time-interleaved ADC enables DSP for 25G SerDes DSP provides powerful equalization to tackle ISI, crosstalk and reflection ISI Correction CDR Gain Adaptation Skew Adjustment ADC Calibration 10

11 High Channel Count SerDes Integration in ASIC Asymmetrical TX and RX Challenges in high channel count SerDes integration High-speed Clocking within SoC Power Integrity of SoC High-speed Signal Integrity 11

12 Challenges in high channel count SerDes integration - PLL Coupling in High Channel Count SerDes Integration LC-PLL Coupling is one of top challenges for high-speed clocking Advanced techniques are required for multiple LC-PLL placement Minimum spacing between 2 LC-PLLs Design rule for substrate isolation and power mesh PLLA Clock Out Spectrum of LSI PLLA 40nm = GHz, 14G-LR PLLB = 8.5 GHz SerDes PLLA Clock Out PLLA= GHz, PLLB = 8.5 GHz Measured Jitter of PLLA Variation limited to +/- 1ps PLLB Test Condition G p2p Jitter 8.5G 12.3ps PLLA Clock Out G 13.2ps 12.5G 12.9ps G 11.2ps E+09 E+09 E+09 E+09 E+09 E+09 E+09 E+09 E+09 E+09 E+09 Powered off 12.6ps Advanced LC-PLL placement achieves no injection lock coupling from other PLL 12

13 Challenges in high channel count SerDes integration - Power Integrity in High Channel Count SerDes Integration Simulation Setup Simulated AC Noise PI Analysis of SoC with LSI 14G-LR SerDes Power supply Recommended PKG DCAP PKG IR Drop (%) Self-induced on-die AC noise peak voltage (%) CAP Value Spec Simulated Spec Simulated VDDA 22nF (x2) VDDREF 10nF (x2) VDDA1P8 N/A 1.0 < PI analysis ensures IR drop and AC noise meet SoC design requirements 13

14 Magnitude (db) Challenges in high channel count SerDes integration - Package SI for High Channel Count SerDes Integration Package routing length can vary 12mm to 25mm for high channel count SoC Package SI Analysis of SoC with LSI 14G-LR SerDes TX insertion loss TX return loss RX-TX cross talk 0 CW Tx Device Sdd 22 Return Loss: Worst Case Die over PVT Frequency (GHz) Port 0: Tx Port 1: Tx Port 2: Tx Port 9: Tx 16GFC Epsilon T Sdd22 RL Compliance Spectrum Package SI Kit provides powerful tool for High-Speed SI analysis 14

15 Challenges in high channel count SerDes integration - Multiple dimensions Electrical Increased loss over given medium length System sizes do not shrink Fixed budget loss driven by a transceiver Mechanical Increased xtalk at connector and package New BGA routing strategy required Port density vs. signal integrity Thermal Dynamic power consumption increase Single hot spot ASIC thermal management Cannot solve with innovative circuits alone 15

16 High-Speed System Design Considerations: SerDes SerDes targets compensation for non-ideal system characteristics DJ caused by frequency dependent loss and reflections Limited ability to address RJ from excessive crosstalk RX Floating Tap DFE a k Tx FIR RX Linear EQ Transmitter Channel Receiver + â k SerDes Features TX FIR de-emphasis RX Linear EQ RX Floating Tap DFE RX DFE loops System Benefit Reduction in dispersion/loss Reduction in dispersion/loss Compensates post-cursor ISI and reflections Improves immunity to Crosstalk SerDes mitigates the need for advanced PCB material and Interconnect Solutions until now 16 LSI Proprietary

17 High Speed System Design Considerations: Crosstalk 10Gbps System Example with severe Crosstalk TX 7.5 Megtron-6 40 Megtron Megtron-6 Xcede Connector Xcede Connector RX Without Crosstalk With Crosstalk Linear EQ Only Linear EQ + DFE Joint System Optimization required for crosstalk mitigation 17

18 Magnitude (db) High Speed System Design Considerations: Reflection 10Gbps System Example with severe Reflections 0 Worst Case 5 inch Blade Channel with FCI GigArray Mezz Connector 5 inch Chip-to-Chip Blade Channel SoC Mezz Card Mezz Connector Blade Card SoC Frequency (GHz) Sdd 21 Insertion Loss: Blade Channel Sdd 11 Return Loss: Blade Channel Sdd 21 Insertion Loss: Ideal 5-inch FR4 trace Significant reflections at 5 GHz Nyquist Frequency 18

19 High Speed System Design Considerations: Reflection 10Gbps System Example with severe Reflections 5 inch Blade Channel 5 inch Ideal FR4 Trace Channel reflections Fixed and Floating Rx DFE taps 1-tap Rx DFE Joint System Optimization required for reflection mitigation 19 LSI Proprietary

20 High Speed System Design Considerations: WC Scenario High density system applications require truncated search criteria Bound the problem by simulating conservative worst case scenarios Parameterize problem and limit permutations to only viable options WC Scenario SI simulation stress parameter SerDes Rx Stress Goal 1 Maximize IL and XTLK magnitudes Degrade SNR 2 Maximize reflections using short T-lines and/or long stubs Increase ISI from reflections Stressing System simulation model with worst case SI scenarios 20

21 Magnitude (db) Magnitude (db) 25 Gb/s System Design Challenges Higher data rates lead to electrically longer channels Consequences: diminishing SNR s and generally higher return loss! Gb/s 25 Gb/s Less SNR Insertion Loss Total XTLK Higher Return Loss Return Loss Frequency (Hz) Frequency (Hz) Primary Impairments are More Accentuated at Higher Frequencies Reference: Kollipara et al, Practical Design Considerations for 10 to 25 Gbps Copper Backplane Serial Links, DesignCon

22 25 Gb/s System Design Issues Issue Potential Solutions Elevated Insertion Loss Ultra Low Loss Tangent PCB laminates Ultra Low Profile Copper Aggravated dispersion Lower Dielectric Constant Elevated IO Return Loss Elevated Connector Return Loss Elevated Connector Crosstalk Innovative circuit / inductors Optimized Mating Interface Impedance Smaller Compliant Pins Improved Shielding Optimized Footprint Topology Joint System Optimization Required for 4x25 Gb/s 22

23 25 Gb/s Applications Power vs. System Margins Tradeoff LSI IP and System design focus on application margins 3-sigma design and beyond for some key parameter (latch offset) Low margins Analog and CML circuits for industry leading performance and margins Low Power Design but not at the expense of system margins No Skew LSI margins System Margin Focus.at manageable power 23

24 Summary 4 x 25 Gb/s is the natural evolutionary step for 100 Gb/s Ethernet SerDes architecture and circuit innovation required for 4 X 25 Gb/s SoCs require high quality clocking, Power Integrity and SI analysis 100G is a multi-dimensional problem that needs to be tackled holistically SerDes alone not a panacea for high speed system design challenges Joint System Optimization required for crosstalk and reflection mitigation 24

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