A Pin and Power Efficient Low Latency 8-12Gb/s/wire 8b8w- Coded SerDes Link for High Loss Channels in 40nm Technology

Transcription

1 A Pin and Power Efficient Low Latency 8-12Gb/s/wire 8b8w- Coded SerDes Link for High Loss Channels in 40nm Technology Anant Singh 1, Dario Carnelli 1, Altay Falay 1, Klaas Hofstra 1, Fabio Licciardello 1, Kia Salimi 1, Hugo Santos 1, Amin Shokrollahi 1, Roger Ulrich 1, Christoph Walter 1, John Fox 2, Peter Hunt 2, John Keay 2, Richard Simpson 2, Andy Stewart 2, Giuseppe Surace 2, Harm Cronie 3 1 Kandou Bus, Lausanne, Switzerland, 2 Kandou Bus, Northampton, United Kingdom, 3 Lausanne, Switzerland

2 Outline Introduction and motivation Macro architecture TX RX System Implementation Results Conclusion

3 Motivation Demand for semiconductor component IO data bandwidth is increasing, pin count is not: need to transmit more bits per pin per second Many industries expect doubling the throughput at equal (or lower) power at every generation Traditional methods are running out of steam.

4 Throughput Increase Change the channel (expensive) Change the signaling (cost depends) One direction: multi-level (4-PAM, 8-PAM, etc)

5 Throughput Increase Change the channel (expensive) Change the signaling (cost depends) One direction: multi-level (4-PAM, 8-PAM, etc) Another direction: Pool more than two wires together, and disperse information among them Generalization of differential signaling

6 Chord Signaling We have developed a whole new theory of signaling based on information dispersal among multiple wires to increase throughput, reduce power, and combat noise Theory has similarities to MIMO in wireless systems, but is unique to chip-tochip communication

7 This Talk Report on implementation of one of the chord signaling methods, called 8b8w 8 bits of information are dispersed among 8 wires Pin-efficiency of single-ended signaling, but much better signal integrity through differential type receivers Only one instantiation of a general technique.

8 8b8w Coding At every UI two of the eight wires are driven high (+1), two are driven low (-1), and four are left at common mode (0). Information is encoded in the positions of the high/low/quiet wires

9 Conceptual View Transmission lines Digital encoder Ensemble driver Ensemble receiver 0,5 3,4 Digital decoder Bits Codeword Arrows show direction of current only. Link is unidirectional. Information to re-create codeword Bits

10 Codebook Total number of distinct permutations of (+1,+1,0,0,0,0,-1,-1) is 8! 2! x 2! x 4! = 420 Of these 256 are chosen judiciously to minimize encoding/decoding complexity 8 bits are transmitted per UI.

11 Quiescent Communication Codeword is uniquely determined by the positions of the 0 s and +1 s The 0 s don t use active power But their positions count for 6 of the 8 bits 6 of the 8 bits are communicated via quiescence, without using active line power. Line power is that of two differential pairs, throughput is 4 times as large.

12 8b8w-Coded SerDes Link Transmits 8-bits over an 8-wire interface Pin efficiency is 1 Differential legacy mode transmits 4-bits on the same 8-wire interface (as 4 differential pairs) Pin efficiency is 0.5

13 Encoder Implements the codebook efficiently

14 Encoder Implements the codebook efficiently No table look-up

15 8b8w Codebook Implements a codebook efficiently No table look-up

16 Code Properties If (c 1,.., c 8 ) is a codeword produced by encoder, then current (voltage) of strength c 1 is applied to the first wire, current (voltage) c 2 is applied to the second wire, etc c c 8 = 0 Zero common mode and SSO noise Receiver uses reference-less comparator network to determine codeword

17 Outline Introduction Macro Architecture TX RX System Implementation Results Conclusion

18 Macro Architecture Components: TX Pattern generators, encoder, serializer Output Driver, FIR RX CTLE, multi-phase detector & sampled system, decoder, errorcheckers Eye scope Clock generation Chip control Differential legacy mode is included for comparison and testing Dig. pads Decoder Output Driver Mux Encoder SPI bridge VTC Track & hold CTLE TX clock generation RX clock generation 3mm x 2mm

19 Transmitter Digital encoder 8:1 serializer From datagenerator 64b Digital E N C O D E R S 64N 64P 8:2 M U X 2N,2P x8 Analog Tx 2:1 & FIR M U X Output Driver N,P x8 R t 2GHz clock 8GHz clock Vcm 2GHz clock Clock regeneration & divide by 4 8GHz clock

20 Output Driver Current mode 2-tap FIR Replica bias ckt w/ swing control Vbp dp7 dn7 VDDA ternary signals wire7 R t R t Vbn Vcm (Tx) Vcm (Rx) dp6 wire6 dn6 R t Vcm (Tx) R t Vcm (Rx)

21 Macro Architecture Components: TX Pattern generators, encoder, serializer Output Driver, FIR RX CTLE, multi-phase detector & sampled system, decoder, errorcheckers Eye scope Clock generation Chip control Differential legacy mode is included for comparison and testing Dig. pads Decoder Output Driver Mux Encoder SPI bridge VTC Track & hold CTLE TX clock generation RX clock generation 3mm x 2mm

22 Receiver Analog front end rank-orders the wires based on detected voltage levels Digital logic detects positions of two maxima ( +1 s) and two minima ( -1 s) in order to decode the bits Information is encoded in the positions, not the actual values on the wires Our receiver actually completely rank orders the wire values

23 Receiver Top Level 16-ph SDC 4-ph FE sampler VTC arbiters 8 GHz ext. CLK Multi-phase generator SDC clock gen,1ghz

24 Receiver Top Level Eye-scope 2 nd T&H 16-ph VTC 16-ph SDC 16-phase time interleaved system ½ rate external clock used as input Analog FE: CTLE, 4-ph T&H 4-ph FE sampler ¼ rate clk per-wire PI VTC arbiters Digital decoder Per-wire phase interpolators (PI) produce ¼ rate sampling clocks external ½ rate clk input 8 GHz ext. CLK Multi-phase generator SDC 1 clock gen,1ghz 16 rate clk

25 Analog Front End Designed to pass high frequency common mode signal in order to allow realignment (de-skew) without distortion

26 Analog Front End Designed to pass high frequency common mode signal in order to allow realignment (de-skew) without distortion Suppresses low frequency common mode noise

27 Analog Front End

28 Analog Front End Input is DC coupled Incoming signals

29 Analog Front End VCM Input is DC coupled Level shifter sets the appropriate common mode for the input stage Incoming signals

30 Analog Front End CTLE CTLE Hybrid between a generalized differential pair and a commonsource amplifier

31 Analog Front End CTLE Shared node CTLE Hybrid between a generalized differential pair and a commonsource amplifier The shared node is stabilized at high frequencies by capacitors effectively turning the structure into a single-ended commonsource amplifier with source degeneration

32 Signal Path T&H CTLE is followed by track and hold circuits (T&H)

33 Signal Path per-wire sampling clks T&H CTLE is followed by track and hold circuits (T&H) Sampling clocks can be adjusted per-wire for deskewing the incoming signals up to 1UI

34 Signal Path T&H CTLE is followed by track and hold circuits (T&H) Sampling clocks can be adjusted per-wire for deskewing the incoming signals up to 1UI T&H operates at 1/4 th rate (4-phase system)

35 Signal Path buffer 2 nd T&H Buffer drives aligned signals to 2 nd T&H circuit (operates at 1/16 th rate)

36 Signal Path Buffer drives aligned signals to 2 nd T&H circuit (operates at 1/16 th rate) VTC produces an edge at time proportional to sampled voltage

37 Signal Path arbiters Buffer drives aligned signals to 2 nd T&H circuit (operates at 1/16 th rate) VTC produces an edge at time proportional to sampled voltage Arbiter network compares the arrival times of edges to rank order the wires

38 VTC cap Converts the sampled voltage to a ramp by discharging a precharged capacitor sampled signal

39 VTC common node Converts the sampled voltage to a ramp by discharging a precharged capacitor Has controlled current source with common tail device across the 8 wires, which allows for different gain settings

40 VTC offset correction Converts the sampled voltage to a ramp by discharging a precharged capacitor Has controlled current source with common tail device across the 8 wires, which allows for different gain settings Includes offset correction

41 VTC Finally a threshold detector converts ramp to an edge

42 VTC to arbiter network Finally a threshold detector converts ramp to an edge And drives to arbiter network that compares arrival times of the 8 edges

43 Receiver Control Loops (1) Information is used from VTC & arbiter network to sort the wires based on voltage (max to min). Error count is logged software

44 Receiver Control Loops (1) Information is used from VTC & arbiter network to sort the wires based on voltage (max to min). Error count is logged (2) Code aware algorithms run in software that use sorting info for timing optimization SPI

45 Receiver Control Loops (3) Set optimal sampling point, per-wire deskew, EQ and gain settings, offset comp (1) Information is used from VTC & arbiter network to sort the wires based on voltage (max to min). Error count is logged SPI (2) Code aware algorithms run in software that use sorting info for timing optimization SPI

46 Receiver Control Loops (3) Set optimal sampling point, per-wire deskew, EQ and gain settings, offset comp (4) DLL aligns the clks (1) Information is used from VTC & arbiter network to sort the wires based on voltage (max to min). Error count is logged SPI (2) Code aware algorithms run in software that use sorting info for timing optimization SPI

47 Receiver Control Loops Control loops run continuously and adapt to incoming signal (3) Set optimal sampling point, per-wire deskew, EQ and gain settings, offset comp (4) DLL aligns the clks (1) Information is used from VTC & arbiter network to sort the wires based on voltage (max to min). Error count is logged SPI (2) Code aware algorithms run in software that use sorting info for timing optimization SPI

48 Outline Introduction Macro Architecture TX RX System Implementation Results Conclusion

49 System Implementation Chip board (TX) Channel board CLK board Chip board (RX) Industrial Demo Session on Monday, Feb 10 th, 2014 DUT Chip board with transceiver mounted as chip-on-board, I/O fan-out to 2x8 SMA connectors, SPI test interface, DAC-controlled power supplies Channel: Channel board with 3 sets of traces, for a total channel length of 369mm/556mm/ 792mm (Rogers RO4350B/ RO4450F), IL 12-17dB Clock: Custom clock PCB generating 4-8GHz differential clocks

50 System Implementation Test system and channel MEDIUM SHORT Channel losses Channel board IL is in the range of 12-17dB at 6GHz Additional 5dB loss due to chip board traces, connectors and cables Wire bond inductance is in the range of 1-1.5nH

51 System Implementation Data generators and test patterns 8b8w data generation and encoding Differential legacy data generation for 4 lanes Modes: 8b8w Differential (legacy) Patterns PRBS9 PRBS31 Custom

52 Outline Introduction Macro Architecture TX RX System Implementation Results Conclusion

53 8b8w vs Differential Differential signaling 8b8w signaling Reference-less receiver YES YES Balanced signals YES YES Wires required for 8 bits 16 8 Line power for 8 bit, equal peak-to-peak Line power for 8 bit, equal noise margin -1 +½ -½

54 Results Differential mode vs. 8b8w mode GBaud Differential Mode Gb/s/ wire Gb/s (8-wires) 8b8w Mode Gb/s/ wire Gb/s (8-wires) Legacy differentialpair mode needs to run at 16Gbd vs. 8b8w mode at 8Gbd in order to deliver the same effective throughput (64Gb/s) Differential 8b8w Total,mW pj/bit Measured power consumption is about 40% lower at same effective throughput

55 Results Differential mode vs. 8b8w mode: Measured bathtub plots at equivalent throughput (64Gb/s) Error rate Error rate Differential 16GBd UI = 62.5ps Opening: 24ps time, ps 8b8w 8GBd UI = 125ps Opening: 50ps time, ps

56 Results Differential mode vs. 8b8w mode: Measured bathtub plots at equivalent throughput (64Gb/s) Error rate Error rate No errors observed during sweep Differential 16GBd UI = 62.5ps Opening: 24ps time, ps 8b8w 8GBd UI = 125ps Opening: 50ps time, ps

57 Results Measured bathtub plot at 12GBd in 8b8w mode over medium loss channel (IL=15dB) Error rate Accumulated error rate time, ps Bit error counting tests run over weekend periods show an accumulated BER better than 8e -15

58 Results Extensive measurements have been made under various conditions: Power supply noise Common mode noise Alien cross talk Channel skew No significant degradation in BER is observed

59 Chip Micrograph and Features Technology 40nm CMOS GP, VDD=0.9V, 10M, DGO Package Wire bond ( mm length), COB Channels 78cm, 55cm & 36cm Rogers (RO4450F/ RO4350B), four 2.4mm connectors, 12 cables, loss up to 15dB IO Cdie 600fF, including ESD Pads Pitch 70µm, bond wire inductance = 1.5nH Data Rate 8-12Gb/s/wire Power and Energy Efficiency 412mW, 4.29 pj/bit at 12Gb/s/wire BER < 8x10-15 at 12 Gb/s/wire 64b-encoder latency, area, power 0.5ns, 2000µm2, 3mW 64b-decoder latency, area, power 0.5ns, 1330µm2, 4mW Differential legacy mode Yes Testability Pattern generators (PRBS31, PRBS9), onchip Eye Scope, error counters, SPI, analog test bus, test software Per wire RX de-skew 1UI

60 Conclusion Successfully designed and tested a 8b8w-Coded SerDes link in 40nm Demonstrated BER performance < up to 12Gb/s/wire Demonstrated receiver circuits that can de-skew up to 1UI and are robust under common-mode and power supply noise conditions Demonstrated approximately 2x advantage in power and eye-opening over legacy differential links at equivalent throughput over same number of wires

61 References [1] D. Slepian, Permutation Modulation Codes, Proceedings of the IEEE, vol. 53, No. 3, , [2] J. Lee, M. Chen, and H. Wang, Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data, JSSC, Vol. 43, No.9, Sep [3] A. Amirkhany, et al, 4.1pJ/b 16Gb/s Coded Differential Bidirectional Parallel Electrical Link, ISSCC Dig. Tech. Papers, pp , Feb [4] H. Cronie, A. Shokrollahi, and A. Tajalli, "Methods and Systems for Noise Resilient and Low Power Communications with Sparse Signaling Codes," US Patent Application Number US2012/ A1. [5] S. Zogopoulos and W. Namgoong High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding, JSSC, Vol. 44, No.2, Feb

62 Thank you