THE power/ground line noise due to the parasitic inductance

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1 260 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 Noise Suppression Scheme for Gigabit-Scale and Gigabyte/s Data-Rate LSI s Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, and Kazunori Ohuchi Abstract In order to reduce the power/ground noise due to the off-chip parasitic inductance and realize gigabit-scale and ultra-high bandwidth large scale integrations (LSI s), this paper proposes two new techniques: 1) a constant-current voltagedown converter (VDC) which reduces the differential mode noise caused by internal peak current in a chip, and 2) a partially inverted data bus architecture which suppresses the commonmode noise caused by driving a large amount of output buffers. The new VDC requires almost constant current through an external V dd =V ss pin in spite of an internal large peak current, resulting in the suppression of the inductance induced voltage bounce and oscillation. Using the new VDC, the power/ground noise in a 1-Gb DRAM is reduced to 20% of the conventional one. The new bus architecture reduces the common-mode noise to 1=n by inverting output bus data partially, using only n 0 1 bit flag signals. Moreover, the modified new bus architecture reduces the noise to 1=2n by using only n bit flag signals. These architectures achieve the ultra-high data transfer rate of 16 GB/s to 32 GB/s. Index Terms CMOS integrated circuits, high-speed bus, interchip communication. I. INTRODUCTION THE power/ground line noise due to the parasitic inductance of a package and a print circuit board (PCB) is a serious problem in the realization of gigabit-scale and ultrahigh bandwidth large scale integrations (LSI s). The noise consists of 1) the differential (or normal) mode noise and 2) the common-mode noise [1]. The internal peak current in a chip causes the differential mode noise of the power/ground line and also causes an oscillation problem. This noise increases by the increase of LSI density and becomes serious in low voltage gigabit-scale LSI s. The common-mode noise is caused by simultaneous switching of the output buffers. It becomes larger with wider I/O s and higher operating frequency. Therefore, in the conventional interface techniques, the bandwidth of chipto-chip communication is limited to 500 MB/s to 1.6 GB/s [2], [3]. A low-voltage differential signaling (LVDS) [4] and emitter coupled logic (ECL) interface [5], in which the paired signals of 1 and 0 data are used for each output data, have excellent noise immunity. However, they double I/O pin counts. This paper proposes two new techniques [6]: 1) a new voltage-down converter (VDC), a constant-current VDC, which reduces the differential mode noise and overcomes the oscillation problem, and 2) a new interface technique, a partially inverted data bus architecture, which suppresses the Manuscript received March 7, 1997; revised June 19, The authors are with the Advanced Semiconductor Devices Research Laboratories, Research and Development Center, Toshiba Corporation, Yokohama 235, Japan. Publisher Item Identifier S (98) Fig. 1. Circuit diagram of a VDC: the conventional VDC and the proposed constant-current VDC. common-mode noise using a few additional flag signals. In Section II, the concept of the new VDC is presented, and the voltage bounce of power/ground line in a 1-Gb DRAM is evaluated. In Section III, first, the concept of new bus architecture is presented. Second, the detailed circuit design of a 128-b I/O is shown. Third, the performance of the proposed bus with wide 128- and 256-b I/O s at 400 MHz or 1 GHz operation is demonstrated. Fourth, the modified bus architecture is also presented and evaluated. Finally, two system configurations using the proposed bus are discussed. Section IV summarizes the results of this work. II. CONSTANT-CURRENT VOLTAGE-DOWN CONVERTER A. Concept In conventional LSI s, and especially in DRAM s, a VDC has been widely used for realizing low power dissipation and for the device reliability [7], [8]. Fig. 1 shows the concept of the new constant-current VDC. In the conventional VDC, the voltage regulator is in between an internal circuit and a power source as shown in Fig. 1. When large peak current is dissipated in the internal circuit, keeping the internal lowered voltage constant, the same amount of peak current flows through a PMOS driver of the VDC and an external pin. It results in large bounce of an internal power/ground line in a chip. On the other hand, in the proposed VDC, a constant current source circuit and a capacitor tank are implemented between the conventional voltage regulator and power source as shown in /98$ IEEE

2 TAKASHIMA et al.: NOISE SUPPRESSION SCHEME FOR GIGABIT-SCALE AND GIGABYTE/S DATA-RATE LSI S 261 Fig. 3. Internal power/ground line (V dd1 =V ss1 ) bounce versus the number of V dd =V ss pins. Fig. 4. External V dd dependency of the internal lowered V int and internal ground V ss1 bounces. Fig. 2. Simulated waveforms of bit-line charging/discharging operation in a 1-Gb DRAM: using the conventional VDC and using the proposed VDC. Fig. 1. The PMOS transistor in the constant current source circuit is operated with saturation region and supplies the constant current. When the large peak current is dissipated in the internal circuit, the external current is limited by the constant current source, and the charge is substantially supplied from the. When the internal current becomes small, the is charged again via the constant current source circuit. Therefore, the external current is kept constant. It results in the elimination of an inductance induced voltage bounce and an oscillation [8], [9]. B. Results and Discussions The simulated waveforms of the bit-line charging/discharging operation in a 1-Gb DRAM using the conventional and the proposed VDC s are shown in Fig. 2, where the pins, parasitic inductance of 10 nh per pin, of 2.5 V, of 1.5 V are assumed. Also assumed are 16 K refresh operation at room temperature using m channel length NMOS and m channel length PMOS transistors. In the conventional VDC of Fig. 2, corresponding to the large internal peak current, the external current has the same peak current as the. It results in large voltage bounces of all internal power/ground lines, and and all internal signal nodes such as word line (WL) and bit line (BL). This noise causes the fatal operations such as the wrong signal fetch in the input buffers. On the other hand, in spite of the internal peak current in the active cycle, the proposed VDC of Fig. 2 flattens the external current and causes almost constant to flow through the external pin even during the standby cycle in order to fill up the capacitor tank. It results in small voltage bounces of all internal power/ground lines and signal nodes. Although the proposed VDC requires the capacitor tank of 12 nf in a 1-Gb DRAM, it occupies only 0.35% area in a chip. Fig. 3 shows the internal power/ground line bounce versus the number of pins, where three refresh operations of 8 K, 16 K, and 32 K cycles are taken as a parameter. In the conventional VDC, the large number of pins are required to ensure stable operation, especially in the 8 K refresh operation. On the other hand, the proposed VDC reduces bounce to 20% of the conventional one in the case of 8 K refresh and pins. This result enables 1-Gb DRAM implementation with a few pins. Fig. 4 shows the external dependency of the drop of and of the rise of. The voltage bounces of and in the conventional VDC become larger at higher

3 262 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 Fig. 5. Internal power/ground line (V dd1 =V ss1 ) bounce versus the capacitance between V dd1 and V ss1 in the conventional VDC and C tank in the proposed VDC. corresponding to quicker VDC response. On the other hand, in the proposed VDC, the maximum drop of is as small as 0.1 V, and the maximum rise of is as small as 0.07 V in the range of 2.5 V 15%. One concern regarding the proposed VDC is large drop of at low because of the serial connection of the voltage regulator and the constantcurrent source circuit. However, this voltage drop is only 0.1 V larger than the conventional one even at of 1.5 V, as shown in Fig. 4. Another conventional approach [1] to suppress the differential mode noise is to use the large capacitance between the internal and lines in the conventional VDC as shown in the circuit diagram of Fig. 5. However, this approach causes the oscillation problem [8], [9]. Fig. 5 shows the dependency of bounce in the conventional VDC and the dependency of bounce in the new VDC, where cycle time (trc) is taken as a parameter. If the conventional VDC is used, the voltage of power/ground line oscillates due to the and parasitic inductance. And the value at which the oscillation occurs varies with the cycle time (trc). Therefore, the large of more than 100 nf is required for wide cycle time operation. On the other hand, as shown in the bold line of Fig. 5, the proposed VDC requires small of 12 nf in order to sufficiently reduce bounce, and eliminates the oscillation problem because of the constant external current. There are two conventional VDC s using the phase compensation techniques: 1) using the capacitor between the and the [8] and 2) using the capacitor between and the gate node of PMOS driver in the VDC [9]. Although these schemes suppress the oscillation due to the feedback loops of VDC, they stabilize only the voltage difference between and. Therefore, it cannot completely eliminate the bounce and the oscillation of induced by the parasitic inductance. III. PARTIALLY INVERTED DATA BUS ARCHITECTURE A. Concept Fig. 6 shows the concept of the partially inverted data bus architecture. In the conventional data bus of Fig. 6, (c) Fig. 6. Concept of the partially inverted data bus architecture: the conventional data bus, proposed data bus, and (c) output data dependence of switching noise. the increase of switching buffers causes a large amount of common-mode noise. This noise strongly depends on the output data of output buffers [10], [11]. Here, we define value as follows: (number of 1 data) (number of 0 data) in the bit bus. (1) The noise in the bit bus becomes larger when is larger. And it becomes maximum when all data are 1 or 0, that is,, as shown in Fig. 6. The simplified model for this reason is shown in Fig. 6(c). When all output data are 1, all charging currents of bus lines are supplied both from pin and from pin via the capacitor. It results in the largest noise in the power/ground line. On the other hand, when is zero, that is, output data of half bits are 1 and those of the rest are 0. The charging current of 1 data and the discharging current of 0 data compensate each other using the internal capacitor. Therefore, there is no large external peak current. The proposed bus shown in Fig. 6 reduces the noise by reducing the maximum value. In a sender chip, first, bit data are divided into segments, Segment 0 and Segment 1, as shown in Fig. 6. Second, in each segment of bit, value is calculated. Third, when is larger than zero or is not larger than zero at both segments, that is, 1 data or 0 data are dominant at both segments, all data of Segment 1 are inverted in order to reduce value and are transferred to the data bus with an inversion flag signal. A receiver chip recreates the original data using the flag signal. For example,

4 TAKASHIMA et al.: NOISE SUPPRESSION SCHEME FOR GIGABIT-SCALE AND GIGABYTE/S DATA-RATE LSI S 263 Fig. 7. Block diagram of the proposed bus architecture of 128-b bus with four segments. when all data in the 128-b bus are 1 as shown in Fig. 6, all Segment 1 data are inverted, and the sender chip transfers all 1 data of Segment 0, all 0 data of Segment 1 and the flag signal of 1 data, which denotes Segment 1 data are inverted. The receiver chip recreates the original data of Segment 1 using the flag signal. The of the proposed bus becomes maximum when of Segment 0 is 64, and of Segment 1 is zero because the total value is not changed whether Segment 1 data are inverted or not. Therefore, the proposed bus reduces the maximum to 1/2 of the conventional one as described by the following expression: (number of 1 data) (number of 0 data) (2) Strictly speaking, the switching noise occurs when output data are changed from 1 to 0 data or from 0 to 1 data. However, the following expression (3) is derived from (2) considering that (2) is satisfied for both the current data and the previous data (see Appendix A): (number of 0 to 1 data) (number of 1 to 0 data) (3) This result lets us choose the I/O circuit design using not (3) but (2), because the circuit using (2) considers only the current output data. B. Circuit Design of 128-b Bus Fig. 7 shows the block diagram of the proposed bus architecture for 128-b bus with four segments. The sender chip divides 128-b data into four segments and executes the following data processing. Each 32-b comparator (Comp32) calculates and outputs and (where becomes 1 when in each segment). The flag signal becomes 1 when or at both segments, Segment 0 and Segment 1. The flag signal also becomes 1 when or at both segments, Segment 2 and Segment 3. In the four cases that Segment 1 data are inverted and not, and Segment 3 data are inverted and not, four 64-b comparators (Comp64) calculate and output and beforehand in parallel. The right data and flag signals are selected by and using the multiplexer. The flag signal becomes 1 when or at both segments, Segments 0 1 and Segments 2 3. This partially inverted bus data is transferred to the receiver chip with 3-b flag signals, each of which denotes whether Segment 1, Segment 2, and Segment 3 data are inverted or not, respectively. The receiver chip recreates the original data using these 3-b flag signals. The worst data of the proposed bus is at Segment 0 and at Segment 1, Segment 2, and Segment 3. In the case of bit bus with segments, the new architecture reduces the maximum value to using only bit flag signals. The key issue for implementation of the proposed bus architecture is how to design the high speed and small size data comparator. Fig. 8 shows the 64-b data comparator using an analog circuit. The 64-b data to are input into the left side. The complementary 64-b data to are input into the right side. When 1 data are dominant, the sensing node becomes lower than the sensing node. The voltage difference of the two nodes is amplified by the sense amplifier. The 64-b data comparison is done with only 1.6 ns, and total data processing in Fig. 7 is 2.5 ns at of 1.5 V. The 2.5-ns delay time meets 400-MHz synchronous DRAM operation with one clock cycle delay (Latency 1). Moreover, the parallel processing using plural units of the proposed data processing enables higher operation frequency of the gigahertz range. The total dissipation current of the eight comparators in Fig. 7 is 2 ma. Although the CMOS-type comparator using

5 264 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 Fig. 8. A 64-b CMOS analog data comparator. pull-up PMOS and pull-down NMOS transistors in Fig. 8 doubles the voltage difference between two sensing nodes and, whereas the current mirror-type comparator using the PMOS load and NMOS pull-down transistors does not, the analog comparator may output a wrong value when is very small. However, in this case, the common-mode noise in the output buffers is small whether segment data are inverted or not. The simulated voltage difference between two sensing nodes in the 64-b comparator is 30 mv to 120 mv when is not larger than two. C. Performance Fig. 9 shows the simulated waveforms of a 128-b data bus in the conventional and the proposed bus architectures. In both of the architectures, the pins for the output buffers are separated from pins for the internal circuit, and one pin and one pin are equipped per four I/O s, where the parasitic inductance of 10 nh per pin and 0.3 nh of PCB are assumed. The impedancematched, center-tapped, doubly terminated, and point-to-point transmission line with small 500 mv signal swing are also assumed [4], [12]. The driver transistor sizes of the output buffer are designed to be m/ m for PMOS transistor and m/ m for NMOS transistor, assuming 0.18 m rule 1-Gb DRAM. The waveforms of Fig. 9 show the, the, and the transmitting data in the output buffers at 400 MHz and 1 GHz operations at room temperature, where the transmitting data shows waveforms in the worst case that all output data have the same data pattern except that only one bit has the reverse data. In the conventional bus, the wide 128-b data bus causes large bounces of internal line for the output buffers. This line noise causes a large center voltage shift between 1 data and 0 data and a large distortion of the transmission lines, resulting in data transmission error. Moreover, the separated internal power/ground line also bounces via the PCB due to the inductance of PCB of 0.3 nh. It causes the fatal operation in the input buffers. On the other hand, the proposed bus has the small bounce of line and the negligible center voltage shift between 1 and 0 transmission data. This architecture realizes stable operation with wide 128-b I/O s at 1 GHz. Fig. 10 shows the separated internal power/ground line bounce versus the number of I/O s. With the increase of the number of I/O s in the conventional data bus, Fig. 9. Simulated waveforms of 128-b bus: the conventional bus and the proposed bus. Fig. 10. Internal power/ground line (V dd1 =V ss1 ) bounce versus the number of I/O s. the power/ground noise becomes larger. Therefore, the number of I/O s is limited to 16 or 32 b. On the other hand, in the proposed data bus, the power/ground noise is reduced with the increase of the number of segments. Therefore, the proposed data bus realizes wide 128-b I/O s at four segments or 256-b I/O s with eight segments, suppressing the power/ground noise level to less than that of 32-b I/O s in the conventional one. As a result, the data transfer rate of the proposed architecture improves by 8 to 16 times that of the conventional bus. Fig. 11 shows the I/O signal margin at 128-b data bus at 400 MHz and 1 GHz operations, where the half voltage of I/O swing of -axis means the original signal voltage, and the signal margin of -axis means the minimum signal voltage during the valid time, which is defined as the time range of 30 to 70% in a burst cycle time as shown in upper side waveforms of Fig. 11. In the conventional data bus, the large center voltage shift between 1 and 0 data and the ringing of the transmission line cause a large signal degradation of transmitting data. On the other hand, in the proposed data bus, the center voltage shift and ringing are suppressed. As a result, the proposed data bus realizes 1-GHz operation with small 300-mV signal swing. Although the power dissipation of 128-b I/O s at 1 GHz with 300-mV signal swing becomes 2.36 W, the termination current reduction techniques such

6 TAKASHIMA et al.: NOISE SUPPRESSION SCHEME FOR GIGABIT-SCALE AND GIGABYTE/S DATA-RATE LSI S 265 Fig. 12. Block diagram of the proposed modified data bus architecture of a 128-b bus with two segments. Fig. 11. I/O signal margin versus a half voltage of the original I/O swing in a 128-b bus with 400 MHz operation and 1 GHz operation. as a dynamic termination [13] reduces power dissipation to 0.44 W. In the practical chip, in order to achieve a data transfer rate of multi-gb/s range, not only the proposed high bandwidth interface technique should be introduced, but also many techniques to realize high data transfer rate between cell arrays and I/O buffers using the global data-line architecture [14], [15] and to minimize the clock and data skews using phase locked loops (PLL s) or delay locked loops (DLL s) [2], [16]. D. Modified Data Bus Architecture A bus-invert coding (or low-weight coding) technique [17], [18], in which all data in the bus are inverted, has been already reported. This scheme also reduces the noise as well as power dissipation. However, it is difficult to reduce the noise to less than 50%. By combining the proposed partially inverted bus scheme with the above all-data inversion scheme, we obtain the modified data bus architecture, which reduces the noise effectively with a few flag signals. Fig. 12 shows the block diagram of the modified data bus architecture for a 128-b bus with two segments. In the sender chip, the following two kinds of data processings are done. 1) Partial data inversion: Using two 64-b data comparators (Comp64), the flag signal decides whether Segment 1 data are inverted or not. From (2), this data processing reduces value to less than using one flag signal. 2) All data inversion: In this processing, all bus data are inverted in order to keep the value larger than zero. The flag signal determines whether all 128-b data are inverted or not using a 128-b comparator (Comp128). The output data satisfy the following expression by these two data processings: (number of 1 data) (number of 0 data) (4) The following expression (5) is also derived from (4) considering that (4) is satisfied for both the current data and the previous data (see Appendix B): (number of 0 to 1 data) (number of 1 to 0 data) (5) In the case of bit bus with segments, the modified data bus architecture reduces the maximum value to using only bit flag signals. Fig. 13 shows the simulated internal power/ground line bounce versus the number of flag signals, assuming 128-b I/O s and 400-MHz operation. The modified data bus architecture achieves the smallest noise based on the same number of flag signals. E. Two Configurations of MPU-DRAM Interfaces Fig. 14 shows two system configurations of the proposed modified bus architecture. In configuration, MPU and

7 266 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 Fig. 13. Internal power/ground line (V dd1 =V ss1 ) bounce versus the number of flag signals. DRAM chips are interconnected with bidirectional 128-b bus and 2-b flags. Each chip has the proposed I/O buffers. In the bidirectional data transfers, the sender chip transfers the proposed encoded data, and the receiver chip decodes the encoded data. By introducing the analog comparators, the chip size penalty of the proposed I/O buffers is only 0.4% assuming 500 mm 1-Gb DRAM. In configuration, only the MPU chip is equipped with the proposed I/O buffers, and the DRAM chip is equipped with the conventional I/O buffers of 128 b plus 2 b and an additional 16-Mb flag memory. In the write operation, the MPU chip transfers encoded data to the DRAM chip, and the DRAM chip stores the encoded bus data and the flag information without the decode processing. In the read operation, the DRAM chip transfers stored encoded data and flag information to the MPU chip directly, without the latency of 2.5 ns due to the data processing, whereas it takes 1.6% chip size overhead for 16-Mb flag memory equipment. IV. CONCLUSION A new constant-current VDC and a new partially inverted data bus architecture for realizing gigabit scale and gigabyte/s data transfer rate LSI s have been proposed. The new VDC flattens an external power/ground pin current and reduces the differential mode noise to 20% of the conventional one in a 1-Gb DRAM. The new bus architecture reduces the difference between the number of 1 output data and that of 0 output data by inverting output data partially. The proposed bus reduces the common-mode noise to using only bit flag signals, and the modified bus reduces the noise to using bit flags. They realize the chip-to-chip communication of 16 to 32 GB/s data transfer rate. APPENDIX A The following two expressions are obtained under the condition that (2) is satisfied for both the current data Fig. 14. Two system configurations of the proposed modified data bus architecture. and previous data in the bit bus: and (A1) (A2) where and are defined as the number of 1 data and that of 0 data in the previous data, and and are defined as the number of 1 data and that of 0 data in the current data. Adding (A1) and (A2) and respectively (A3) can be divided into the following two terms, the number of 0 to 1 data that of 1 to 1 data the number of 1 to 0 data that of 1 to 1 data the number of 0 to 0 data that of 0 to 1 data the number of 0 to 0 data that of 1 to 0 data. We obtain (3) by substituting (A4) (A7) into (A3). (A4) (A5) (A6) (A7) (number of 0 to 1 data) (number of 1 to 0 data) (3) APPENDIX B The following two expressions are obtained under the condition that (4) is satisfied for both the current data and previous data in the bit bus: (B1)

8 TAKASHIMA et al.: NOISE SUPPRESSION SCHEME FOR GIGABIT-SCALE AND GIGABYTE/S DATA-RATE LSI S 267 and (B2) where and are defined in Appendix A. Adding (B1) and (B2) (B3) As and can be divided into two terms as shown in Appendix A, we obtain (5) by substituting (A4) (A7) into (B3) (number of 0 to 1 data) (number of 1 to 0 data) (5) ACKNOWLEDGMENT The authors would like to thank A. Hojo, J. Matsunaga, and A. Toriumi for their encouragement throughout this work. REFERENCES [1] H. B. Bakoglu, Circuits, interconnections, and packaging for VLSI. Reading, MA: Addison-Wesley, ch. 7, [2] N. Kushiyama et al., A 500-Megabyte/s data-rate 4.5 M DRAM, IEEE J. Solid-State Circuits, vol. 28, pp , Apr [3] Y. Nitta et al., A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture, in ISSCC Dig. Tech. Papers, Feb. 1996, pp [4] R. C. Fross et al., Fast interfaces for DRAM s, IEEE Spectrum, vol. 29, no. 10, pp , Oct [5] T. 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Papers, June 1996, pp Daisaburo Takashima was born in Ishikawa, Japan, on October 21, He received the B.E. and M.E. degrees in electrical and electronics engineering from Sophia University, Tokyo, Japan, in 1985 and 1987, respectively. In 1987 he joined the ULSI Research Laboratories, Research and Development Center, Toshiba Corporation, Kawasaki, Japan. Since then he has been working on the circuit design of highdensity DRAM s. In 1997, he joined the Advanced Semiconductor Devices Research Laboratories, Research and Development Center, Yokohama, Japan. Mr. Takashima is a member of the Institute of Electronic, Information and Communication Engineers of Japan. Yukihito Oowaki was born in Kagoshima, Japan, on December 19, He received the B.E. and M.E. degrees in applied physics from the University of Tokyo, Japan, 1981 and 1983, respectively. In 1983 he joined the Toshiba Research and Development Center, Toshiba Corporation, Kawasaki, Japan, where he worked on the development of 1- Mb DRAM s. Since then he has been engaged in the research and development of submicrometer CMOS DRAM s. He also worked on high-speed CMOS device technology and device modeling. In 1992 and 1993 he was a Visiting Scholar at the Cavendosh Laboratory, University of Cambridge, Cambridge, U.K., where he was engaged in research in the field of mesoscopic devices. His present interests include application-specific memories, embedded memories, new memory cell structure, and application of mesoscopic devices. Mr. Oowaki is a member of the Physics Society of Japan. Shigeyoshi Watanabe was born in Mie, Japan, on March 19, He received the B.E. degree in instrumental engineering from Keio University in 1977 and the M.S. degree in applied physics from Tokyo Institute of Technology, Tokyo, Japan, in In 1979 he joined the Semiconductor Device Engineering Laboratory of Toshiba Corporation, Kawasaki, Japan. Since then he has been working on the circuit design of MOS memories, including dynamic RAM, EPROM, and EEPROM. He is currently managing the MOS LSI Memory Research Group at the Toshiba ULSI Research Center, Kawasaki, Japan. Kazunori Ohuchi was born in Tochigi, Japan, in June He received the B.S. degree in electronics engineering from Tohoku University, Sendai, Japan, in In 1970 he joined the Toshiba Research and Development Center, Toshiba Corporation, Kawasaki, Japan. Since then he has been working on the circuit and device design of MOS memories, including EPROM, static RAM, and dynamic RAM. His current interests are in the advanced device structures and circuits for megabit dynamic RAM s and EEPROM s. Mr. Ohuchi is a member of the Institute of Electronic, Information and Communication Engineers of Japan.