TODAY S digital signal processor (DSP) and communication

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1 592 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997 Noise Margin Enhancement in GaAs ROM s Using Current Mode Logic J. F. López, R. Sarmiento, K. Eshraghian, and A. Núñez Abstract Two different techniques that allow the implementation of embedded ROM s using a conventional GaAs MESFET technology are presented. The first approach is based on a novel circuit structure named low leakage current FET circuit (L2FC), which reduces significantly subthreshold currents. The second approach is based on pseudo current mode logic (PCML) which is by far the best choice in terms of noise margin levels. This characteristic is found to be the key factor when implementing GaAs ROM s because of its degradation as the number of word lines is increased. A 5-Kb ROM and a 2-Kb ROM were designed giving delays in the order of 2 ns and less than 1 ns, respectively. The results demonstrate the effectiveness of these techniques and their significance toward improving the noise margin. Index Terms Current-mode logic, Gallium materials/devices, logic design, MESFET integrated circuits, semiconductor memories, very-high-speed integrated circuits. I. INTRODUCTION TODAY S digital signal processor (DSP) and communication circuits demand memories having an ever decreasing cycle time. Placing embedded GaAs memories is crucial in many applications, basically to avoid chip-to-chip delays that occur when the memory is in a separate package. In very large scale integrated (VLSI) systems that require high-speed program control and storage, speed, power dissipation, and chip area have significant influence upon the performance of such architectures. Most of the published reports that have considered GaAs ROM s are based on new process technologies developed specifically for memory design [1] [3]. These processes impose separate chips for the memory, thus they introduce off-chip delays in the systems and hence limit the operating bandwidth. In order to overcome these disadvantages, we present in this paper the implementation of GaAs-based ROM s using a conventional process technology. A conventional GaAs process presents some problems, mainly due to its leaky characteristics and the small output logic swing,, which is in the order of 500 mv. Therefore, circuit options other than the direct-coupled FET logic (DCFL) becomes necessary in order to achieve higher noise margin and low sensitivity as the number of memory word lines is increased. Moreover, the new possibility when combined with structures such as divided word line (DWL) structure [4] Manuscript received November 16, 1995; revised November 15, This work was supported in part by the Comisión Interministerial de Ciencia y Tecnología from Spain (EDGAAS, TIC ) and by the European Community (GARDEN, CHRX-CT ). The work was also supported by the ARC. J. F. López, R. Sarmiento, and A. Núñez are with the Centre for Applied Microelectronics, University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain. K. Eshraghian is with the Department of Computer and Communications Engineering, Edith Cowan University, Perth, Western Australia. Publisher Item Identifier S (97)02475-X. Fig. 1. DCFL inverter. or hierarchical word decoding (HWD) architecture [5], could provide GaAs ROM s having acceptable storage capacities. In Section II, a brief overview of DCFL is presented, as it is the most commonly used logic family. Temperature and leakage current effects are shown in order to illustrate their influence upon logic swing and delay. Section III introduces low leakage current FET circuit (L2FC) as a circuit technique for reduction of leakage current in GaAs ROM s. The use of pseudo current mode logic (PCML) as the basis for implementing ROM s is presented in Section IV. Finally, in Section V, a comparison between the two approaches is presented, and results for 5-Kb and 2-Kb ROM s using Vitesse 0.8 m are given. II. DCFL LIMITATIONS FOR ROM DESIGN The DCFL family shown in Fig. 1 resembles the silicon nmos logic, where a D-MESFET is used as an active load, and E-MESFET s are used to implement the logic functions. Due to the presence of the Schottky diode acting as a clamp at the input of the gate, a reduced logic swing relative to a CMOS technology is obtained which results in shorter signal transition times and therefore permits the realization of higher speed circuits. DCFL is a ratio logic family, which means by adjusting a dimensioning factor,, defined as it becomes possible to obtain satisfactory logic levels and noise margin for different process spreads. In this expression, and represent transistor width and length, respectively, represents pull-up transistors and pull-down. Operation (1) /97$ IEEE

2 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL Fig. 2. Effect of temperature in logic swing. Fig. 3. ID 0 VGS characteristics for an E-MESFET at 25 C. of DCFL is influenced by temperature. An increase in temperature results in an increase in the leakage current, which together with a shift in the threshold voltage degrades the noise margin. A. Temperature Effects The design of ROM s using GaAs MESFET DCFL is a challenging task due to the deterioration of logic voltage swing. The low voltage level of an enhancement/depletion (E/D) inverter is higher than the lowest power supply by more than 100 mv, because the low level is due to the tradeoff between the charge current through the load FET and the discharge current through the driver FET. As the temperature increases, the characteristics of the GaAs MESFET also change. This is shown in Fig. 2 for the case of an inverter. The high level of the output signal falls, the low level rises, and the transient region from high level to low level becomes wide. Therefore, the signal voltage swing becomes small, the transient slope from high level to low level becomes smooth, and the inverter threshold is decreased. The smaller signal voltage swing and the gentler transient slope lead to the decrease of the noise margin. The degradation of the inverter characteristics by an increase in the temperature is a physical phenomenon and little can be done to prevent this degradation. This is one of the most important problems in using E/D-DCFL for memory circuits at high temperature. B. Leakage Current It is well known that in both MOSFET s [6] and MES- FET s [7], small amounts of current continue to flow from source to drain for values below the pinch-off voltage. The basic physical mechanism for subthreshold current, that is thermionic emission/diffusion over a potential barrier, is the same for both MOSFET s and MESFET s. However, due to the larger threshold voltage of typical MOSFET s (700 mv) compared with threshold voltage of 200 mv for E-type MESFET s and the small logic low level obtained by CMOS, a more negative is obtained in the OFF state for CMOS than for DCFL GaAs circuits. Therefore, the observed drain current in the OFF state is five to six orders of magnitude larger than that of the MOSFET s. This implies that the subthreshold leakage current easily dominates circuit operation. As an example, the graphical representation of drain-to-source current versus gate-to-source voltage for an E-MESFET with 10 m width and 1.2 m length is shown in Fig. 3. The dependence of the leakage current with the different voltages is represented by the following expression: where and are fitting parameters. Basically a ROM matrix consists of NOR gates with high fan-in that correspond to the number of word lines, while the output of each NOR gate defines the bit line. The ROM is programmed by the presence or absence of a path between word and bit lines. In such a situation, there are two possible cases, as shown in Fig. 4. The first one represents a logic 1 programming, with a charge current, given by the pull-up transistor to the bit line, represented by. The second case represents a logic 0 programming in the bit line. In both cases, represents the total subthreshold current that flows to through the pull-downs. Thus, the influence of these currents for this kind of architecture is apparent as long as the number of word lines is increased as shown in Fig. 5, where represents the number of transistors contributing to the total leakage current, thus, representing the number of word lines in the core. As can be seen, it is possible to implement DCFL NOR gates with up to eight inputs. However, for larger number of inputs such as 16, no switching is produced because of the total leakage current. A possible solution is the use of a modified [8], where degradation is made slower as fan-in increases. This method permits the doubling of the storage capacity of the ROM compared with the one obtained with a fixed aspect ratio. In the modified approach, we have proposed a new variable (2)

3 594 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997 Fig. 4. ROM programmation. Fig. 5. Logic swing variations versus fan-in (N +1) for NOR gates. Fig inputs L2FC NOR gate. aspect ratio, modulated by the number of word lines, so that as this number increases, the aspect ratio decreases. Although significant improvements are encountered in the noise margin when applying this approach, it is still influenced by the fan-in. Fig. 6. L2FC inverter and layout. III. LOW LEAKAGE CURRENT FET CIRCUIT (L2FC) Low leakage current FET circuit (L2FC) presents as its main advantage a low noise margin sensitivity with fan-in. It is based on placing the input transistors with such a low when they are in cutoff region that leakage currents are almost negligible. As it was shown in Fig. 3, for the gate-to-source voltage,, below the threshold voltage, (210 mv for E- MESFET in H-GaAs II process), a current in the order of a few A continues to flow. If the MESFET is operated with negative values for instead of positive values, it becomes possible to significantly reduce the leakage currents. Such an approach is shown in Fig. 6. When is logic high ( 1.35 V), is ON. Due to the voltage drop of 100 mv produced through, node is placed at 1.9 V. As in is approximately 0.55 V, this transistor is also ON, and therefore, will be at

4 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL Fig. 8. N-input PCML NOR gate. Application to ROM s and layout. logic low. If changes to logic low state ( 1.9 V), will be OFF, and most of the current from the current source will flow to bus through diode, producing a voltage drop, and hence placing of at a negative voltage. on this circuit is degraded still producing leakage currents on the gate of the transistor it is driving. However, this fact does not affect the performance of the memory since it is a transistor located outside the core of the memory and hence, not strongly affected by leakage currents as is the case for high fan-in NOR gates. This approach allows us to implement ROM s with up to 256 word lines and perfect switching in a range of temperature from 0 Cto70C as shown in Fig. 7. Noise margin in this case is in the order of 130 mv and remains almost fixed with fan-in increase. However, dispersion in process parameters still affects greatly the noise margin, and hence, alternative solutions are needed. IV. PSEUDO CURRENT MODE LOGIC (PCML) Using DCFL, low noise margin (approximately 120 mv) is the main drawback [9], [10]. This is due to the barrier height of the MESFET Schottky diode, which limits the output voltage swing. Other problems are the large sensitivity of gate delay and noise margin with fan-in, fan-out, and capacitance, as well as the poor temperature stability of the basic gates. Although with L2FC the complexity of the memory cell is increased, it also improves the sensitivity of noise margin with fan-in. However, low noise margin still imposes stringent requirements on threshold uniformity and process variation. This fact has spurred an interest in other solutions that increase the logic swing or alleviate strict process requirements altogether. One of these solutions is based on current mirrors. Fig. 8 illustrates the structure for a ROM based on (PCML) [11]. The operation of this circuit can

5 596 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997 TABLE I COMPARISON OF DELAY SENSITIVITY the internal node, and furthermore ensures is turned OFF when the input goes low. It also provides a means to adjust the inverter s switching threshold. The last stage is essentially a DCFL inverter. For a NOR gate, transistors to can pull up hard on the gate of transistor. This fact causes power dissipation variations and could overdrive the DCFL inverter, causing some degradation in through the source resistance of. However, that is not the case when dealing with ROM applications in which just one input (or none of them if in stand-by state) can be high at any one time. As for the case of DCFL, PCML is also a ratioed logic. Device sizes are usually chosen so that the output can be pulled down to a conveniently low logic-zero voltage. The main advantage of this logic family relies on the stability and high noise margins with fan-in as compared with the other two solutions studied. Fig. 9. Noise Margin characteristics in terms of temperature, parameter dispersion and fan-in for DCFL, L2FC and PCML. be described as follows. When one of the inputs, E-type device for example, is high ( 0.6 V because of the source follower scheme), it functions as a current source since its drain voltage is greater than effective gate voltage ( ) and sources current to the current mirror formed by the two E-type devices and, thus causing the output node to be pulled down. actually reduces the speed and the gain of the circuit, while improving its rejection of temperature and parameter dispersion effects. When the input goes low, is cutoff, which disrupts the pull-down current. D-type device pulls up to the rail. Device serves to discharge V. RESULTS AND DISCUSION A comparison between the two solutions studied in this paper together with that of DCFL is shown in Fig. 9 in terms of noise margin variation with temperature, parameter dispersion, and fan-in. For the case of dispersion, negative values represent a slow process (for example, 3 represents 3 slow process), positive values represent a fast process, and zero value represents a typical process. The restricted noise margin in DCFL is improved using L2FC, where its sensitivity with fan-in is very low. Noise margin for this structure is greatly affected by parameter dispersion, obtaining values below 60 mv for 3 at 25 C. Although PCML is also influenced by dispersion, it is by far the best choice for ROM design because of its higher noise margin, which is above 250 mv for 3 dispersion and because of its low variation with fan-in. It also incurs some power penalty due to larger swing on the world line relative to DCFL, but noise margin limitations do not make DCFL a real contender for large ROM designs. Improved schemes for sensing reduced bit-line voltage swings could increase PCML performance. Two parameters, and, which define the delay sensitivity with temperature and with parasitic capacitance in the bit line are now introduced. is very important since it is related with the length of the bit line and therefore with the number of word lines. These parameters are expressed as follows:

6 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL TABLE II COMPARISON OF PERFORMANCE FOR L2FC AND PCML BASED MEMORIES The values obtained for the different structures, together with the transistor count per primitive cell when implementing ROM s, are given in Table I. It has to be mentioned that when calculating for PCML, the variation of the capacitance has been made at the internal node of the gate, since that node is the one that represents the bit line. For the other two cases, the bit line is represented at the output node of the gate. Once again, PCML provides better performance in all three aspects, thus confirming the choice of this logic family. Taking into account all these considerations, a 5 Kb and a 2 Kb ROM were designed using L2FC and PCML, respectively. In order to reduce bit-line capacitances and hence delay, the memories were partitioned in four blocks for the first one and in two for the second. The performance of the two L2FC and PCML based memories are given in Table II for a typical case. VI. CONCLUSIONS The performance of a high-speed control-driven processor depends greatly on how fast instructions and data are obtained from SRAM s. This is even truer for application-specific dedicated processors, coprocessors, and other dataflow dominated computations for which fast ROM s are also required. As GaAs technology matures, its real merits are becoming clear because of a better understanding of the physics, circuit theory, experimental results, and products. This technology is found to be a good choice in order to get the bandwidth requirements needed by current and future processors. This work illustrates the method whereby a conventional GaAs E/D process can be utilized to realize high-performance ROM s just by dealing with circuit design aspects permitting inclusion of dense onchip GaAs ROM s. The use of PCML in GaAs ROM s has been shown to be an effective choice for the design of a ROM when the aim is obtaining high noise margin and low sensitivity with fan-in. REFERENCES [1] J. Chun, R. Eden, A. Fiedler, D. Kang, and L. Yeung, A 1.2 ns GaAs 4K read only memory, in Proc. IEEE GaAs IC Symp., 1988, pp [2] M. Ino, H. Suto, N. Kato, and H. Yamazaki, A 1.2 ns GaAs 4kb readonly-memory fabricated by 0.5 m-gate BP-SAINT, in Proc. IEEE GaAs IC Symp., 1987, pp [3] J. Chun, S. Enam, D. Kang, and B. Remund, A pipelined 650 MHz GaAs 8K ROM with translation logic, in Proc. IEEE GaAs IC Symp., 1990, pp [4] M. Yoshimoto et al., A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM, IEEE J. Solid-State Circuits, vol. SC-18, pp , Oct [5] T. Hirose et al., A 20 ns, 4-Mb CMOS SRAM with hierarchical word decoding architecture, IEEE J. Solid-State Circuits, vol. 25, pp , Oct [6] R. R. Troutman, Subthreshold design considerations for insulated gate field-effect transistors, IEEE J. Solid-State Circuits, vol. SC-9, pp , Apr [7] S. J. Lee et al., Ultra-low power, high speed GaAs 256 bit static RAM, in IEEE GaAs IC Symp., 1983, pp [8] J. F. López, K. Eshraghian, M. K. McGeever, A. Núñez, and R. Sarmiento, Gallium arsenide MESFET memory architectures, in IEEE Int. Workshop on Memory Technology, Design and Testing, San Jose, CA, Aug. 1995, pp [9] S. I. Long and M. Sundaram, Noise-margin limitations on galliumarsenide VLSI, IEEE J. Solid-State Circuits, vol. 23, pp , Aug [10] S. I. Long and S. E. Butner, Gallium Arsenide Digital Integrated Circuit Design. New York: McGraw-Hill, [11] R. A. Duncan, K. C. Smith, and A. S. Sedra, Gallium-arsenide pseudo current mode logic, Electron. Lett., no. 25, pp , Dec