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1 343 Comparison of different design techniques of XOR & AND gate using EDA simulation tool RAZIA SULTANA 1, * JAGANNATH SAMANTA 1 M.TECH-STUDENT, ECE, Haldia Institute of Technology, Haldia, INDIA ECE, Haldia Institute of Technology, Haldia, INDIA 1 razia4@gmail.com, jagannath196@gmail.com ABSTRACT XOR & AND gates are most important basic building blocks of any VLSI applications. These gates can be implemented in different architectures by using different circuit designs techniques. This paper evaluates and compares the performance of various design techniques of XOR-AND gates. The performances of these techniques have been evaluated by Tanner Tools V13 using the 9nm CMOS technology. In this work, XOR & AND gates can be implemented using seven different logic design techniques i.e. Standard CMOS logic, logic, logic, logic, DVL logic, GDI logic and Domino logic. The XOR gates with design are suitable for arithmetic gates and other VLSI applications with very low power consumption and a very high speed performance and the AND gate GDI design has better performance than other design techniques. Keywords: Exclusive-OR, AND gate, High speed, Low power, Pass-Transistor Logic, Delay, PDP 1. INTRODUCTION The demand for low power VLSI is increasing day by day at different levels such as process technology level, architectural level, circuit and layout level. At the circuit design level, considerable potential for power savings exists by means of proper choice of a logic style for implementing combinational gates. This is because all the important parameters like power dissipation, area, delay are strongly influenced by the chosen logic style. Moreover, the explosive growth driving the designers to strive for smaller silicon area, higher speeds, longer battery life, and more reliability. Power is one of the premium resources a designer tries to save when designing a system. The XOR-AND gates are basic building blocks in various circuit especially-arithmetic gates (full adder, and multipliers), Compressors, Comparators, Parity Checkers, Code converters, Error-detecting or Errorcorrecting codes, and Phase detector. The performance of the complex logic gates is affected by the individual performance of the XOR-AND gates that are included in them [1-3]. Therefore, careful design and analysis is required for XOR-AND gates to obtained full output voltage swing, lesser power consumption and delay in the critical path. Additionally, the design should have a lesser number of transistors to implement XOR- ANDgates. In this work, XOR & AND gates can be implemented using seven different logic design techniques i.e. Standard CMOS logic, logic, logic, logic, DVL logic, GDI logic and Domino logic. The performances of these techniques have been evaluated by Tanner Tools V13 using the 9nm CMOS technology. The rest of the paper is organized as follows. Section II gives the idea on previous work done on XOR and AND gates. Section III gives a short introduction to the various XOR and AND gates design and compares them qualitatively. Results of quantitative comparisons based on simulations of different design techniques are shown in Section IV. In section V, the results are discussed and the paper is concluded in Section VI.. PREVIOUS WORK In the past two decades, a number of circuit techniques have been reported with a view to improve the circuit performance of XOR-AND gates [1-9]. In this section we have presented an overview of some significant techniques. A wide variety of XOR-AND implementations are available to serve different speed and density requirements. Instead of cascading two -input XOR gates, a new design for 3-input XOR circuit is given in [5]. The reported circuit has the least number of transistors and no complementary input signals are needed. Especially, the power-delay product is also minimized. A based 4-transitors XOR gates presented in [5].The Pass-Transistor Logic () is a better way to implement gates designed for low power applications. The advantage of is that only one network (either NMOS or PMOS) is sufficient to perform the logic operation, which results in smaller number of transistors and smaller input loads, especially when NMOS network is used. Moreover, VDD-to- GND paths, which may lead to short-circuit energy dissipation, are eliminated. These gates have a non-full voltage swing at the output node and are characterized by its low power consumption. And it has better power-delay product than other techniques. Many circuit implementations have been proposed in the literature.some of the main advantages of over standard CMOS design are 1) high speed, due to the small node capacitances; ) low power dissipation, as a result of the reduced number of transistors; and 3) lower interconnection effects due to a small area. However, most of the implementations have two basic problems. First, the threshold drop across the single-channel pass transistors results in the

2 344 reduced current drive and hence slower operation at reduced supply voltages. There are many sorts of techniques such as Transmission gate CMOS (TG), Complementary pass-transistor logic () and Double pass-transistor logic () that intend to solve the problems. Another low-power design technique is the gate diffusion input (GDI) technique. The GDI based - transistor AND circuit presented in [6]. This method is suitable for design of fast, low-power gates, using a reduced number of transistors, while improving logic level swing and static power characteristics. Different types of design techniques to implement the XOR and AND gates are discussed in the next section. 3. VARIOUS DESIGN TECHNIQUES FOR XOR & AND GATES 3.1. Static CMOS XOR and AND gates Static CMOS uses dual networks to implement a given function [1-3]. A first part consists solely of complementary pull-up PMOS network while a second part consists of pull-down NMOS networks. The advantage of this technique is that it gives full output swing i.e.; no threshold loss but on the other side it has many shortcomings such as more area because of more number of CMOS transistors required to design a gate, large power consumption and less speed. Static CMOS XOR and the AND gate is shown in Fig.1(a) and Fig.1(b). Fig.1: (a) Static CMOS XOR (b) Static CMOS AND gates 3.. based XOR and ANDgates differs from static CMOS is that the source side of the MOS transistor is connected to an input line instead of being connected to power lines. Another important difference is that only one network (either NMOS or PMOS) is sufficient to perform the logic operation. XOR-AND gates of the pass transistor logic style are shown in Fig(a, b, c,d).the advantage of is that only one network (either NMOS or PMOS) is sufficient to perform the logic operation, which results in smaller number of transistors and smaller input loads, especially when NMOS network is used. Fig: (a, b, c) XOR gates (d) AND gates For XOR circuit in Fig. (a), when the input B is at logic 1, the inverter circuit functions like a normal CMOS inverter. Therefore the output is the complement of input A. When the input B is at logic, the CMOS inverter output is at high impedance. However, the PMOS pass transistor is ON and the output gets the same logic value as input A. The operation of the whole circuit is thus like a -input XOR circuit. However, it performs non fullswing operations for some input patterns causing their corresponding outputs to be degraded by Vth. For A = 1 and B =, voltage degradation due to threshold drop occurs across transistor and consequently the output is degraded with respect to the input. The XOR gate respectively in Fig. (b) and has degraded output voltage swing, limited driving capability and is characterized by low power consumption. The circuits in Fig. (c) has provides good output levels and the driving capability of the circuits is also improved as it uses static CMOS inverter. The main limitation of the circuits is extra power consumption due to the presence of the static CMOS inverter. -transistors AND circuit using logic is shown in Fig. (b). When A is at logic, B is at logic and A is, B is 1 respectively, PMOS transistor is ON and NMOS is OFF and as PMOS is weak device, it will pass incomplete logic low signal to the output. With both the inputs stated above A is constantly zero but B is changing its state from to 1.When A is logic 1 and is B logic, PMOS transistor is OFF and NMOS is ON, and as NMOS is strong device, it will pass complete logic low signal to the output and when A is logic 1 and B is logic 1, PMOS transistor is OFF and NMOS is ON, and due to NMOS is weak 1 device,

3 345 output will be charged to incomplete logic high. This gate has better performance in the terms of power consumption with increasing input voltage based XOR and AND gate The was significant in the fact that it was based on the use of the pass transistor networks. benefits from the small input capacitances (NMOS network only), the fast differential stage, and the good output driving capability (output inverter), making the implementation of complex gates very efficient. On the other hand, the large number of nodes and transistors and the two inversion levels result in relatively inefficient implementations of simple gates. Usually, pull-up PMOS transistors are necessary for swing restoration. Larger short-circuit currents and higher wiring overhead (dual-rail signals) compared to CMOS also increase power consumption. XOR-ANDgates using Complementary pass transistor logic style are shown in Fig.3. Fig3(a): XOR (b) AND gates 3.4. XOR and AND gates: A pass transistor logic attempts to solve the problem of the pass transistor threshold voltage drop exhibited in. therefore represents a pass transistor logic family alternative to. Double pass-transistor logic () uses complementary transistors to keep full swing operation and reduce the dc power consumption. This eliminates the problem of the threshold drop and the use of inverters after each logic blocks. One limitation of is the large area used due to the presence of PMOS transistors. 4-transistors (Double pass-transistor logic) XOR and AND gates are shown in Fig.4 have been design to improve circuit performance at low supply voltages [7]. Fig.4(a): XOR (b) AND gates 3.5. DVL AND Gate A step further in development of is taken in a logic family termed DVL (Dual value logic). The main drawback of is its redundancy, i.e. it requires more transistors than actually needed for the realization of a function. To overcome the problem of redundancy, a new logic family, DVL is derived from. It preserves the full swing operation of with reduced transistor count. As introduced in [8], DVL circuit can be derived from gates in three steps, consisting of: (a) elimination of redundant branches in (b) elimination of branches via signal rearrangement (c) Selection of the faster halves. 3-transistors AND circuit using DVL is shown in Fig.5. Fig5: DVL AND gate

4 GDI based XOR-AND gate GDI (Gate diffusion input) is a low-power digital combinational circuit design technique is based on the use of a simple GDI cell as shown in Fig6.The basic difference between GDI cell and standard CMOS inverter is as follow: Fig6: (n + ) inputs GDI cell. The GDI cell [9] contains three inputs G (common gate input of NMOS and PMOS transistor), P (input to the source/drain of PMOS), and N (input to the source/drain of NMOS).Bulks of both NMOS and PMOS are connected to N or P (respectively), so it can be arbitrarily biased at contrast with a CMOS inverter. This technique allows reducing power consumption, propagation delay, and area of digital gates while maintaining low complexity of logic design. XOR and AND gate using GDI logic is shown in Fig.7 and the output waveforms are shown in Fig.7(a) and Fig.7(b). Fig.7: (a) GDI XOR (b) GDI AND gates 3.7. Domino Logic based XOR-AND gate In this type dynamic CMOS logic, the output is connected with a static CMOS inverter. The addition of this inverter make this dynamic CMOS logic to be cascaded. Here, during pre-charge phase the output of the dynamic CMOS stage is pre-charged to a high logic level and the output of the inverter to a low logic level. According to external inputs, during evaluation, the output of the inverter is restricted to only the transition form to 1, but from logic 1 to is never possible. So, when these logic blocks are cascaded, all input transistor in subsequent logic blocks will be turned off during the pre-charged phase, since all buffer outputs are equal to. During the evaluation phase, each buffer output can make at most one transistor ( to 1) and thus each input of all subsequent logic stages can also make at most one transition. In a cascade structure consisting of several stages, the evaluation of each stages ripples the next stage evaluation, similar to a domino falling one after the other. XOR-AND gates using Domino logic style are shown in Fig.8. Fig.8 (a): Domino logic XOR gate (b) Domino logic AND gate T XOR The early designs of XOR gates were based on either eight transistors or six transistors that are conventionally used in most designs. Over the last decade, considerable emphasis has been laid on the design of four-transistor XOR gate. Fig9(a,b) could operate without requiring complementary inputs which is a severe drawback of CMOS transmission gate logic based XOR gates. Bui, Wang and Jiang further improved the XOR gate

5 347 designed a XOR gate without a VDD shown in Fig.9(c). However, this XOR gates consumed considerable silicon area for their optimum performance and the power delay product is also large. Fig.9 (a, b, c): 4 Transistor XOR gate 3.9. Inverter based XOR Gate Inverter based XOR gate is design by cascading three inverters as shown in Fig.1. The serious limitation of these circuits is non full voltage swing at the internal nodes of the circuit. However, they operate reliably at high supply voltage. Fig.1. Inverter based XOR gate 4. SIMULATION RESULTS AND COMPARISON Various design techniques for XOR and AND gate are compared based on the performance parameters like propagation delay, power dissipation, power delay product (PDP). The channel width of the transistors is.45μm for the NMOS and.9μm for the PMOS in all cases. All the simulations works have been done by Tanner EDA simulation tool for supply voltage 1v using the 9nm CMOS technology. Fig:11(a & b) showing the output waveform of based and Fig.1(a & b) showing the output waveform of GDI based XOR & AND gate from simulation results. Fig11: (a) XOR output waveform for Fig. (a). Fig11: (b) AND output waveform for Fig. (d). Fig1: (a) XOR output waveform for Fig. 8 (a). Fig1 (b): AND output waveform for Fig. 8 (b). Table 1: Comparative performance of various type of XOR gate at 9nm CMOS technology. Sl. No. Logic Styles Complexity Delay (ns) Avg. power PDP(fJ) Consumed (nw) (Fig.a) (Fig.b) (Fig.c) (Fig.3a) (Fig.3b) (Fig.4a) GDI (Fig.7a)

6 348 5 Domino (Fig.8a) T XOR (Fig.9a) T XOR (Fig.9b) T XOR (Fig.9c) Inverter based (Fig.1) Table : Comparative performance of various type of AND gate at 9nm CMOS technology Sl. No. Logic Styles Complexity Delay Avg. power (ns) Consumed (nw) PDP(fJ) 1 (Fig.d) (Fig.3c) (Fig.4b) DVL (Fig.5a) GDI (Fig.7b) Domino (Fig.8b) Complexity of XOR gate Complexity of AND gate No. of trasistors GDI Domino 4-T XOR 4-T XOR 4-T XOR INV No. of Transistors (Fig.d) (Fig.3c) (Fig.4b) DVL (Fig.5a) GDI Domino (Fig.7b) (Fig.8b) (Fig.a) (Fig.b) (Fig.c) (Fig.3a) (Fig.3b) (Fig.4a) (Fig.7a) (Fig.8a) (Fig.9a) (Fig.9b) (Fig.9c) (Fig.1) Fig. 13: Complexity of different design styles of XOR & AND gate Delay analysis of different XOR gates Delay (ns) GDI Domino 4-T 4-T 4-T INV (Fig.a) (Fig.b) (Fig.c) (Fig.3a) (Fig.3b) (Fig.4a) (Fig.7a) (Fig.8a) XOR XOR XOR (Fig.1) (Fig.9a) (Fig.9b) (Fig.9c) Consumed power (nw) (Fig.a) Fig.14: Delay analysis of various types of XOR gate Avg. Power consumed for diffrent XOR gates GDI Domino 4-T 4-T 4-T INV (Fig.b) (Fig.c) (Fig.3a) (Fig.3b) (Fig.4a) (Fig.7a) (Fig.8a) XOR XOR XOR (Fig.1) (Fig.9a) (Fig.9b) (Fig.9c) Fig.15: Avg. power consumption for various type of XOR gate 5 Power Delay Product of various XOR gates PDP (fj) (Fig.a) GDI Domino 4-T 4-T 4-T INV (Fig.b) (Fig.c) (Fig.3a) (Fig.3b) (Fig.4a) (Fig.7a) (Fig.8a) XOR XOR XOR (Fig.1) (Fig.9a) (Fig.9b) (Fig.9c) Fig.16: PDP of various type of XOR gate

7 349 Avg. power consumed of various AND gates PDP of various AND gates Power consumed (nw) (Fig.d) (Fig.3c) (Fig.4b) DVL (Fig.5a) GDI (Fig.7b) Domino (Fig.8b) Fig.17: Avg. power consumption for various type of AND gate Fig.18: PDP of various type of AND gate PDP (fj) (Fig.d) (Fig.3c) (Fig.4b) DVL (Fig.5a) GDI (Fig.7b) Domino (Fig.8b) DISCUSSION After individual discussion of the individual logic style, comparison must be done among them to know which design technique is more optimized and suitable in terms of Average power consumption, Propagation Delay and Power delay product (PDP) for implementation of XOR gate and the AND gate. From the Fig. 13 it is clearly shown that based XOR and the AND gate is better than others in terms of Transistor count or number. But transistor count is not only the single parameter for any implementation in VLSI. We have to consider other parameters like Average power consumption, Propagation delay, Power delay product (PDP). Now let s start with the discussion with respect to Average power consumption for choosing the suitable logic style for XOR and the AND gate implementation. From Fig. 15 it is seen that logic style XOR gate and Fig.17 GDI logic style AND gate gives the lowest average power consumption. The next parameter is Propagation delay. From the Fig.14 it is seen that in logic style XOR gate propagation delay is less. From Fig.16 has been seen that based XOR gates and Fig. 18 the AND gate with GDI design has minimum PDP than other design techniques. CONCLUSION In this paper, we have reviewed various design techniques for XOR-AND gates. The mentioned design techniques are compared based on a delay, power consumption, and PDP. The performances of these techniques have been evaluated by TANNER TOOLS using a 9nm CMOS technology. These design techniques are suitable for arithmetic gates and other VLSI applications with very low power consumption and a very high speed performance. Based on the simulation results, it has been seen that based XOR gates and the AND gate with GDI design has very low power consumption and a minimum PDP than other design techniques. REFERENCES [1] S. Roy Chowdhury, A Banerjee, A. Roy, and H. Saha, A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates, International Journal of Electronics, Gates and Systems, WASET Fall,(8). [] Sung-Mo Kang, Y. Leblibici, CMOS Digital Integrated Gates: Analysis and Design, Addition-TGH(3). [3] K.H. Cheng and C.S. Huang, The novel efficient design of XOR/XNOR function for adder applications, in Proc. IEEE Int. Conf. Elect., Gates Syst., 1: 9-3(1999). [4] W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, Pass transistor logic design, Int. J. Electron vol. 7, pp , [5] Sung-Chuan Fang, Jyh-Ming Wang, Wu-Shiung Feng, A New Direct design for three-input XOR function on the transistor level, IEEE Trans. Gates Syst. I: Fundamental theory and Applications, 43(4): (1996). [6] Km. Deepmala, Prof.B.P.Singh, " New Efficient T and Gate Design International Conference on VLSI, Communication & Instrumentation (ICVCI) 11. [7]H.Lee and G. E.Sobelman, Newlow-voltage gates for XOR and XNOR, in Proc. IEEE Southeastcon, Apr. 1-14, pp. 5-9(1997). [8]V.G. Oklobdzˇija, B. Duchene, Pass-Transistor Dual ValueLogic for Low-Power CMOS, Proceedings of International Symposium on VLSI Technology, Systems, and Applications, May June, 1995, pp [9] A. Morgenshtein, A. Fish, and I. A. Wagner, Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinational Circuits, IEEE Trans. Very Large Scale Integ. Syst. (VLSI), 1(5): ().