DESIGN OF LOW POWER CMOS THREE INPUT XOR/XNOR

Transcription

1 DESIGN OF LOW POWER CMOS THREE INPUT XOR/XNOR D.lakshmaiah 1 (Ph.D),T.sai baba 2 M.Tech,B.sravani #, M. kalyani #, G.priya darshini #, D.shashi kumar # 1 Asso. Professor, 2 Assit.Professor # B.Tech students Christu Jyothi Institute of Technology and Science, Jangaon(Mdl.), Warangal(Dist.)T.S,INDIA Abstract: In this paper, we propose a new threeinput XOR/XNOR circuits to improve the speed and power as these circuits is basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. We start with selecting a basic cell including three independent inputs and two complementary outputs. Next we combine this basic cell with various correction and optimization techniques to build a perfect XOR-XNOR circuit with full swing operation. The performance of the XOR-XNOR circuits based on 90 nm CMOS technology process models at all range of the supply voltage is evaluated by the comparison of the simulation results obtained from MICRO WIND. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs. Key words : Binary Decision Diagram, 3-input XOR/XNOR circuits, CMOS. I.INTRODUCTION While the growth of the electronics market has driven the VLSI industry towards very high integration density and system on chip designs and beyond few GHz operating frequencies, critical concerns have been arising to the severe increase in power consumption and the need to further reduce it. Moreover, with the explosive growth th demand and popularity of portable electronics is driving designers to strive for smaller silicon area, higher speeds, longer battery life, and more reliability. Power is one of the premium resources a designer tries to save when designing a system. The XOR-XNOR circuits are basic building blocks in various circuit especially- Arithmetic circuits (Full adder, and multipliers), Compressors, Comparators, Parity Checkers, Code converters, Error-detecting or Error-correcting codes, and Phase detector circuit in PLL. We focus on XOR XNOR circuits as they are often used to obtain optimized performances for full adders. Balanced XOR XNOR circuits along with multiplexers are also the main components of compressors in parallel multiplication circuits. Also these circuits play an important role in comparator and parity checker blocks. Balanced XOR XNOR circuits, which serve as critical components in balanced complimentary outputs, eliminate power dissipated by the glitches. In any type of logic design, the non full swing outputs play a decisive role in cell weak drivability. Full swing outputs impact multi-stage structured arithmetic circuit performance. Therefore designers consider achieving full swing output operations as an important factor in arithmetic circuit basic block design. The performance of the complex logic circuits is affected by the individual performance of the XOR- XNOR circuits that are included in them [1]-[6]. Therefore, careful design and analysis is required for XOR-XNOR circuits to obtained full output voltage swing, lesser power consumption and delay in the critical path. Additionally, the design should have a lesser number of transistors to implement XOR- XNOR circuits and simultaneous generation of the two non-skewed outputs. In this paper a PTL based XOR and XNOR circuits were considers. Despite the saving in transistor count, the output voltage level is degraded at certain input combinations. The reduction in voltage swing, on one hand, is beneficial

2 to power consumption. On the other hand, this may lead to slow switching in the case of cascaded operation. We propose and compare new XOR- XNOR circuit designs which produce the XOR- XNOR outputs simultaneously with full output voltage swing. The NMOS and PMOS transistors are added to the basic circuits to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. We see many published papers that compete in designing better circuits [7]- [12]. Such studies mostly rely on creative design ideas but do not follow a systematic approach. As a consequence, most of them suffer from some different disadvantages [8]. 1) They are implemented with logic styles that have an incomplete voltage swing in some internal nodes, which leads to static power dissipation. 2) Most of them suffer from severe output signal degradation and cannot sustain lowvoltage operation. 3) They predominantly have dynamic power consumption for nonbalanced propagation delay inside and outside circuits, which results in glitches at the outputs. Therefore, a well-organized design methodology can be regarded as a strong solution for the challenge.cell design methodology (CDM) has been presented to design some limited functions, such as two-input XOR/XNOR and carry inverse carry in the hybrid- CMOS style [13] [15]. The predominant results persuade us to improve CDM through two stages: 1) generating more complex functions and 2) rectifying some remaining flaws. The flaws in previously published CDM include containing some manual steps in the design flow and generating a large number of designs in which the predominant ones would be determined after the completion of simulations. CDM is matured as systematic CDM (SCDM) in designing the three-input XOR/XNORs for the first time. It systematically generates elementary basic cell (EBC) using binary decision diagram (BDD), and wisely chooses circuit components based on a specific target. Therefore, after the systematic generation, the SCDM considers circuit optimization based on our target in three steps: 1) wise selection of the basic cell; 2) wise selection of the amend mechanisms; and 3) transistor sizing. We consider the power-delay product (PDP) as the design target. This method has some advantages. 1. It increases the driving capability and avoids the degradation on the output voltage. 2. It uses only less number of transistors in the critical path which results in less delay and power- delay product(pdp). 3. The dynamic consumption optimization comes from the fact of well-balanced propagation delay. 4. Power-ground-free main structure leads to power reduction. 5. The methodology has high flexibility in target and systematically consider it in the three design steps. This can lead to efficient circuits in terms of performance, power, PDP, EDP, area, or a combination of them. II.EXISTING WORK In this section, we will see the three-input XOR/XNOR circuits to examine their highperformance[16]. In complementary CMOS logic [16], the pull-down and pull-up networks used in the circuit perform the function in a complementary way. It has high noise margin and no static power consumption. In the CMOS with transmission gate,[16]there is a advantage of using less number of transistors. In complementary pass-transistor, it has a good output driving capability and pass-transistor logics gain their speed over the CMOS due to their high logic functionality. The XNOR-XOR circuit by using CMOS transistor and compare it with the proposed design of XNOR-XOR circuit using transmission gate with CMOS inverter circuit. Figure-1[16] shows the XNOR- XOR combine gate using CMOS transistor circuit. There are total sixteen transistors used in which 8 transistors are PMOS and rest are the NMOS transistors. The NMOS transistor can give the LOW signal completely, but it has very poor performance at HIGH signal. Similarly PMOS transistor can gives the HIGH signal completely, but poor performance at LOW signal. The a concept of transmission gates and CMOS inverter[17]. The CMOS inverter is driving the transmission gate to achieve the perfect output voltage swing. P and Q are given as the input of transmission gates through CMOS inverter. Output

3 of transmission gates gives the XNOR output and using an inverter we get the XOR output. The transmission gate allows to passes the signal through it, when the enable signal of transmission gate is high. The transmission gate has a n-channel device and a p-channel device, the n-channel MOS is situated on the bottom of the p-channel MOS. When zero signals apply to the enable (i.e. en) pin the transmission gate is off, and no signal is transferred through it. When enable signal is asserted high, the input signal appears to the output. III. PROPOSED WORK 1. INTRODUCTION OF CELLS In this section we introduce different basic cells which are used as a basis for designing various circuits. To pro-vide better understanding we first introduce the elementary structure, referred to as the elementary basic cell. 2. The Elementary Basic Cell In order to generate the EBC of three-input XOR/XNOR circuits, four steps are taken from. Initially, three-input XOR and its complement is represented by one binary decision tree (BDT) [18] in order to share common sub circuits. The step is followed by applying reduction rules to simplify the BDT representation[19]. These include elimination, merging, and coupling rules. The result of applied reduction rules to the tree is shown in Fig. 1(c). as the inputs into the first level are 0 s and 1 s of the function s truth table, the 0 and 1 can be replaced by the Y and Y, respectively. Then the simplified symbol can be divided into two distinct symbols: 1) the plus sign with the x input control and 2) the minus sign with the x input control. The result of applying steps 3 and 4 is shown in Fig. 1(d). The EBC, which is extracted from the above procedure, has been presented in Fig. 1(e). feedback pull up-down, bootstrap-feedback, inverterfeedback, and inverter-pull up-down]. Introduction of Feedback Networks All circuits with complementary outputs have the ability to optionally determine the state of an output or amplify it through the use of another output and a suitable transistor. Transistor or transistors which are placed between the two outputs to influence the second output through activating the first one, are called feedback networks. This feedback network is placed between the two complementary out-puts and causes the high impedance output states to be eliminated and replaced by the desired levels. Also, it is possible to ensure full swing operation at the outputs. As different basic cell versions presented in this work come with different short comings, the required feedback net-work should be different. We use four different feed back networks and they are: Fp, Fn, Fc and Fnp. Fp is a feedback network using two pmos transistors. Fn is a feedback network with two nmos transistors. Fc is a complementary feedback network and Fnp includes nmos and pmos transistors placed between the two complementary outputs Y and Y. Note that we improve the driving capability of feedback networks as we use VDD and GND connections. MECHANISMS Different mechanisms are optimization mechanisms to resolve non full swing [inverter and feedback ], correction mechanisms to resolve high impedance [pull up-down network and feedback ], or the combinations of them [bootstrap-pull up-down, Pull Up and Pull Down Networks

4 The use of pull up and pull down networks as a means of eliminating the critical states of a circuit is common and has been used in several reports[20]. The high impedance states should be replaced by 0 or 1.One possible solution is to use pull up and pull down networks. When facing output high impedance states, it is possibleto use a pull up network to connect Y or Y to the supply voltage.this results in replacing the high impedance state by logic 1.T o replace a high impedance state with logic 0, a pull down network is used to connect the output to ground. Output Inverters One way to ensure full swing operation at the outputs is to use output inverters. Adding inverters to the original circuit increases the number of transistors, power dissipation, area and the overall delay of the circuit. Meantime using inverters results in signal level restoration but enhances the circuit drive according to transistor sizes. Using this mechanism for the basic cells eliminates the non full swing operation but cannot replace high impedance states. Fig: Cmos Three-input XOR/XNOR circuit I. Bootstrap Technique By placing a boot transistor between the input and the gate terminal of the transistor we shift the gate voltage of the transistor.if the value of this shift is greater than or equal to the threshold transistor voltage (V T ) the transistor can transfer data to the outputs perfectly and there will be no voltage drop due to transistor s threshold voltages. Experimental results and analysis of the circuit reveals that in order to provide the capacitive property and for the boot phenomenon to occur, boot transistors and main transistors should be of the same type. Fig: Cmos Three input XOR/XNOR circuit II. Fig: Cmos Three input XOR/XNOR circuit III. IV.PERFORMANCE AND SIMULATION

5 The performance of our proposed designs of threeinput XOR/XNOR are simulated below. Based on the performance of the proposed designs the power, delay and PDP values are tabulated and compared with the existing circuits power delay 0 Cmos 90nm Cmos 65nm Fig : output waveform of circuit I Fig: power and delay of CMOS circuit I Cmos 90nm Cmos 65nm Power Delay Fig: power and delay of CMOS circuit II Fig: output waveform of circuit II Cmos 90nm Cmos 65nm Power Delay Fig: Power and Delay of CMOS circuit III Fig: output waveform of circuit III The performance results show that the feedback networks are better to produce full output swing.

6 TABLE : COMPARISIONS OF THE DELAY, POWER,PDP,AREA OF THREE-INPUT XOR/XNOR CIRCUITS. PROPOSED WORKS Cmos Circuit I Cmos Circuit II Cmos Circuit III V.CONCLUSION Power Delay PDP(femito) Area (mw) (ns) µm The use of XOR XNOR circuits has been the topic of numerous reports in the form of full adder circuits, compressors, parity checkers and comparators. The proposed designs have the better performance than the existing three input XOR/XNOR circuits. In this paper, we have used different types of optimization and correction mechanisms which has reduced the PDP, delay, and the number of transistors compared to the previous circuits[17]. ACKNOWLEDGEMENT We are thankful to our guide Mr. D.Lakshmaiah whose personal enrollment in the project has been a major source of inspiration for me to be flexible in my approach and thinking for tackling various issues. We express our sincere thanks to Mr. Rev. Y.PAPI REDDY and J.B.V SUBRAMANYAM, for providing necessary facilities in order to complete our project successfully. REFERENCES: [1] N. Weste, and K. Eshranghian, Principles of CMOS VLSI Design: A System Perspective, Reading MA: Addison-Wesley, 1993 [2] S.M. Kang, and Y. Leblibici, CMOS Digital Integrated Circuits: Analysis and Design, Tata McGraw Hill, [3] J.Rabaey, Digital Integrated Circuits: A Design Prospective, Prentice- Hall, Englewood Cliffs, NJ, [4] Sung-Chuan Fang, Jyh-Ming Wang, and Wu- Shiung Feng, A New Direct design for three input XOR function on the transistor level, IEEE trans. Circuits Syst. I: Fundamental theory and Applications, vol. 43, no. 4, April [5] H. T. Bui, Y. Wang, and Y. Jiang, Design and analysis of low-power 10 transistor full adders using XOR-XNOR gates, IEEE trans. Circuits Syst. II, Analog Digit. Signal Process, vol.49, no. 1, pp , Jan [6] D. Radhakrishanan, Low-voltage low-power CMOS full adder, in Proc. IEE Circuits Devices Syst., vol. 148, Feb [7] C.-K. Tung, S.-H. Shieh, and C.-H. Cheng, Lowpower high-speed full adder for portable electronic applications, Electron. Lett., vol. 49, no. 17, pp , Aug [8] M. Aguirre-Hernandez and M. Linares-Aranda, CMOS full-adders for energy-efficient arithmetic applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp , Apr [9] M. H. Moaiyeri, R. F. Mirzaee, K. Navi, T. Nikoubin, and O. Kavehei, Novel direct designs for 3-input XOR function for low-power and highspeed applications, Int. J. Electron., vol. 97, no. 6, pp , [10] S. Goel, M. A. Elgamel, M. A. Bayoumi, and Y. Hanafy, Design methodologies for highperformance noise-tolerant XOR-XNOR circuits, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp , Apr [11] S. Goel, A. Kumar, and M. Bayoumi, Design of robust, energy-efficient full adders for deepsubmicrometer design using hybrid-cmos logic style, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp , Dec [12] C.-H. Chang, J. Gu, and M. Zhang, A review of 0.18-μm full adder performances for tree structured arithmetic circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp , Jun [13] T. Nikoubin, M. Grailoo, and S. H. Mozafari, Cell design methodology based on transmission gate for low-power high-speed balanced XOR-XNOR circuits in hybrid-cmos logic style, J. Low Power Electron., vol. 6, no. 4, pp , [14] T. Nikoubin, A. Baniasadi, F. Eslami, and K. Navi, A new cell design methodology for balanced XOR-XNOR circuits for hybrid- CMOS logic, J. Low Power Electron., vol. 5, no. 4, pp , [15] T. Nikoubin, M. Grailoo, and C. Li, Cell design methodology (CDM) for balanced Carry

7 InverseCarry circuits in hybrid-cmos logic style, Int. J. Electron., vol. 101, no. 10, pp , [16]Chien-Cheng Yu, Design of High Performance Three-input XOR/XNOR Circuit,HSIUPING JOURNAL. VOL.2.PP.197~208. [17]swati Sharma, Rajesh Mehra Area & Power Efficient Design of XNOR-XOR Logic Using 65 nm Technology. [18] C. Yang and M. Ciesielski, BDS: A BDD-based logic optimization system, IEEE Trans. Comput.- Aided Design Integr. Circuits Syst.,vol. 21, no. 7, pp , Jul B.Sravani,currently she is a final year student in Electronics and communication engineering branch from CJITS,Warangal(Dist.). D.Shashi Kumar,currently he is a final year student in Electronics and communication engineering branch from CJITS,Warangal (Dist.). Dayadi.Lakshmaiah(ph.D) is the Research scholar at JNTUK, Kakinada, Andhra Pradesh, India. He Received B.Tech Degree in ECE from National Institute of Technology, Warangal (RECW) and M.Tech (DSCE) Degree from JNTUA Anantapur. He has published 25 technical papers in International Journals..His area of interest is in Low Power VLSI. India. M.Kalyani,currently she is a final year student in Electronics and communication engineering branch from CJITS,Warangal (Dist). G.Priya Darshini,currently she is a final year student in Electronics and communication engineering branch from CJITS,Warangal (Dist.).