CHAPTER - IV. Design and analysis of hybrid CMOS Full adder and PPM adder

Transcription

1 CHAPTER - IV Design and analysis of hybrid CMOS Full adder and PPM adder

2 Design and analysis of hybrid CMOS Full adder and PPM adder 63 CHAPTER IV DESIGN AND ANALYSIS OF HYBRID CMOS FULL ADDER AND PPM ADDER 4.1 Introduction Full adder is a basic building block for various arithmetic circuits such as multipliers, compressors, comparators and so on. The power requirement and output delay of these circuits greatly depend upon the power requirement and delay of full adder circuits. So by minimizing the power and delay of the full adder circuit we can design high performance arithmetic circuits. Several logic styles for designing the Full adder have been proposed. Each style has some advantages and some disadvantages. In classical design of full adder normally single CMOS structure is used for whole design. Such as the standard static CMOS full adder [4] is based on regular CMOS structure with conventional pull-up and pull-down transistors providing full swing output and good driving capabilities. The main drawback of this circuit is high input capacitance and use of large no. of PMOS, due to which the speed of this structure is degrade. In another conventional design the complementary pass transistor logic (CPL)[4] is used. It provides good driving capability, full swing of operation and high speed. But its main disadvantage is high power dissipation due to large number of internal nodes in the cell. The speed of dynamic CMOS logic style adder is higher. It has several demerits such as charge sharing, high clock load, higher switching activities and lower noise immunity. And it requires high power requirement for driving the clock lines. Another logic styles are transmission-gate full adder (TGA)[5] and transmission-function full adder (TFA)[6] based upon transmission gates and transmission function theory. These full adders are very low power consuming but have very low driving capabilities. Hybrid-CMOS logic design style uses more than one module for designing of full adder. Examples of this style are NEW 14-T adder [7], hybrid pass logic with static CMOS output drive (HPSC) full adder [8], NEW-HPSC [9] full adder and hybrid-cmos full adder[10-12]. In this design style full adder structure is designed by breaking the full adder into three modules. In module I a XOR-XNOR circuit is designed. The outputs of

3 Design and analysis of hybrid CMOS Full adder and PPM adder 64 module I is used as intermediate signals for the other modules. So it is required to get full output swing of XOR and XNOR simultaneously and circuit must have good driving capability. Module II and Module III are the sum and carry circuits which use the intermediate signals and third input signal as input to produce the sum and carry respectively. This logic design style provides the freedom to take the optimum circuits for every module for getting the optimum performance of adder cell. These adders generally lack the driving capabilities. Their performance as a single bit is good but as the size of chain increases, the performance degraded drastically. In the late 1950, Avizienis [16] introduced the redundant number system to solve this problem. The important properties of this number system are to have more than one representation for its value and to represent negative number easily. In the other hand, the disadvantage is space usage for store. The purpose of signed-digit representations is to allow addition and subtraction of two numbers in which no serial signal propagation is required along the adder; that is time duration of the operation is independent of the length of the operands and is equal to the time required for the addition or subtraction of two digits. In such a system, a carry free addition can be performed, where the term carry free in this context means that the carry propagation is limited to a single digit position. In other words, the carry propagation length is fixed irrespective of the word length. The addition consists of two steps. In the first step, an intermediate sum t i and a carry z i are generated, based on the operand digits xi and yi at each digit position i. This is done in parallel for all digit positions. In the second step, the summation u i = z i + t i -1 is carried out to produce the final sum digit u i. The important point is that it is always possible to select Intermediate sum z i and transfer digit t i -1 such that summation in the second step does not generate a transfer digit. Hence the second step can also be executed in parallel for all the digit positions yielding a fixed addition time, independent of the word length. The chapter is organized as follows. Power, evaluation delay, and PDP characteristics of various hybrid adder circuits with the proposed technique are evaluated in Section 4.2. Performance investigation and energy efficiency of several PPM adders is presented in section 4.3

4 Design and analysis of hybrid CMOS Full adder and PPM adder Hybrid-CMOS Logic Design The sum (S) and carry (Cout) expression for a 1-bit full adder with three binary inputs A, B and Cin are given by S = A B Cin Cout = A.B + Cin.(A B) These expressions can be expressed in many ways. Such as in hybrid-cmos architecture we get XOR and XNOR of A and B inputs as the intermediate signal at the output of module I. H = A B H' = A B These input signals and Cin are available for the input of module II and module III. So we get new expression for sum and carry using H and H. S = H Cin = H.Cin' + H'.Cin Cout = A.H + Cin.H Module I circuit is a XOR-XNOR circuit. Many Module I circuits are proposed by many authors. But we required full swing XOR and XNOR outputs simultaneously and good driving capability. Some module I circuits are given in Fig.4.1. We can choose the circuit with minimum power, delay and according to proposed module II and module III circuit to get the best result. i) Module II The expression for the output of module II is given by S = H.Cin' + H'.Cin The expression shows that module II circuit is only a XOR circuit. Many XOR circuits are presented till now. Some Module II circuits are shown in Fig.4.2. The circuits have its own advantages and disadvantages. In the circuit shown in Fig. 4.2(a), output is connected to the input using transmission gates and pass transistors. This circuit has less driving capability. But the power consumption and delay is less in the circuit. The circuit shown in Fig 4.2(b) uses a inverter at its output. So this circuit has good driving capability but due to presence of an inverter the power consumption and delay is more. The truth table for the expression of module II is given by

5 Design and analysis of hybrid CMOS Full adder and PPM adder 66 Fig.4.1 General form of Hybrid-CMOS Logic Design (a) (b) (c) Fig. 4.2 Module I Circuit reported (a) in [7](b) in [8](c) in [9] (a) (b) (c) Fig.4.3 Module II Circuit reported (a) in [7](b)and (c) in [8]

6 Design and analysis of hybrid CMOS Full adder and PPM adder 67 (a) (b) (c) Fig.4.4 Module III Circuit (a) in [7](b) in [8](c) and (d) in [10] (d)

7 Design and analysis of hybrid CMOS Full adder and PPM adder 68 Table I H Cin S The truth table shows that when both inputs are at logic 0 then output is also at logic 0 so we use one NMOS with gate terminal connected with H' and source with Cin and drain at the output. Similarly for H at logic 0 and Cin at logic 1 we use one PMOS for passing the logic1, by connected the source terminal with Cin, gate terminal with H and drain with output. When H will be at logic 0 H' will be at logic 1, both transistors will be on and output will be connected to Cin. So when Cin will be at logic 1 output will be connected to logic 1. And when Cin will be at logic 0 output will be connected to logic 0. The transistors will be in off state for other combinations. When Cin and H are at level 1 than output is low so we connect two NMOS in series with their gates connected with H and Cin and source of one of the NMOS grounded and output at the source of another CMOS. Similarly when H is at logic 1 and Cin is at logic 0, the output is at logic 1 so we use two PMOS in series with source of one of the PMOS at logic high, drain of other PMOS at output and the gates are connected with H and Cin respectively. When both inputs will be at logic 1 then output will be connected to ground and output will be at logic 0, when H will be at logic 1 and Cin will be at logic 0 both inputs H' and Cin will be at logic 0 and both transistor will be on and output will be connected to power supply and we get logic 1 at the output. ` In the designing of circuit we try to avoid the use of inverters to reduce the power consumption and the logic high passes by PMOS while Logic low passes by NMOS to get the minimum delay. ii) Module III The expression for the output of module III is given by

8 Design and analysis of hybrid CMOS Full adder and PPM adder 69 Many module III circuits are presented by many authors. Some circuits are shown in Fig 4.3. The truth table of module III is given by Table III A B C H H' Cout This truth table shows that when H is at logic 1, C passes to Cout. We use transmission gate with H and H' at the gate terminals of NMOS and PMOS respectively Proposed Circuit: We proposed a new full adder circuit design using module II and Module III are discussed in section III. Before module II and module III circuit presented in section III. In the proposed circuit we use three modules. Some circuits of require full XOR and XNOR output swing simultaneously and good driving capability. There are many proposed XOR-XNOR circuits but many of them do not meet our requirements. We are discussing here some XOR-XNOR circuits. Circuit shown in Fig. 4.1(a) use only 6 transistors and provide full output swing. This circuit is widely used in hybrid CMOS logic style. This circuit requires low power and provides low delay and due to the feedback transistors at the output connected with supply voltage and ground provide good driving capability. But some combination of inputs such as 00 and 11 it provides little bit higher delay. The circuit shown in Fig. 4.1(b) is an improved version of this circuit in this circuit pull up and pull down transistors are used to improve the delay performance of the circuit for these combinations. But the drawback of the circuit is that the overall delay of this circuit increased. There is a circuit shown in Fig. 4.1(c), which

9 Design and analysis of hybrid CMOS Full adder and PPM adder 70 provide full output swing for XOR and XNOR simultaneously and provide good driving capability but due to use of inverter circuit at one of the input the power requirement is higher. We use Fig 4.1(a) circuit in our proposed full adder circuit because overall performance of this circuit is best. We use hybrid CMOS logic style to design a new proposed full adder circuit as shown in Fig This circuit has three modules. In module I we use a XOR-XNOR circuit. It produces XOR and XNOR outputs with full swing simultaneously as intermediate signals for other modules. Module II circuit, proposed in section III, produces sum output using intermediate signals produce by module I and third input (C IN ). Module III circuit, proposed in section III, produces carry output using intermediate signals of module I and input signals A, B, and C IN Simulation Results: A. Simulation Setup: The transient analyses of the circuits were performed on HSPICE at a supply voltage ranging 1.2V-2.4V using TSMC 0.186m CMOS process technology. For providing the real environment to the simulation. we use input buffers for all the inputs and a constant output load capacitance of 5.6fF for power and delay measurements. Comparison of the worst case C IN to C OUT delay, C IN to C sum output delay, power consumption, PDP for sum and carry outputs at the supply voltage range of 1.2V-2.4V of reported and proposed circuit is shown in Fig.4.6, 4.7, 4.8 and 4.9. B. Simulation Results and Discussion: The delay comparison of carry in (C IN ) to carry out in the proposed circuit provides the better delay performance than the reported circuits in terms of worst case C IN to C OUT delay. The proposed circuit is 25% to 27% faster than other reported circuits in at 1.8V supply voltage

10 Design and analysis of hybrid CMOS Full adder and PPM adder 71 Fig.4.5 Proposed full adder Fig.4.6 Delay sum comparison for different circuits

11 Design and analysis of hybrid CMOS Full adder and PPM adder 72 Fig.4.7 Delay carry comparison for different circuits Fig.4.8 PDP sum comparison for different circuits

12 Design and analysis of hybrid CMOS Full adder and PPM adder 73 Fig.4.9 PDP carry comparison for different circuits

13 Design and analysis of hybrid CMOS Full adder and PPM adder PPM Adder: Basically PPM adder is a signed digit adder where no need for an explicit mechanism to handle signed digit number. A PPM adder performs the addition of a redundant number x (where x = x + - x - ) to an unsigned binary number y, resulting in another redundant number expressed by an interim sum u - and a transfer digit t +. The input bits are defined as x +, x -, y Є {0, 1} and the output bits are t +, u - Є {0, 1}. The PPM Adder performs the following operation: X + Y = x + - x - + y = 2t + - u - (4.1) There are a variety of PPM adders in the literature, both at the gate level and transistor level [2] [19] [20]. In 1989 A. Guyot [22] has proposed 24-transistors based on a CMOS Structure. Since the performance of an adder would affect the digital system (as in multipliers and dividers). A PPM adder should be designed targeting the maximum reduction of power consumption, time delay and chip area. So a new design of a 14-transistor PPM adder [21] was reported based on sharing and balanced methods which were derived from new algorithms. The reported designs are implemented using pass transistor logic and transmission gates and uses only 14 transistors. They have a full swing output voltages of the output signals u - and t+, thus the noise margins of these new designs are optimum. The sharing method can be Derived as following u - = (x + x - ) y + ( x + x - ) y' (4.2) By denoting z = ( x + x - ) and z' =(x + x - ), we have u - = zy' + z'y Similarly we have, t + = x + ( x + x - ) + u - (x + x - ) (4.3) = x + z + u - z' Three modules are used to implement the two sets of PPM adders shown in fig.4.10

14 Design and analysis of hybrid CMOS Full adder and PPM adder 75 Module-1 consists of six transistors and generates the XOR and XNOR logic signals of z and z [21]. Module-2 consists of the four transistors. It is required to generate the interim sum u - using the signals z, z' and y. This module uses the transmission gate implementation of the XNOR gate with no ground or power supply rails, thus eliminating the short circuit and leakage currents. Module-3 consists of two transmission gates and is required to generate the transfer digit t+, given the control signals z, z', IN and x +. In sharing method of PPM adder (Fig.4.11) uses u- as their IN signal in Module-3.and circuit used to generate u- is also used for t+ (shared method). The balanced method can be derived from the following equations: u - = (x + x - ) y + ( x + x - ) y' (4.4) = u - = zy' + z'y And for transfer digit t + = x + ( x + x - ) + y (x + x - ) (4.5) = x + z + yz' The PPM adder (balanced method) is an improvement relative to sharing method PPM adder, with the feature of a balanced generation of the output signals u - and t+. This leads to the simultaneous generation of the signals u - and t+ and lower time delay (Fig 4.14)

15 Design and analysis of hybrid CMOS Full adder and PPM adder 76 Fig 4.10 Module of PPM adder Fig Transistor PPM adder (Sharing Method) Fig T PPM adder (balanced method)

16 Design and analysis of hybrid CMOS Full adder and PPM adder Proposed configuration: The main aim of the proposed work is to reduce delay, PDP and EDP in long full Adder chain. In this proposed work configuration of various modules are changed with same number of transistor. The PPM design based on the sharing method (Fig-4.11) may suffers from glitches at the output ( t - ) and longer time delay since the generation of t - depends on the signal u + leading to an accumulation of the time delay. The second PPM adder design (Fig-3.4) generates the two output signals (t - and u + ) simultaneously which should results in a better performance. Based on the truth table, the logic functions of u + for the sharing and balanced method of the PPM adder is obtained as: u - = (x+ x - y) (4.6) Thus, the output u - can be generated by using two XNOR gates. The balanced method of PPM adder is an improvement relative to the sharing method of PPM adder, with a balance generation of the output signals u - and t +. The resultant improvement is due to the fact that the generation of signal t - does not depend on the signal u -. Based on the truth table, the logic function of t +, for the balanced method of the PPM adder, is obtained as: t + = x + ( x + x - ) + y (x + x - ) (4.7) One XNOR gate and one multiplexer are used to produce the output digit t +. This design allows a simultaneous generation of both output digits for balanced method PPM Adder in contrast to sharing based adder where the generation of u - is required to generate t +. The proposed XOR-XNOR circuit is basically a PTL (pass transistor logic) based circuit. Two pull-up transistors P1 and P2 and two pull-down transistors N1 and N2 augment the basic skeleton. [Chapter III] output of XOR, XNOR consists of the four transistors. It is required to generate the interim sum (u-) using the signals x+, x - and y. This module uses the transmission gate implementation of the XNOR gate with no ground or power supply rails, thus eliminating the short circuit and leakage currents [21].

17 Design and analysis of hybrid CMOS Full adder and PPM adder 78 Module-3 uses 4 transistors and provides full output voltage swing. This module behaves as a multiplexer passing either x+ or y depending on the control signals (x + x - ) and (x + x - ) (Fig.4.10) The circuit provides good output voltage levels for all combination of input because of the availabilty of feedback PMOS and NMOS transistor loop. The circuit has two cross-coupled PMOS and NMOS transistors connected between XOR and XNOR outputs. This arrangement eliminates the output threshold loss, improve the noise immunity and enhance the driving capability of the circuit. To overcome the problem of skewed outputs the XOR and XNOR functions are combined in one circuit as shown in Fig.4.13.The circuit has a single connection to V DD and single connection to GND. The existence to V DD and GND connections improve the driving capability of the circuit Simulation Setup The transient analysis of the circuits was performed on CADENCE VIRTUOSO at a supply voltage 1.8V using TSMC 0.18µm CMOS process technology. An output load capacitance of 10fF-150fF is used for power and delay measurements. Timing input and output waveforms for redundant binary full adder using XOR-XNOR circuit with feedback transistors are shown in Fig.4.14 and Comparison of the worst case delay, power consumption, PDP, and EDP of all designs at the lowest supply voltage of 1.8V of reported and proposed circuits are shown in Fig.4.16 and Simulation Results The delay is measured between the time when the changing input reaches its 50% voltage level to the time when the resulting output reaches its 50% voltage level for both rise and fall output transitions. The worst case delay is the largest delay among all input signals. The proposed circuits give the better performance than the reported circuits in terms of worst case delay. The simulation results of delay for all circuits are shown in Fig. ( ). The power-delay product (PDP) measured in femto Joule is defined as the product of the worst case delay and the average power consumption. The overall PDP for the proposed circuits have been improved by10 % to15 % at the supply voltage of 1.8V when compared with the reported circuits.

18 Design and analysis of hybrid CMOS Full adder and PPM adder 79 The power consumption is measured with the same input settings as for the propagation delay measurement. The simulation results of the average power consumption shown in Fig.4.17 Energy delay product (EDP) is equal to the product of worst case delay and PDP is reported in Fig 4.18 and Fig Simulation Result of PPM adders TABLE 4.1 PERFORMANCE PARAMETERS OF VARIOUS PPM ADDER Adder Power Delay PDP EDP type (µw) (ns) (µw* ns) (j-s) 24-T PPM SET-1 PPM SET-2 PPM T PPM Proposed PPM * 10-3

19 Design and analysis of hybrid CMOS Full adder and PPM adder 80 Fig 4.13 Proposed 14-T PPM adder Fig.4.14 Timing Input waveforms for proposed PPM Adder based on PTL X-OR, X-NOR circuit

20 Design and analysis of hybrid CMOS Full adder and PPM adder 81 Fig Timing output waveforms for proposed PPM adder based on PTL X-OR, X- NOR circuit Fig.4.16 Comparison of various PPM adders for delay Vs Capacitive Load

21 Design and analysis of hybrid CMOS Full adder and PPM adder 82 Fig.4.17 Comparison of various PPM adders for Power consumption Vs Capacitive Load Fig.4.18 Comparison of various PPM adders for Power Delay Product Vs Capacitive Load

22 Design and analysis of hybrid CMOS Full adder and PPM adder 83 Fig.4.19 Comparison of various PPM adders for delay Vs Capacitive Load

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