A Low-Power 12 Transistor Full Adder Design using 3 Transistor XOR Gates

Transcription

1 A Low-Power 12 Transistor Full Adder Design using 3 Transistor XOR Gates Anil Kumar 1 Kuldeep Singh 2 Student Assistant Professor Department of Electronics and Communication Engineering Guru Jambheshwar University of Science and Technology, Hisar, India Abstract- This paper presents realization of full adder design using 3 transistor XOR gates and transmission gates. The proposed design has been compared with earlier designed adders in terms of power, delay and PDP. The proposed adder shows significant improvement in power and delay. The implementation of circuits is done in Mentor Graphics utilizing standard 180nm CMOS technology. I. INTRODUCTION Demand of low power VLSI systems and compact implementation has increased, due to evolution of portable device and advanced fabrication technologies. Also high computation performance has led to more power consumption which increases the cooling cost. So low power design has become compulsory to reduce cooling cost and increase reliability. Speed is also important for digital systems. But for high speed, power dissipation can be the restrictive factor. So there is a need of finding a circuit technique which can make balance between speed and power. Addition is the most basic arithmetic operation and adder is the most fundamental arithmetic component of the processor. Two important aspects of most applications of digital circuits are maximizing speed and minimizing power consumption. Speed of different modules used in the design will dominate the overall performance of the system. In this paper, we compare the performance of full-adder cells implemented with different CMOS logic styles with the proposed 12 transistor full adder which is more efficient in power consumption. In this paper Section II explains full-adder cell function. In Section III-VI, different designs of Full Adder are implemented and analyzed, Section VII presents the design of Proposed 12T adder. Simulation results of full adder cells are presented in Section VIII. The comparison of the adder cells is based on speed, power consumption, and power delay product. II. FULL ADDER BUILDING BLOCK The full-adder function can be described as follows: For three 1-bit inputs A, B and, the two 1-bit outputs sum and Cout are- (1) (2) From the equations (1) and (2), it is clear that XOR gates form the fundamental building block of full adders. Performance of the adder can be improved by enhancing the performance of the XOR gates. Different types of XOR gates have been proposed over the years. Initially designs were based on either eight transistors [9] or six transistors [9] that are conventionally used in most designs. Design of 4T XOR gate [4, 5, 6, 7, 8, 10, 11] has been emphasized over the last decade. Wang, Fang and Feng in [10] proposed XOR architectures that could operate without complementary inputs which is a drawback of CMOS transmission gate logic based XOR gates shown in [9]. Bui, Wang and Jiang further improved the XOR gate and designed adders with some improvements in the power-delay product and used these XOR gates in their design [5,6]. Shams, Darwish and Bayoumi in [4] further optimized the performance of XOR gates in terms of area and power delay product. III. CMOS BASED FULL ADDER One of the classical design of full adder is standard static CMOS Full Adder [2]. This full adder provides full swing output and good driving capabilities. This conventional adder is made of 28 transistor which causes larger area and high power consumption. 134

2 Figure 1-28T Adder Figure 2-Transient Response of 28T Adder 135

3 IV. TRANSMISSION GATE ADDER Transmission Gate Full Adder design is based on Transmission gate which is a switch comprised of a pmos transistor and a nmos transistor. The control gates are biased in a complementary manner so that one transistors is on or off at a time. This adder is more power consuming than 28T CMOS adder but provide less propagation delay. Figure 3-Transmission Gate Adder Figure 4-Transient Response of TGA 136

4 V. 14T ADDER 14T Adder [11] is based on six transistor XOR/XNOR logic and transmission gates. Sum is generated by input propagation through XOR-XNOR logic, then signal passing through another pass transistor logic as:- Sum = ( Carry is generated by input propagation through XOR- XNOR logic then propagation through any one of the transmission gates as:- Cout = ( It provides lowest propagation delay and consumes power comparable to 28T Adder. Figure 5-14T Adder Figure 6-Transient Response of 14T Adder 137

5 VI. 10T ADDER 10T adder design is based on 4T XNOR gate [6] and pass transistor logic. This XNOR gate has no ground connection. It shows improvement in both power and delay in comparison to the previous adders. The only disadvantage is the threshold loss problem due to Pass transistor logic. International Journal of Electronics, Electrical and Computational System Figure 7-4T XNOR Figure 8-10T Adder 138

6 Figure 9-Transient Response of 10T Adder VII. 3T XOR BASED 12T ADDER The new 12T design proposed here is based 3T XOR gate and transmission gates. Sum output is generated by input propagation through XOR-XOR logic. And the carry is generated by using 3T XOR gate, an inverter, and transmission gates. This adder have improved noise margin and less output signal degradation than 10T Adder. 3T XOR Gate design of XOR logic gate using three transistors is shown in Figure-10. This design is based on a CMOS inverter and PMOS pass transistor logic. When the input B is at logic one, the inverter on the left functions as a normal CMOS inverter. So the output Y is the complement of input A. When the input B is at logic zero, PMOS pass transistor M3 is turned ON and the output Y=A. Thus, the circuit acts as a 2 input XOR gate. For A=0 and B=0, voltage degradation occurs due to threshold drop across the PMOS pass transistor M3 while passing the output logic zero and consequently the output is degraded with respect to the input. This voltage degradation because of threshold drop can be considerably minimized by increasing the W/L ratio of transistor M3 [8]. Figure 10-3T XOR 139

7 Figure 11-12T Adder Figure 12-Transient Response of 12T Adder 140

8 Power Consumption (in pw) PDP(10-20 Ws) Delay for Carry (in ps) Delay for Carry (in ps) International Journal of Electronics, Electrical and Computational System VIII. SIMULATION RESULTS AND COMPARATIVE ANALYSIS Experiments are performed on these full adders at the schematic level. Simulation of the circuits is done using Mentor Graphics. Channel length of the transistors is 180nm and channel width of NMOS and PMOS are 2µm and 4µm respectively. Rise time and fall time of all the input signals is 0.1ns. Various results are shown in Table 1 and graph T TGA Table 1-Comparison for Power Supply 1.8V 0 1.8V 1.6V 1.4V 1.2V 1.0V Power (in pw) Delay for carry (in ps) Delay for Sum (in ps) PDP(10-20 Ws) (in case of carry) Graph 2 28T TGA T T T TGA 14T 10T 12T V 1.6V 1.4V 1.2V 1.0V 700 Graph V 1.6V 1.4V 1.2V 1.0V 28T TGA 14T 10T 12T V 1.6V 1.4V 1.2V 1.0V 28T TGA 14T 10T 12T Graph 1 Graph 4 141

9 IX. CONCLUSION The main aim of this paper is to design a high performance and low power full adder cell. The circuits are designed with a TSMC 0.18µm technology in Mentor Graphics, simulated and compared against other conventional full adder cell. By using 5 steps of power supply from 1 to 1.8 volts, power, delay and PDP of Full Adder cells are compared. Simulation results show that 10T and 12T have less PDP than other conventional adders. But proposed 12T adder has improved noise margin and less output signal degradation than 10T Adder. So due to less power dissipation and less transistor count the 12T full adder cell can be useful in portable and low power devices. X. REFERENCES [1] D. Wang, M. Yang, W. Cheng, Novel low power full adder cells in 180nm CMOS technology, IEEE Conference on Industrial Electronics and Applications, pp , May [2] N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd ed. Delhi, India: Pearson Education, [3] C. H. Chang, J. M. Gu, and M. Zhang, A review of 0.18-μm full adder performances for tree structured arithmetic circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp , Jun [4] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, Performance analysis of low-power 1-bit CMOS full adder cells, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp , Feb [5] H.T. Bui, Y. Wang, Y. Jiang, Design and analysis of 10-transistor full adders using novel XOR XNOR gates, in Proc. 5th Int. Conf. Signal Process., vol. 1, Aug , 2000, pp [6] H. T. Bui, Y. Wang, and Y. Jiang, Design and analysis of low-power 10-transistor full adders using XOR-XNOR gates, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, Jan. 2002, pp [7] A. M. Shams and M. Bayoumi, A novel highperformance CMOS 1-bit full adder cell, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 5, May 2000, pp [8] K.-H. Cheng and C.-S. Huang, The novel efficient design of XOR/XNOR function for adder applications, in Proc. IEEE Int. Conf. Elect., Circuits Syst., vol. 1, Sep. 5 8, 1999, pp [9] Y. Leblebici, S.M. Kang, CMOS Digital Digital Integrated Circuits: Mc Graw Hill, 2nd edition, 1999, Ch. 7 [10] J. Wang, S. Fang, and W. Feng, New efficient designs for XOR and XNOR functions on the transistor level, IEEE J. Solid-State Circuits, vol. 29, no. 7, Jul. 1994, pp [11] D. Radhakrishnan, Low-voltage low-power CMOS full adder, IEEE Proc. Circuits Devices Syst., vol. 148, no. 1, pp , Feb [12] Jin-Fa Lin, Yin-Tsung Hwang, and Ming-Hwa Sheu, Low power 10-transistor full adder design based on degenerate pass transistor logic, IEEE ISCAS, 2012, pp