Design of High speed Low-Power 1-Bit CMOS ALU using threshold voltage Techniques

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1 ISSN: , June, Design of High speed Low-Power 1-Bit CMOS ALU using threshold voltage Techniques Kadari Shivaram yadav 1, M.Praveen kumar 2 Dr. Dayadi Lakshmaiah 3 G.Naveen 4,Ch.Rajendra Prasad 5,Dr. S.pothalaiah 6 IV B tech students 1,4,Professor 3,6, assistant professor 2,5 Vignana Bharathi Institute of Technology, Hyderabad, India. kadarishivaramyadav1056@gmail.com Abstract: - The demand for increasing speed and low power dissipation elicits numerous research efforts with the increasing demand of handy devices driven by batteries. Huge development in VLSI technology has allowed following Moore s law for doubling component density on a silicon chip after every three years. Though MOS transistors have been scaled down, increased interconnections have limited circuit density on a chip. As Microprocessors has been an essential to each and every product that we use in our day to day life such as radio, home appliances and of course, computers. Further, the size of transistor is limited to great extend and increase in power consumption that lead to degradation in the device performance and life time of the device leads to short period of time. Transistors are the main components of microprocessors.. In this paper, we proposed 1- bit CMOS Arithmetic and Logic Unit (ALU) using a 1-bit Full Adders,2x4 Decoder and Logic Unit. Where FA is designed with 10E, transistors. The design is attributed as an efficient area and low power ALU. This design does not compromise for the speed as the delay of the full adder is minimized for large number of computations. We analyzed power consumption of ALU in this paper it is reduced 59.42% and this proposed work is optimized up to 96 MOS transistors. Compared to reference paper 120 MOS transistor.[14] Keywords- ALU, Decoder, Logic unit, Full Adder. I. Introduction Basically an integrated circuit or (also referred to as an IC, a chip, or a microchip) is a set of electronic components designed or embedded on one small flat piece of normal silicon semiconductor material.the integration of huge numbers of very small transistors into an single small semiconductor chip results in construction of electronic components with increased performance and with an less area than those constructed of discrete electronic component. Since the IC's results in increased capability of production, flexibility in designing, reliability and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. Integrated Circuits are now used in every electronic equipment and have a huge growth in the world of electronics. In the past, the major parameters of the VLSI designer were performance area, cost and accuracy. Power consideration was mostly of only secondary importance. An ALU is a circuit that performs operations on the data stored in the registers. The digital function that implements the micro-operations on the information stored in registers is commonly called an Arithmetic Logic Unit (ALU). An arithmetic logic unit is basically a fundamental building block for CPU and a digital electronic circuit that performs arithmetic and logical operations on integer binary numbers. An ALU also a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). Full adder could be defined as a combinational circuit that forms the arithmetic sum of three input bits [4].A digital multiplexer made from MOS device selects one of the 4 operations results and directs it to a single output line. The full adder is an main block in the ALU which performs the all assessing functions of the ALU. A full adder could be defined as a combinational circuit that forms the arithmetic sum of three key in or input bits. A basic full adder block consists the arithmetic sum of three input bits [4].A digital multiplexer made from MOS device selects one of the four operations results and directs it to a single output line. Arithmetic functions like as addition, subtraction, multiplication and division are some examples, which use adder as a main edifice or building block. Design of full adder by using conventional CMOS design style has been presented. Construction of full adder circuit using 14PMOS and 14NMOS transistors with CMOS Inverters of two generates the output transistor, Aspect ratio W/L of entire

2 PMOS &NMOS transistors are similar. To achieve the optimized time domain performance we need the increase the dimensions of indusial transistors [5]-[13] In addition to cost, there is an issue of reliability. Every 10 C increase in operating temperature roughly doubles a components failure rate [13-18]. II. proposed Full Adder Architecture:- A full adder was designed with 10 MOS Transistor for the implementation of logic expression of Eq. (1), Eq. (2). The 1-bit full adder circuit consists of three modules, XNOR-I, XNOR-II and MUX. The XNOR-I and XNOR-II modules are designed using 4 MOS transistors considering two inputs and one output, and MUX module is designed with two MOS transistors for optimum operation. This proposed model there is a possibility to increase the Fig (2) Block diagram of proposed 10T- Full Adder III. Schematic diagram of existing ALU speed of the logic circuits. Fig (1) Full adder implementation with 10 MOS transistors The circuit has the XNOR functionality embedded to reduce the power. The circuit provided ground for XNOR functionality. First XNOR CMOS circuit has no ground connection, second XNOR CMOS circuit has ground connection. SUM = A B C in Eq (1) C out = A B C in + AB Eq (2) Fig (3) existing arithmetic logical unit using 14T full adder The ALU design consisting of two 4 to 1 multiplexers, two 2 to 1 multiplexers and one full adder is s the multiplexers have been used in the ALU design for input and output signal selection. The multiplexer is implemented using pass transistors and full adder. IV. PROPOSED WORK ARITHMETIC AND LOGIC

3 UNIT Fig :4 proposed ALU CMOS circuit The table is given In next page. Above ALU CMOS circuit has been designed using sub circuits like Full Adder, 2x4 Decoder, and Logic Unit. This circuit optimized up to 96 MOS transistors Compared to reference paper [14]. This designed circuit follows the less Delay that is 3.135ns. Logical functions and Arithmetic functions described the implementation of logic expression of Eq. (3) and Table.1 can be performed using ALU CMOS circuit. A, B are inputs S0, S1, S2, S3, S4, S5, are select lines. The circuit designed simulated using Microwind.3.1 Tool.

4 Table 1. Truth table of proposed ALU S0 S1 S2 S3 S4 S5 FUNCTION A A B B B A BAR A BAR B BAR B BAR A OR B A XNOR B A XNOR B A BAR A (B BAR) (A BAR )B (A BAR)+AB (A BAR)+AB (A BAR)+AB B BAR B BAR B BAR B BAR A+B=XOR A+B=XOR A+B A B B-A B-1` AXOR B A AND B A AND B A OR B A OR B Fig: 5 Proposed ALU Circuit using software

5 Fig (6) ALU CMOS circuit using Micro wind Tool Proposed ALUs Reference Paper[14] No. of MOS Transistor Power (µw) Delay (ns) PDP (Femito) Area (µm 2 ) Fig (7) Delay report of proposed full adder model 1 using 1 bit ALU in 90 nm Technology The delay present in the circuit is ns and the power delay product is femito V. SIMULATION RESULTS OF PROPOSED ALU ALU using 10E Table.2 From the results we can analyzed circuit consumption power of µw It is reduced 59.42% compared Reference paper. Occupied area of ALU CMOS circuit 2369 µm 2 this optimized to up to 24.24%.

6 Fig (8) Simulation results of proposed ALU Fig (9) Power delay product of proposed 1-bit Arithmetic and Logic Unit with normal threshold voltage(0.4v) compared to existing work, V DD =1.2V. The comparison of the proposed CMOS full adder using CMOS ALU was reported, the results are embodied in Table 2, Fig 6, Fig 7 and Fig 8. It is observed that for the ALU built using the proposed 10T-Full adder model 1 and the ALU built using the 10T- full adder model 1, the PDP (performance) is reduced up to 31% and 30%. Fig (10) Delay report of proposed full adder model 3 with low threshold voltage using 1bit ALU. The ALU built using the proposed 10T-full adder model 2 saves the area of 14%.Performance analysis of the proposed full adders using 1bit ALU with low threshold voltage = 0.3V in 90nm Technology V DD =1.2V is given in table2 Table3 : Performance of the proposed full adder using 1 bit ALU with low threshold voltage 0.3v

7 Transistor s power(µw) Delay (ns) PDP (Femito) w/s Area(µm 2 ) [93] [92] [47] Full adder model PDP Power Delay Area (Femito) (µw) (ns) (µm 2 ) w/s [93] [92] [47] FAmodel Fig (11) Area report of proposed full adder model 1 with low threshold voltage using 1bit ALU Performance of proposed CMOS full adder with low threshold voltage using CMOS ALU is given in Table 3, Fig 9, Fig 10 and Fig 11. Performance analysis of the proposed full adders using 1bit ALU with high threshold voltage =0.6V, V DD =1.2V is given in table 6.7. Table 4: Performance of the 1 bit ALU with high threshold voltage 0.6v Fig (11) Area report of proposed full adder model 1 with low threshold voltage using 1bit ALU. Fig 12 Area report of proposed full adder model 3 with

8 high threshold voltage using 1bit ALU. analysis of the proposed full adders using 1bit ALU with low (0.3V) and high threshold voltage(0.6v), V DD =1.2V. Fig 15 Area report of 1- bit ALU with full adder model 2 for combined threshold voltages ALU. The CMOS ALU built using CMOS full adder with low and high threshold voltages compared with the existing work and the results embodied in Table 4. VI. CONCLUSION Fig (13) Power delay product of proposed 1-bit Arithmetic and Logic Unit with high threshold voltage (0.6V) compared to existing work V DD =1.2V In this work, a 1-bit ALU is designed at transistor level for low power and minimum area. In this work much effort are spent on the design of full adder circuit. Different typologies of full adders are studied and compared. A 1-bit full adder with 10 transistors is used for lowest power consumption and minimum possible are. The power consumption of 1-bit ALU with full adder transistor is observed to be μw. REFERENCES Fig (14) Area report of proposed full adder model 1 with low threshold voltage using 1bit ALU All proposed CMOS full adder with high threshold voltage using CMOS ALU compared with the existing work, and the results embodied in Table 4, Fig 11, Fig 12 and Fig 13 Performance [1]. Jian-Fei Jiang, Zhi-Gang Mao,Wei-Feng He, Qin Wang, A New Full Adder Design For Tree Structured Arithmetic Circuits, nternational conference on computer engineering and technology, pp , [2]. Manoj Kumar R and Krishna Murthy M, A Low Power Area Efficient Design for 1-bit Full Adder Cell, International Journal of Computer Science and Information Technologies, Vol. 3, no.3, pp.-, , [3]. Subodh Wairya, Garima Singh, Vishant, R. K. Nagaria and S. Tiwari, Design Analysis of XOR (4T)

9 based Low Voltage CMOS Full Adder Cell, In Proceeding of IEEE International Conference on Current Trends In Technology (NUiCONE), pp. 1-7, [4]. FartashVasefi,Z. Abid, Low Power N-Bit Adders And Multiplier Using Lowest-NumberOf-Transistor 1-Bit Adders, IEEE Conference on Electrical and Computer Engineering,,pp , [5]. Jin-Fa Lin Yin-Tsung Hwang, Ming-Hwa Sheu and Cheng- Che Ho, A High Speed and Energy Efficient Full Adder Design Using Complementary & Level Restoring Carry Logic, IEEE International Symposium on Circuits and Systems, pp , [6]. Morgenstern, A.; Fish, A.; Wagner, I.A., Gatediffusion input (GDI): A Power Efficient Method for Digital Combinational circuits, IEEE Transaction on VeryLarge Scale Integration (VLSI) Systems, Vol. 10, No. 5,pp , [7]. Morgenshtein, A.;Fish, A.Wagner, A., Gatediffusion input (GDI)-Anovel power efficient method for digital circuits: A Design Methodology, IEEE International Conference, pp ,2001 [8]. Chip-Hong Chang, Jiangmin Gu, and Mingyan Zhang A Review of 0.18-_m Full Adder Performances for Tree Structured Arithmetic Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 13, no: 6, pp , [9]. [9] Po-Ming Lee; Chia-Hao Hsu; Yun-Hsiun Hung, Novel 10-T full adders realized by GDI structure Components, Circuits, Devices &Systems,Engineered Materials, Dielectrics & Plasmas,pp , [10]. Shahid Jaman, NahianChawdhury, Aasim Ullah, Muhammad FoyazurRaham, A New High Speed-Low Power 12 Transistor Full Adder Design With GDI Technique, international Journal of Science & Engineering Research, Vol.3,No.7,2012. [11]. N. Weste andk.eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Pearson/ Addison - Wesley Publishers, [12]. R.Zimmermannn and W.Fichtner, Lowpower logic styles: CMOS versus pass-transistor logic, IEEE J. Solid-State Circuits, vol. 32, pp , July 1997 [13]. L.Bisdounis, D.Gouvetas and O.Koufopavlou, A comparative study of CMOS circuit design styles for lowpower high-speed VLSI circuits Int. J. of Electronics, Vol.84, No.6, pp ,1998. Anu Gupta, Design Explorations of VLSI Arithmetic Circuits, Ph.D. Thesis, BITS, Pilani, India, [14]. G.V.V.S.R.krishna Behavioral Analysis of Different ALU Architecture Volume1 June 2012 IJECSE [15]. Design and Comparison of low power & high speed 4-bit ALU by Arvin Rajput, Anil Goyal Kadari Shivaram yadav pursuing B.Tech final year in the department of Electronics and Communication Engineering at Vignana Bharathi Institute of Technology(VBIT), Ghatkesar,Hyderabad,India. Gadam Naveen pursuing B.Tech final year in the department of Electronics and Communication Engineering at Vignana Bharathi Institute of Technology(VBIT), Ghatkesar,Hyderabad,India.

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