EFFICIENT DESIGN OF NEW NOVEL FULL ADDER IN GATE DIFFUSION INPUT TECHNIQUES

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1 EFFICIENT DESIGN OF NEW NOVEL FULL ADDER IN GATE DIFFUSION INPUT TECHNIQUES M. Rajarajan 1 Dr. A. Rajaram 2 A.Saravanakumar 3 C. Sathiyam 4 C. Elavarasu 5 PG Scholar Associate Professor PG Scholar PG Scholar PG Scholar Karpagam University, Karpagam University, Karpagam University, Karpagam University, Karpagam University, Coimbatore, India. Coimbatore, India. Coimbatore, India. Coimbatore, India. Coimbatore, India. mmrajan1990@gmail.com. gct143@gmail.com. askrece@gmail.com. csathiyam7@gmail.com. elavarasusme@gmail.com. Abstract- We describe the design and performance of the new adder based on the Gate Diffusion Input (GDI) technique is efficient technique for digital design circuits it consumes less power compare with CMOS technique. GDI has an advantage of minimum area, less complexity and propagation delay for any digital circuit design. We propose a new adder using GDI technique its performance is compared with the ripple carry adder and propagate adder it achieves the best power-delay. The new novel adder is simulated using gate diffusion input technique and their performance is higher than the existing GDI adders, with an area requirement comparable with ripple carry adder and carry look ahead adder. Circuit is designed and simulated using CADENCE tool at 180nm technology. Keywords- analysis, Gate Diffusion Input technique, new adder, low power, VLSI design. I. INTRODUCTION Addition operation is the most important function of digital system. Adder is only not used for the arithmetic operation but also necessary to all modern computers. Adders occupies critical path in key areas of microprocessor, adders are requirement for the design of fast processing system. Many fast adders are available but the design of high speed with low power and less area adders are still challenging. In modern computers, multiple ALU S with wide adders and multiple execution core units on the same chip creates thermal hotspots and large temperature gradients. This affects the circuit and increasing the cooling cost of the system. Adders should have highest performance with least amount of power dissipation and small layout area to minimize the delay. Historically, VLSI designs have used speed as the performance metric. Portable system as well as fast growth of the power in IC s, power dissipation becomes main design of the objectives equal to the high performance of the system. For VLSI designs main goal is to designing the power efficient digital system. Generally Ripple Carry Adders are used for all types of adders because of its compact design but it is the slowest adder. CMOS is the most common digital circuit design style/technique for designing any digital circuit but it is dissipates most of the power during transistor activity. In this brief, an innovative technique is present to implement high proposed a power efficient full adder based on the gate diffusion input circuit design. Using this GDI design style, power dissipation in new full adder also it reduces area and propagation delay. The rest of this brief is organized as follows: a brief background of the GDI technique and existing adder designed in GDI is given Section II, the new full adder design is then introduced in Section III, simulation result and comparison table are presented in Section IV, and finally, in Section V conclusions are drawn. speed low area adders in GDI technique shown in [3]. We RES Publication 2012 Page 6 II. BACKGROUND The GDI technique method is based on the use of simple cell as shown in Fig. 1. In the GDI cell, the inputs are applied at the source/drain of NMOS and PMOS and also gate. There are three inputs (N, P, and G) with one output. The GDI technique is first presented by A. Morgenshtein, A.Fish, and I. A. Wagner in 2002 [3]. The GDI functions is given in below table is simple GDI cell corresponds to different Boolean functions. Single input CMOS inverter structure to a tripleinput GDI cell in order to achieve implementation of complicated logic functions with a number of transistors. Extension of any number of n-input CMOS structure to an (n+2) input GDI cell can be done by

2 time but it is relatively slow, since for each full adder must wait for carry output bit, is to be calculated by previous adder. The maximum delay in RCA is computed from the Cin to Cout of carry, passing through each full adder circuit along the way. III. NOVEL FULL ADDER Figure.1 shows GDI basic cell Table 1: Various logic function of GDI cell A. Development of gates on GDI technique Using GDI function shown in table I, AND, OR and XOR gates are designed using only two transistors are shown in figure 2, 3, 4. N P G OUT FUNCTION 0 B A AB F1 B 1 A A+B F2 1 B A A+B OR B 0 A AB AND C B A AB+AC MUX 0 1 A A NOT Using an input P instead of supply voltage V in the PMOS block of a CMOS structure and an N input instead of Gnd in the NMOS block. This implementation can be represented by the following logic expression [2]: ( ) ( ) where ( ) is a function of an nmos block not the whole original n-input CMOS structure. The above equation function F can be written as follows: ( ) ( ) ( ) ( ) ( ) The function of basic GDI cell output shown in table I are based on Shannon expansion where A, B and C are inputs respectively as, This makes a standard GDI cell suitable for any implementation of logic function that written by Shannon expansion. Shannon expansion is a useful technique for precomputation based on low power design in sequential logic circuits, due to its multiplexing properties [6]. GDI cells can be successfully used for low power design for combinational digital circuit, while combining two approaches, and combinational logic where transitions of logic input values are prevented from propagating through the circuit. Using GDI functions Ripple-carry (RCA) and Carry look ahead adders are presented in [4]. A Ripple Carry Adder (RCA) is an optimized area-efficient adder design [1]. The layout of ripple carry adder is simple, which allows fast design Figure.2 schematic and layout design of AND gate GDI AND and OR gates requires only two transistors but in CMOS AND and OR gate require six transistors. For GDI XOR gate uses only four transistors as compare to 12 transistors in CMOS technique. Since number of transistors required in GDI is less compare with CMOS, then for any operation of digital gate switching activity will be less and so that power dissipation will be less due to charging and discharging of load capacitance. RES Publication 2012 Page 7

3 Figure.3 schematic and layout design of GDI OR gate The figure 3 shows the Gate Diffusion Input technique for OR gate. By using gate diffusion input gates the power and delay consumes less compare with other. In section II discussed about the gate diffusion input technique background. Figure.4 schematic and layout design of GDI XOR gate B. Development of novel full adder on GDI The computation time of carry in ripple carry adder can be reduced at the price of complex design of novel full adder. The novel adder design can be obtained by creating a main signal of carry for each bit position. The novel adder design can be obtained by a transformation of ripple carry design in which the carry logic over fixed group of bits of the adder. Table 2: Comparison table for 4-bit adder design using GDI Figure.5 shows schematic of 4-bit carry chain block The figure 5 shows the 4-bit carry chain block of novel full adder. Even through these addition circuits use different topologies of the full adder, they have carry in and carry out path consisting of two AND gate and one OR gate, and a carry in to sum bit path containing two AND gate, one OR gate, one XOR gate plus one inverter. In ripple carry adder for each full adder must wait for the carry bit to be calculated from the previous full adder. The below figure which shows the 4-bit sum chain block of novel full adder. In this adder the carry is calculated first to reduce the delay of previous carry of full adder. It must be noted that the time critical addition is performed when a carry is generated at the least significant bit position and it is propagated through subsequent bit positions to the most significant one. The proposed novel full adder is the implemented by cascading n/2 modules as shown in fig. 5. Assumed that the carry in of the full adder is cin = 0, the least significant bit position is simplified. Considering that further two AND, one OR, one XOR gates and one inverter are required to compute the sum bits. Adder Design Gate Diffusion Input technique Power (µw) Delay (nsec) Area (µ ) PDP (FJ) New adder RCA CLA Table 3: Comparison analysis of GDI and CMOS based digital gates Gate type Power (µw) Delay (nsec) GDI PDP No. of transistors RES Publication 2012 Page 8 Power (µw) Delay (nsec) CMOS PDP No. of transistors

4 AND OR XOR Figure.8 simulation result obtained for the new novel 4-bit full adder Figure.6 schematic of 4-bit sum chain block IV. SIMULATION RESULT Simulations of novel full adder using Gate Diffusion Input (GDI) are done in CADENCE tool at 180nm technology. All the parameters are set at the time of simulation. Width/ length ratio is shown in the figure 2, 3 and 4, for different gates the width and length value is changed for the better power delay performance. The below figure which shows the layout design of 4-bit novel full adder. The table 2 and table 3 which shows the comparison of the performance of new novel full adder and digital gates. Simulation is done for new novel 4-bit full adder using GDI technique as shown in figure 8. From the table it is observed that GDI based new novel adder reduces power consumption by fifty five percent as compare to CMOS based adders. V. CONCLUSION In this paper we propose new novel full adder based on GDI technique. The new novel adder is simulated using gate diffusion input technique and their performance is higher than the existing GDI adders, with an area requirement comparable with ripple carry adder and carry look ahead adder [4]. The new adder operated in RCA, but it could propagate a carry signal through a number of cascaded gates significantly lower than RCA and CLA. REFERENCE Figure.7 Layout design of 4-bit novel full adder on GDI technique in CADENCE 1. Stefania Perri, Pasquale Corsonello, And Giuseppe Cocorullo, Area-delay Efficient Binary Adders In QCA, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. pp No. 99, April 21, Laxmi Kumre, Ajay Somkuwar and Ganga Agnihotri, Power efficient carry propagate adder, International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June Arkadiy morgenshtein, Alexander fish and Israel a.wagner, Gate Diffusion input (GDI): A power efficient method for RES Publication 2012 Page 9

5 digital combinatorial circuits, IEEE Transaction on very large scale integration (VLSI) systems vol.10, no. 5 October A.Bazzazi and B. Eskafi, Design and Implementation of Full Adder Cell with the GDI Technique Based on 0.18μm CMOS Technology, IMECS vol II, March Radu Zlatanovici, Sean Kao, and Borivoje Nikolic, Energy Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example, IEEE journal of solidstate circuit vol. 44, no. 2, February Po-Ming Lee, Chia-Hao Hsu, and Yun-Hsiun Hung, Novel 10- T full adders realized by GDI structure, ISIC Shahid Jaman, Nahian Chowdhury, Aasim Ullah, Muhammad Foyazur Rahman, A New High Speed - Low Power 12 Transistor Full Adder Design with GDI Technique, IJSER vol. 3, Issue 7, July Balakrishna.Batta, Manohar.Choragudi, Mahesh Varma.D, Energy Efficient Full-adder using GDI Technique, IJRCCT vol. 1, Issue 6, November N.H.E.Weste, David Harris Ayan Banerjee, CMOS VLSI design, Pearson Education Publication,Sixth Impression, A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Lowpower CMOS digital design, IEEE J.Solid-State Circuits, vol. 27, pp , Apr A. P. Chandrakasan and R.W. Brodersen, Minimizing power consumption in digital CMOS circuits, Proc. IEEE, vol. 83, pp , Apr R. J. Baker, CMOS: circuit design, layout, and simulation, IEEE Press Series on Microelectronic Systems. 13. E. Shannon and W. Weaver, The Mathematical Theory of Information. Urbana-Champaign: University of Illinois Press, J. P. Uyemura, Circuit Design for CMOS VLSI. Norwell, MA: Kluwer Academic, 1992, pp M.Morris Mano Digital Logic and Computer Design, Pearson Education Publication, Indian reprint Alireza Saberkari Shahriar Baradaran Shokouhi, A Novel Cmos 1-Bit Full Adder Cell With The Gdi Technique, College of Electrical Engineering, Iran University of Science & Technology, Tehran, Iran. 17. Issam, S., A. Khater, A. Bellaouar and M. I. Elmasry, 1996, Circuit tech-niques for CMOS lowpower high performance multipliers, IEEE Journal of Solid-State Circuits, 31, Zhuang, N. and H. Wu, 1992, A new design of the CMOS full adder, IEEE Journal of Solid-State Circuits, 27, Authors Profile Rajarajan M received the B.Tech. degree in Electronics and communication Engineering in Bharathiyar College of Engineering & Technology Pondicherry University, Karaikal India, in 2012 and, Currently pursuing his M.E. VLSI Design in Karpagam University, Coimbatore, India. Rajaram A received the BE degree in electronics and communication Engineering from the Govt., College of Technology, Coimbatore, Anna University, Chennai, India, in 2006, the ME degree in electronics and communication engineering (Applied Electronics) from the Govt., college of Technology, Anna University, Chennai, India, in 2008 and he received the Ph.D. degree in electronics and communication engineering from the Anna University of Technology, Coimbatore, India in March He is currently working as a Associate Professor, ECE Department in Karpagam University, Coimbatore, India. His research interests include mobile adhoc networks, wireless communication networks (WiFi, WiMaxHighSlot GSM), novel VLSI NOC Design approaches to address issues such as low-power, crosstalk, hardware acceleration, Design issues includes OFDM MIMO and noise Suppression in MAI Systems, ASIC design, Control systems, Fuzzy logic and Networks, AI, Sensor Networks. Saravanakumar A received the B.E. degree in Electronics and communication engineering in maharaja prithvi Engineering College Anna University, Madras India, in 200 and, currently University, Coimbatore, India. Sathiyam C received the B.E. degree in Electronics and communication engineering in maharaja prithvi Engineering College Anna University, Madras India, in 2010 and, currently University, Coimbatore, India. Elavarasu C received the B.E. degree in Electronics and communication engineering in Anna University, Madras India and, currently University, Coimbatore, India. He has over 7 years of experience in Telecommunication field. His areas of interests include Low power VLSI design, Analog circuit design, Wireless communication and computer networks RES Publication 2012 Page 10