AREA OPTIMIZED ARITHMETIC AND LOGIC UNIT USING LOW POWER 1-BIT FULL ADDER

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1 International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN X Vol. 3, Issue 3, Aug 2013, TJPRC Pvt. Ltd. AREA OPTIMIZED ARITHMETIC AND LOGIC UNIT USING LOW POWER 1-BIT FULL ADDER G. KANAKA DURGA 1 & K. SOWJANYA 2 1 Professor & Head, Department of ECE, MVSR Engineering College, Hyderabad, Andhra Pradesh, India 2 Research Scholar, MVSR Engineering College, Hyderabad, Andhra Pradesh, India ABSTRACT In this paper, we proposed a low power 1-bit full adder (FA) with 8-transistors and this is used in the design ALU. By using low power 1-bit full adder in the implementation of ALU, the power and area are greatly reduced to more than 70% compared to conventional design and 30% compared to transmission gates. This design does not compromise for the speed as the delay of the full adder is minimized thus the overall delay. The leakage power of the design is also reduced by designing the full adder with less number of power supply to ground connections. In fact, power considerations have been the ultimate design criteria in special portable applications. For large number of computations, efficient ALU is to be designed for minimum area and speed. KEYWORDS: 8 Transistor Full Adder INTRODUCTION While lowering the no of transistors and decreasing the frequency of switching activities are prevalent techniques of reducing power consumption and area in ALU. First, while supply voltage reduction effectively lowers power consumption, its application is limited to the functional units in the ALU circuits. The project proposes a design for low power area optimized consumption ALU that exploits the benefits of offline software, which can work alone in delivering minimum power consumption or work alongside supply voltage reduction technology to deliver even lower power consumption. Our ALU architecture consists of a set of fast and slow functional units. There are many advantages and plus points to the design of our ALU. Not only does it consume minimal power during runtime, it does not require real time process to monitor performance. Neither is a hardware circuit needed to tune the supply voltage. Compared with other models operating on the supply voltage reduction principle, the ALU we have designed is far simpler. FULL ADDER ARCHITECTURES A basic full adder has three inputs and two outputs which are sum and carry. The logic circuit of this full adder can be implemented with the help of XOR gate, AND gates and OR gates. The logic for sum requires XOR gate while the logic for carry requires requires AND and OR gates. The basic equations for sum and carry of a full adder are Sum = A_B_C (1) Carry = AB + BC + CA (2)

2 116 G. Kanaka Durga & K. Sowjanya below The basic logic diagram for full adder using its boolean equations with basic gates can be represented as shown Figure 1: Logic Circuit for Full Adder Table 1: Truth Table for Full Adder The conventional full adder which consists of 28 transistors is shown in figure2. Another full adder circuit which consists of 14 transistors using transmission gates is also shown in figure 3. Figure 2: Static Complementary CMOS Adders Using 28 Transistors Figure 3: Fourteen Transistor (14T) Full Adder with Transmission Gates 8 transistor full adder area are greatly reduced compared to conventional design and transmission gates. 8 transistor full adder is shown in the figure 4.

3 Area Optimized Arithmetic and Logic Unit Using Low Power 1-Bit Full Adder 117 Figure 4: 8 Transistor Full Adder Figure 5: Simulation Wave Form of 8 Transistor Full Adder ARITHMETIC AND LOGIC UNIT (ALU) The arithmetic logic unit (ALU) is one of the main components inside a microprocessor. It is responsible for performing arithmetic and logic operations such as addition, subtraction, increment, decrement, logical AND, logical OR, logical XOR and logical XNOR. An ALU is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the Central Processing Unit (CPU) of a computer, and even the simplest microprocessors contain one. The processors found inside modern CPUs and Graphics Processing Units (GPUs) have inside them very powerful ALUs. We have designed ALU in three different ways by using multiplexers and full adder circuit. The input and output sections consist of 4x1 and 2x1 multiplexers and logic is implemented by using full adder.in ALU design the multiplexers are designed with pass Transmission gates and full adder is designed with 8TFA both for minimum area and low power. A set of three select signals have been incorporated in the design to determine the operation being performed and the inputs and outputs being selected. Figure 6 shows the block diagram of 4-bit ALU with the CARRY bit cascading all the way from first stage to fourth stage. The ALU consists of eight 4x1 multiplexers, four 2x1 multiplexers and four full adders. The 4-bit ALU is designed in 180nm, n-well CMOS technology. For the INCREMENT and DECREMENT operations logic 1 and logic 0 are applied as inputs respectively. The complement of B is used for SUBTRACTION operation. The full adder performs the SUBTRACT operation by two s complement method The outputs from the full adder are SUM, EXOR, EXNOR, AND & OR. Based on the condition of the select signals, the multiplexer stage selects

4 118 G. Kanaka Durga & K. Sowjanya the appropriate inputs and gives it to the full adder. The full adder computes the results. The multiplexer at the output stage selects the appropriate output and sends it out. Table 2 shows the truth table for the operations performed by the ALU based on the status of the select signals. Table 2: 4-Bit ALU S0 S1 S2 Operation buffer sub add inc Xnor r And xor Simulation Results of 16-Bit ALU Figure 6: Block Diagram of a 4-Bit ALU Figure 7: 1-Bit ALU Figure 8: Output of 1-Bit ALU

5 Area Optimized Arithmetic and Logic Unit Using Low Power 1-Bit Full Adder 119 Figure 9: 2-Bit ALU Using 1Bit ALUs Figure 10: 16-Bit ALU Using 4Bit ALUs CONCLUSIONS In this work, a 16-bit ALU is designed at transistor level for low power and minimum area. In this work much efforts are spent on the design of full adder circuit. A 1-bit full adder with 8 transistors is chosen for its lowest Power Consumption and minimum possible area. With this full adder, the leakage power is also very less as the number of power supply to ground connections are greatly reduced. The power consumption of 16-bit ALU with 8 transistor full adder is observed to be ìw. REFERENCES 1. R. Shalem, E. John, and L.K.John, A novel low-power energy recovery full adder cell, in Proc. Great Lakes Symp. VLSI, Feb. 1999, pp P. Chandrakasan, S.Sheng, and R.W.Broderson, Low-power CMOS digital design, IEEE J. Solid-State Circuits, vol. 27, pp , Apr R. Pedram and M. Pedram, Low Power Design Methodologies. Norwell, MA: Kluwer, H. T. Bui, A. K. Al-Sheraidah, and Y. Wang, Design and analysis of 10-transistor full adders using novel XOR- XNOR gates, in Proc. Int. Conf. Signal Processing 2000 (Wold Computer Congress), Beijing, China, Aug J.Wang, S.Fang, and W.Feng, Newefficient designs for XOR and XNOR functions on the transistor level, IEEE J.Solid-State Circuits, vol.29, pp , July 1994.

6 120 G. Kanaka Durga & K. Sowjanya 6. N. Weste and K.Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Pearson/ Addison -Wesley Publishers, R.Zimmermannn and W.Fichtner, Low-power logic styles: CMOS versus pass-transistor logic, IEEE J. Solid- State Circuits, vol. 32, pp , July Y.Jiang, Y.Wang, and J.Wu, Comprehensive Power Evaluation of Full Adders, Florida Atlantic Univ., Boca Raton, Tech. Rep., 2000.