Power and Area Efficient CMOS Half Adder Using GDI Technique

Transcription

1 Power and Area Efficient CMOS Half Adder Using GDI Technique 1 Ranbirjeet Kaur, 2 Rajesh Mehra 1 M.E.Scholar, 2 Associate Professor 1, 2, Department of Electronics & Communication Engineering NITTTR, Chandigarh, India ABSTRACT In the modern era minimizing power consumption for digital systems involves optimization at all levels of the design and power dissipation has become a major and vital constraint in industries. Different techniques are applied to reduce the power dissipation. A novel Gate-diffusion input (GDI) circuits are applied to different logical circuits.gdi technique reduces the power consumption to greater extent as compared to other techniques. This technique also reduce the number of transistors used, hence reduce the area.gdi cell has same structure as that of CMOS transistor with low complexity and low switching transition.gdi technique also provides enhanced hazard tolerance and are more suitable for low Voltage operations. In this paper half adder with GDI technique is presented and comparison has been done in terms of no. of transistors and power dissipation with other half adders using other techniques. The Main aim of this paper is to de Half adder with GDI technique is 30% faster, and consume 85% less power, Key Words: GDI, Transmission gate, CMOS, Power dissipation 1. INTRODUCTION The adder is a basic building block in the arithmetic unit of digital signal processors and application specific integrated circuits used in various digital electronic devices[1]. The adder is the very important circuit used arithmetic block of the Central Processing Unit (CPU) and Digital Signal Processing (DSP), therefore its performance and power Optimization is of utmost importance. With the technology scaling to deep sub-micron, the speed of the circuit increases rapidly[2]. At the same time, the power consumption per chip also increases significantly due to the increasing density of the chip. Therefore, in realizing Modern Very Large Scale Integration (VLSI) circuits, low-power and high-speed are the two predominant factors which need to be considered[3] There are three major sources of power consumption in digital CMOS circuits, which are summarized in the following equation [1]. Ptotal = Pswitching + Pshort-circuit + Pleakage = (α0 1 x CL x Vdd2 x fclk) + (Isc x Vdd) + (Ileakage x Vdd) (1) The first term represents the switching component of power, where C is the load capacitance, f clk is the clock frequency and α0 1 is the node transition activity factor. The second term is due to the direct path short circuit currents, I sc, which arises when both the NMOS and PMOS transistors are simultaneously active, conducting current directly from supply to ground. Finally, leakage current, I leakage, which can arise from substrate injection and sub threshold effects, is primarily determined by fabrication technology considerations. However, while supply Voltage reduction is the most effective way to reduce the power consumption, such a reduction require new design methods for low- Voltage and low power integrated circuits. Since an average of 15-20% of the total power is dissipated in glitching, low power can also be achieved by reducing the glitches of the circuit [l]. In VLSI implementation, major problems are heat dissipation and power consumption. To solve this problem it is required to reduce power supply Voltage, switching frequency and capacitance of transistors [4]. The strength of a signal is measured by how closely it approximates and ideal Voltage source [5] Today, there are an increasing number of portable applications requiring small-area[6] lowpower high throughput circuitry[7]. Besides addition, adder circuits can be used for a lot of other applications in digital electronics like address decoding, table index calculation etc. For more than four decades, downscaling of CMOS has been the fundamental strategy for improving the performance of VLSI circuits. However, there have been reports suggesting that the MOS transistor cannot shrink beyond certain limits dictated by its operating principle [8]. With the development of the technology towards submicron region leakage power ISSN: Page 401

2 has become significant component of total power dissipation [9]. To overcome the problem of speed and area in adders TG technology can also be used because the main advantage of the TG logic is complex logic functions are implemented by using small number of transistors, thus reduced area. But the problems with transmission gate are it degrades the output as it passes through various stages and no isolation between input and output terminal. The drawback in a transmission gate is that it needs inverted signal values to control gates of PMOS and NMOS, respectively [10]. So new technique i.e GDI Technique is a low power technique that can be used to overcome the drawbacks of CMOS and PTL logic. In this technique, power dissipation and transistor count will be less compared to other logics was introduced. 2. ADDER DESIGN Half adder circuit needs two binary inputs and two binary outputs. The input variables designated the augends and added bits; the output variables produce the sum and carry [11]. The block diagram of half adder is shown in Fig-1 Figure 2. Simple half adder using XOR and AND gate In very Large Scale Integration circuits, a novel adder using XOR gates which are in turn designed with less number of transistors is implemented. Modification of XOR gate portion in an adder using minimum number of transistors is the key idea for the design [12]. XOR gates are the most fundamental blocks for building adder systems [13]. The performance of adder can be improved by designing XOR gate such as using minimum number of transistors but without sacrificing the performance. XOR gates were designed using eight transistors or six transistors in early designs [14] TRANSMISSION GATES Transmission gate logic circuit is a basically passtransistor logic circuit. It is built by connecting a pmos and a nmos transistor in parallel, which are controlled by complementary control signals. The transmission gate consists of two MOSFETs, one n- channel responsible for correct transmission of logic zeros, and one p-channel, responsible for correct transmission of logic ones. Fig-1: Block diagram of half adder The simplified Boolean function according to the truth table is given as S=A B+AB C=AB Table-1 gives the input output relation as Table-1 Truth table of half adder A B SUM CARRY Figure 3: Transmission Gate Circuit When C = 1, X and Y are connected, both logic zero and logic one are passed without degradation ISSN: Page 402

3 2.2 GDI CELL The GDI method is based on the use of a simple cell as shown in Fig. 1[15]. At a first glance the basic cell resembles the standard CMOS inverter, but there are some important differences: GDI cell contains three inputs G (the common gate input of the nmos and pmos transistors), P (input to the outer diffusion node of the pmos transistor) and N (input to the outer diffusion node of the nmos transistor).the Out node (the common diffusion of both transistors) may be used as input or output port, depending on the circuit. Multiple-input gates can be implemented by combining several GDI cells. The buffering constrains, due to possible VT drop are described in detail in, as well as the technological compatibility with CMOS[15]. Now we will make the original CMOS circuit of half adder with the help of transmission gate. Thus Fig-4 shows the half adder implementation using transmission gate Fig-4: schematic Half adder using TG Fig 4: GDI basic cell A salient feature of GDI is that it has improved logic level swing and static power characteristics. It should be noted that the source of the PMOS in a GDI cell is not connected to VDD while the source of the NMOS in a GDI cell is not connected to GND. This feature gives the GDI cell two extra input pins to use which makes the GDI design more flexible than an usual CMOS design. Fig-5: schematic Half adder using GDI TABLE II: Various functions of GDI basic cell. N P G OUT FUNCTION 0 B A A B F1 B 1 A A +B F2 1 B A A+B OR B 0 A AB AND C B A A B+AC MUX 0 1 A A NOT Fig-6: Simulation result of half adder using transmission gate ISSN: Page 403

4 fabrication as now a day s chip area is very important factor. With respect to chip area, power consumption and transistor count, GDI technique is significantly advantageous over conventional as well as transmission gate technology. S R. N O.. Fig-7: Simulation result of half adder using 4. RESULT ANALYSIS Comparative analysis between three types of design method i.e. Conventional half adder, Half adder using transmission gate and half adder using GDI technique e is shown in table-iii. Comparison aspects are based on delay, power consumption, surface area and number of transistors used. Comparison shows that transmission gate based half adder is better than conventional half adder. But half adder using GDI gives best results. Table-III Comparative Analysis PARAM ETER 1. Delay (ns) 2. Power (μw) 3. No. Of Transistor 5. CONCLUSION CONVENTI ONAL ADDER [15] ADDE R USING TG ADDE R USIN G GDI GDI technique is implemented for half adder. Comparisons are made among GDI half adder, conventional CMOS half adder and transmission gate half adder. The analysis shows that the GDI technique is novel and an effective technique for reducing power consumption, delay, area and the Transistor count which will effectively reduce the size of the chip.gdi will allow high density of 6. REFERENCES [1] Anjali Sharma, Rajesh Mehra Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique, International Journal of Computer Applications ( ) Volume 66 No.4, March 2013 [2] A Sharma Singh, R Mehra, Low power TG full adder design using CMOS nano technology, parallel distributed and grid computing (PDGC), 2 nd IEEE, pp ,2012 [3] H. Bui, Y. Wang and Y. Jiang, Design and Analysis of Low- Power 10-T Full Adders Using Novel XOR XNOR Gates, IEEE Transactions on Circuits and Systems Analog and Digital Signal Processing, Volume. 49, pp , [4]. Richa Singh and Rajesh Mehra, Power efficient design of multiplexer using adiabatic logic, International Journal of advances in engineering and technology, pp , March [5]. Neil H.E.Weste, David Harris and Ayan Banaerjee, CMOS VLSI design. Pearson Education,Inc., pp. 11, Third Edition, 2005 [6] Ranjeeta Verma and Rajesh Mehra, CMOS Based Design Simulation Of Adder /Subtractor Using Different Foundriess, International Journal of Science and Engineering, Volume 2, Number , pp [7] M. Shams, and M. A. Bayoumi, A Novel High Performance CMOS 1-Bit Full Adder Cell, IEEE Transactions on Circuit and System, Volume.47, NO. 5, May, 2000 [8] Y.Tau, D.A.Buchanan, W.Chen, D.Frank, K.Ismail, S.Lo, G.Sai-Halasz, R.Viswanathan, H.Wann, S.Wind, and H.Wong, CMOS Scaling into the Nanometer Regime, Proceeding of the IEEE, Volume.85, pp , [9]. Hanchate, N. Ranganathan A new technique for leakage reduction in cmos circuits using self-controlled stacked transistors, 17th International Conference on VLSI Design, pp [10]. W.Jyh-Ming. F.Sung-Chuan, and F.Wu-shiung, New efficient designs for X-OR and XNOR functions on the transistor level, solid-state circuits, IEEE journal, Of. Volume.29,pp ,1994. [11]. M. Morris Mano, Michael D. Cilleti Digital Design, 4th edition, pp.143, [12] V. Elamaran, G. Rajkumar, S. Singh Rajpurohit and R. Anooj Krishnan, Low Power Adder-Subtractor using Efficient XOR Gates. Journal of Applied Sciences, Volume.14, pp [13] Haghparast, M. and K. Navi, 2007, Reversible full adder circuit for nanotechnology based systems J. Applied Sci., Volume.7, pp [14] Leblebici, Y. and S.M. Kang, CMOS Digital Integrated Circuits. 2nd Edition. McGraw Hill, Singapore. [15] Ravi Kumar Anand, Kartar Singh, Pankaj Verma, Ashish Thakur, Design of area and power efficient half adder using transmission gate,international Journal of Research in Engineering and Technology Volume: 04, April-2015 [16] A. Morgenshtein, A. Fish, I. A. Wagner, Gate-Diffusion Input (GDI) A Power Efficient Method for Digital Combinatorial Circuits, to be published, IEEE Trans. On VLSI. ISSN: Page 404

5 Authors: Ms.Ranbirjeet Kaur: Ms.Ranbirjeet Kaur is currently working as Assistant Professor in Ropar IMT group of colleges,shekhupur,punjab.she is pursuing ME from NITTTR Chandigarh Sec,26.She completed her B.tech from Yadawindra College of engg. Under Punjabi University Patiala. She is having five years experience approximately in teaching. Dr. Rajesh Mehra: Dr. Mehra is currently associated with Electronics and Communication Engineering Department of National Institute of Technical Teachers Training & Research, Chandigarh, India since He has received his Doctor of Philosophy in Engineering and Technology from Panjab University, Chandigarh, India in Dr. Mehra received his Master of Engineering from Panjab Univeristy, Chandigarh, India in 2008 and Bachelor of Technology from NIT, Jalandhar, India in Dr. Mehra has 20 years of academic and industry experience. He has more than 325 papers to his credit which are published in refereed International Journals and Conferences. Dr. Mehra has guided 75 ME thesis. He is also guiding 02 independent PhD scholars. He has also authored one book on PLC & SCADA. He has developed 06 video films in the area of VLSI Design. His research areas are Advanced Digital Signal Processing, VLSI Design, FPGA System Design, Embedded System Design, and Wireless & Mobile Communication. Dr. Mehra is member of IEEE and ISTE ISSN: Page 405