INTERNATIONAL JOURNAL OF COMPUTER ENGINEERING & TECHNOLOGY (IJCET)

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1 INTERNATIONAL JOURNAL OF COMPUTER ENGINEERING & TECHNOLOGY (IJCET) International Journal of Computer Engineering and Technology (IJCET), ISSN (Print), ISSN (Print) ISSN (Online) Volume 3, Issue 1, January- June (2012), pp IAEME: Journal Impact Factor (2011): (Calculated by GISI) IJCET I A E M E ABSTRACT NEW DESIGN OF LOW POWER 3T XOR CELL 1 Shiwani Singh, 2 Tripti Sharma *, 2 K. G. Sharma and 1 Prof. B. P. Singh 1 Electronics and Communication Department FET- MITS (Deemed University) Lakshmangarh, Distt.- Sikar, India 2 Electronics and Communication Department Suresh Gyan Vihar University, Jagatpura Jaipur, Rajasthan, India mits.shiwani@gmail.com, tripsha@gmail.com, sharma.kg@gmail.com, bpsinghgkp@gmail.com This paper proposes a 3T XOR gate design implemented using pmos transistors only. The design has been compared with existing design and significant improvement in power consumption has been obtained. All pre layout simulations are performed on 45nm standard model on Tanner EDA tool version Keyword XOR gate, low power and pmos transistor I. INTRODUCTION The XOR gate forms the basic building blocks of various digital VLSI circuits like full adder, multiplier, comparator and parity checker. Enhancing the performance of the XOR gates can significantly improve the performance of the system as whole. The design of this gate has been undergoing a considerable improvement in terms of power consumption. Many design architectures and techniques have been developed to reduce power consumption and has become one of the primary focuses of digital design [1]. This paper proposes a 3T XOR circuit which reduces 76

2 the threshold-loss problem significantly as exists in previous designs and improves the power consumption too. The paper is organized as follows: Section II describes an existing 3T XOR cell as reported in the literature. Section III introduces the proposed 3T XOR cell. Simulation results and their comparisons are included in Section IV and finally Section V concluded the paper. II. Prior Work Figure 1 Existing XOR Gate The design shown in Fig.1 [2]-[6] is based on a modified version of a CMOS inverter and a pmos pass transistor. When the input B is at logic high, the inverter functions like a normal CMOS inverter. When the input B is at logic low, the CMOS inverter output is at high impedance. However, the pass transistor M3 is enabled and the output Y gets the same logic value as input A. However, when A=1 and B=0, voltage degradation due to threshold drop occurs across transistor M3 and consequently the output Y is degraded with respect to the input. The voltage degradation due to threshold drop can be considerably minimized by increasing the W/L ratio of transistor M3 [7]. Table I illustrates the performance in terms of obtained output at various input combinations. 77

3 III. Proposed 3T XOR Gate Figure 2 Proposed XOR Gate The design of proposed XOR gate is shown in Fig. 2. It consists of three pmos transistors and an input voltage of (-440)mV is given to M3. Due to this input voltage, M3 remains ON. The substrate terminals of all the transistors are connected to respective source terminal in order to nullify the substrate bias effect. When AB=00, all transistors are ON and as pmos is weak 0 device, it will pass low logic signal with threshold loss. When AB=01, M1 is ON and pmos being strong 1 device will pass complete logic high at the output but as M3 is always ON, so due to parallel resistance of both the devices the output will be slightly degraded than logic 1 and similar case will happen with AB =10. The W/L ratios of transistors M1and M2 are increased up to 3/1 in order to minimize the threshold loss of M3[7]. For AB=11, only M3 is ON and it will pass incomplete logic 0 signal at the output port. Table I. Performance Table of Existing and Proposed 3T XOR Cell A (Volt) B (Volt) Expected Output Obtained Output (Volt) (Volt) Existing Proposed The performance table shown in Table I illustrates that the small degradation in the output voltage with respect to the full scale input voltage value which can be easily interpreted as logic 1. This proposed design for XOR gate gives better performance than existing one. 78

4 IV. Simulations and Comparison All schematic simulations are performed on Tanner EDA tool version 13.0 using 45nm technology with input voltage ranges from 0.5 to 1.0 V in steps of 0.1 V. Figure 3 Power Consumption with increasing input voltage and temperature In order to prove that proposed design is consuming low power and have better performance, simulations are carried out for power consumption at varying supply voltages and input voltages, temperature and operating frequency respectively. Fig.3 and Fig.4 reveal that the power consumption of the proposed cell is less than that of existing one and thus proposed cell proves its superiority over existing one and hence ensuring the better performance for low power systems. Figure 4 Power Consumption with increasing operating frequency V. Conclusion The pre layout simulations of both the designs have been done and studied using 45nm technology. The proposed design shows improved logic levels at certain input combinations. The proposed XOR gate also has improved power 79

5 consumption with respect to various parameters. Hence, the proposed gate can be used for various applications like adder, multiplier and other complex designs. REFERENCES 1. Y. Leblebici, S.M. Kang (1999), CMOS Digital Integrated Circuits, Singapore: McGraw Hill, 2nd edition, Ch T.Sharma, et. al. (2010), High Speed, Low Power 8T Full Adder Cell with 45% Improvement in Threshold Loss Problem, Proceedings of the 12 th International Conference on Networking, VLSI and Signal Processing, pp , Coimbatore and University of Cambridge, UK. 3. Tripti Sharma, et. al. (2010),, A Novel CMOS 1-bit 8T Full Adder Cell, World Scientific and Engineering Academy and Society (WSEAS) Transactions on Systems, Vol. 9, No.3, pp Tripti Sharma, et. al.(2010), High Performance Full Adder Cell: A Comparative Analysis, Proceedings of the 2010 IEEE Student s Technology Symposium, 3-4 April, IIT Kharagpur. 5. S. R. Chowdhury, et. al.(2008), A high speed 8-transistor full adder design using novel 3 transistor XOR gates, International Journal of Electronics, Circuits and Systems, vol. 2, No. 4, pp J. Wang, et. al.(1994), New efficient designs for XOR and XNOR functions on the transistor level, IEEE J. Solid-State Circuits, vol. 29, no. 7, pp Y.Tsividis, (1996), Mixed Analog-Digital VLSI Devices and Technology, Singapore: McGraw Hill, 1st edition. 80