FULL ADDER USING MULTIPLEXER

Transcription

1 FULL ADDER USING MULTIPLEXER Amit Kumar,Adnan Sherwaniakash Singh Electronics and Communication Engineering. Dronacharya College of Engineering, Gurgaon. Abstract: - Full adder may well be a basic building block of the numerous application specific integrated circuits. The paper evaluates and compares the performance of various full adder circuits that unit designed victimization techniques such as XOR, transmission gates, multiplexers etc. collectively a full adder circuit designed victimization device is planned. The performance of these circuits depends on 180nm technique model at give voltage of 2.5V. The TSPICE simulation results show that the planned circuit s performance is healthier as compare to the circuits that unit found in literature whose performance is evaluated. Index Terms: XOR, Power, Full Adder, Transmission gate, Multiplexer. INTRODUCTION: Most of the VLSI applications, like digital-signal method, process system and microprocessors use arithmetic operations extensively. The arithmetic unit is therefore, heart of all the purpose systems. Addition, subtraction, multiplication, and multiply and accumulate (MAC) unit of mea surement samples of the foremost sometimes used operations of the arithmetic circuit. Binary addition is take into account this perform the foremost crucial 0.5 of the arithmetic unit as a results of all completely different arithmetic operations usually involve addition [1, 2]. It s put together a really vital operation as a results of it involves a carry propagation step. The analysis time of addition depends on the length of the operands. demand high speed method capabilities that in addition consume less power.the1-bit full adder is that the building block of these operation modules. Thus, enhancing its performance is very important for enhancing the general module performance. during this paper, we've an inclination to reviewed entirely totally different 1-bit full adder cells and in addition gift a 1-bit full-adder cell victimization XOR gate with minimum transistor count and multiplex circuit that gives faster operation, and consumes less power than the choice planned full-adder cell found within the literature. The rest of the paper is organized as follows: In section II, some traditional implementations of the entire adder circuits are mentioned. In section III, the projected sort of 1-bit full adder based on the XOR-multiplexer circuit is given. In section IV, simulation results for projected and existing designs full adder circuits are given and comparisons are administrated with graph. Thus, the complete adder that's the essential building block of all digital VLSI circuits got to are undergoes a considerable improvement, being driven by three basic vogue goals, viz. minimizing the junction transistor count, minimizing the flexibility consumption and increasing the speed. the growth of transferrable devices like PDAs, cell phones, etc. IJIRT INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 860

2 The general mathematical equations for the sum and carry are given below in equations (1) and (2). Proposed Full Adder: In the proposed circuit the transistor M1, M2 and M3 formed a XOR gate; M6 & M7 and M8 & M9 forms the multiplexers. The feature size of NMOS and PMOS in the XOR gate is used in such a way that it will give the correct output for all logic combinations. The operation of the circuit for different inputs is shown in the table1. IJIRT INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 861

3 SIMPULATION RESULTS: All the simulations area unit done on TSPICE and every one the schematics unit designed on 180nm technology and simulation is completed exploitation power give of 2.5V. The circuit unit compared in terms of delay, power consumption and power delay product. The below given table 2 and 3 severally offers the simulation results of assorted adder cells given in literature conjointly the projected adder cell. IJIRT INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 862

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5 terms of delay, power consumption and power delay product. REFERENCES: [1] Weste N, Eshragian K; Principles of CMOS VLSI Design-A systems Perspective. [2] [3] CONCLUSION: In this paper, performance of three adder cells is compared by the projected adder cell that's supposed by exploitation XOR and device. The simulation results show that the projected adder is economical in IJIRT INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 864