An Efficient Low Power and High Speed carry select adder using D-Flip Flop

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1 Journal From the SelectedWorks of Journal April, 2016 An Efficient Low Power and High Speed carry select adder using D-Flip Flop Basavva Mailarappa Konnur M. Sharanabasappa This work is licensed under a Creative Commons CC_BY-NC International License. Available at:

2 International Journal of Latest Research in Science and Technology Volume 5, Issue2: Page No , March-April ISSN (Online): AN EFFICIENT LOW POWER AND HIGH SPEED CARRY SELECT ADDER USING D-FLIP FLOP 1 Basavva Mailarappa Konnur, 2 Sharanabasappa 1,2 Dept. Of Electronics & communication Engineering Don Bosco Institute of Technology Bangalore, India 1 basammkonnur@gmail.com, 2 Sharan.k12@gmal.com Abstract Increase in the usage of the portable systems and increase in the packaging density in VLSI design allows designers to design more complex functional units on a chip. Area, power, speeds of the system are the parameters play a major role in the designing and optimizing the IC s. Adder s circuits are the main building block of any data processing systems. In which carry selection is critical path in the data path of the system. For the speed operations, compared to other type of adders speed of the carry select adder is high because separate carry will be used for each block. This proposed paper uses D-flip flop along with TSPC logic in place of BEC or RCA block in the conventional design. So that it significantly reduces the parameters like power delay and decrease in the power delay product with improved performances. The proposed 16-bit carry select adder implemented and simulated in Cadence virtuoso 180-nm Technology and compared with other conventional CSL adders. Keywords CSLA, D-flip flop, TSPC, High speed, low power. I. INTRODUCTION Speed is an important parameter for the DSP applications, in order to increase the speed, the delay of the circuit should be less [1].To get an efficient high performance processors for the applications such as signal processing, an efficient low power and area addition is needed. In processor like Pentium and arm, number of instructions will be executed in a single cycle. Hence high performance adders in the final stage of a multiplier plays key role in the overall performance of the circuits. The speed of the addition is limited by the propagation of carry signal in adders. The sum of each bit is produced sequentially only after the previous bits is summed and carry signal is propagated to next bit in an elementary adder design. Carry select adder is in between delay of ripple carry adder and Area of the carry look ahead adders circuits. CSA reduces the cost and improves the performances. There are two main blocks in carry select adder: for the first block assuming cin=0, for other one cin=1. Hence it avoids propagation of carries over the block by selecting independently generated multiple local carries. This results provides two pre- computed carry and sum output. The final output is selected based on the original carry signal applied to multiplexer. CSA classified as: Square-root CSA which is obtained by equalizing delay via two carry chains and the signal of the previous stage of the multiplexer. This is in binary weighted form also called a non-linear CSA. Linear CSA which is constructed by blocks those are in equal length of each [2]. In proposed design, we introduce low power technique called as true single phase clock with d-flip flop which reduces power drastically and increase the overall speed of the carry select adder. The proposed architecture greatly reduces the delay introduced by Binary to excess-1 converter used in conventional CSA to some extent. The main advantage of the d-flip flop comes from high speed than the n- bit full adder structure used in conventional adder. II 16-bit CSLA Adders A. 16-bit Carry Select Adder using RCA Ripple carry adder is constructed by cascading one bit full adder block and produces the sum and carry signal. The sum of succeeding block is produced sequentially only after the preceding block is summed and carry propagated to the next. This architecture is area efficient and simple but delay in the propagation of the carry signal from preceding block to next hence slower in speed. In CSA, n-bit stages divided into m blocks. Each m blocks composed to a two RCA s with each having cin=0 and cin=1 respectively. Finally, the actual sum is obtained through the multiplexer according to the original cin is given to the MUX [3] [4]. The 16-bit square root RCA is as shown in Fig. 1. CSLA computes very faster because it will not wait for carry from the previous bit instead of that computes sum with independent given carry signal. Hence we can get actual result in MUX output with little amount of delay of each one bit full adder. ISSN:

3 Fig.1 16-bit Square root CSLA using RCA B. 16-bit Carry Select Adder using Binary to Excess-1 Converter To reduce the power and area of regular carry select adder, binary to excess-1 converter is introduced with replacement of cin=1. BEC provides an extraordinary performance over regular CSA. To get high speed, carry select adder uses binary to excess-1, ripple carry adder along with multiplexer for getting fast addition for uneven arrival of the input signal with different time. Input to multiplexer is one from RCA block with cin=0 and another one is from binary to excess-1 converter [4]. The 16-bit Square-Root CSLA with BEC as shown in Fig.2. CSLA with BEC as shown in Fig.2. International Journal of Latest Research in Science and Technology. True single phase clock is one which takes true phase of the clock and it will not take complements of the clock. Flip flops are used to store single bit of data. While considering the regular CSLA and CSLA using binary to excess -one converter the carry select adder using flip flops are more efficient than those [5]. Flip flops becoming more popular in designing an adder circuits. A dual clock pulse generator required to produce pulses in both side of the clock edges i.e. raising edge and falling edge of the clock and also the same pulse can be used to switch the ground. Here, the input D is connected to the both PMOS and NMOS and implemented using transistor switching logic. This design uses less number of transistor i.e. 11 therefore consumes less power compared to other circuits. But only the disadvantages are when there is complexity in cascading units such as multipliers. Here, The 16- bit carry select adder using normal D-flip flop uses the regular RCA block for addition with cin, when clock goes zero the adder circuit performs the addition and stores the result in flip flops. When clock goes high adder performs operation and gives to multiplexer. The stored data in flip flop will be latches until clock goes high. So that actual sum and carry will be produced during one complete clock cycle. The 16- bit CSA using Normal D-flip flop as Shown below Fig. 3. Fig bit Square-Root CSLA using Normal D-flip flop Fig.2 16 Bit Square-Root CSLA using BEC C. 16-bit Carry select adder using normal D-flip flop with normal True single phase clock. III. Modified TSPC True single phase clock having clock and clock given to both PMOS and NMOS devices. Output is constantly affected by changes in the inputs with variation in the clock. True single phase clock which reduces the total power required for operation of the circuit design. It requires less transistor therefore consumes less power. TSPC will acts as master and slave circuits. Below Fig.4. Shows Normal and Modified True single phase clock flip flop. ISSN:

4 International Journal of Latest Research in Science and Technology. in one complete clock cycle. That is if multiplexer control signal is zero, then we will get the output to next succeeding with cin=0. If it is one, we will get the output with cin=1.carry is propagated from previous block multiplexer block multiplexer. Using d-flip flop operation speed will be increased and uses less amount of power. Below Fig. 5. Shows the 16-bit CSLA using Modified D- Flip flop. Fig bit CSLA using Modified D- Flip flop. Fig.4. Normal and Modified True single phase clock flip flop. IV. PROPOSED ARCHITECTURE A. Carry Select Adder using D-Flip Flop with Modified True Single Phase Clock. Here, we are using positive edge D- flip flop with Modified TSPC to produce sum and the carry output. It consumes less power compared to Normal TSPC because usage of the transistor in the Modified TSPC will be less. It consists of regular CSA, D-flip flop which replaces the BEC and RCA blocks in the regular CSLA design, Multiplexer in the final stage to select the actual sum and carry depending upon the actual clock signal. When clock goes low adder circuit performs the operation and holds the result in D-flip flop and when clock goes high it performs the operation and gives to multiplexer. The final result will be obtained by multiplexer V. COMPARISON OF PROPOSED CSLA WITH OTHER ADDERS The 16-bit carry select adder using D-flip flop is implemented and simulated in cadence 180-nm virtuoso editing tool. The proposed design compared with other existing design. The total power consumption is reduced with less delay but as we seen the power delay product it is totally reduced with other regular adders hence proposed design is best suited for arithmetic applications as well as DSP Applications. Below Table 1 Shows the Comparison of 16-bit Proposed CSLA with Regular adders respectively. Here the half of the power will be reduced from the proposed design when e compared with the carry select adder using normal D-flip flop. And also number of transistor count is reduced from the regular CSLA adder circuits. Simulated in 100MHZ activity and the clock pulse and width will be 10ns and 5ns respectively. DSP Applications. Below Table 1 Shows the Comparison of 16- bit Proposed CSLA with Regular adders respectively. Here the half of the power will be reduced from the proposed design when e compared with the carry select adder using normal D-flip flop. And also number of transistor count is reduced from the regular CSLA adder circuits. Simulated in 100MHZ activity and the clock pulse and width will be 10ns and 5ns respectively. Table 1: 16-bit Carry Select Adder Comparison Results. VI. CONCLUSION In VLSI Design Technology, The power consumption, delay and area are the main factors to determine the overall performance of the circuit. The regular adder circuits ISSN:

5 International Journal of Latest Research in Science and Technology. consume more power compared to proposed design. The proposed 8- bit and 16-bit carry select adder using D-flip flop with Modified TSPC is consumes less power with improved performance. Hence suited for the arithmetic and DSP applications compared to other adder topologies. We achieved better power delay product with proposed design REFERANCES 1. O. J. Bedrij, Carry Select Adder, IRE Transactions on Electric Computers, Volume: EC-11, Issue: Parmar, Shivani, and Kirat Pal Singh. "Design of high speed hybrid carry select adder." Advance Computing Conference (IACC), 2013 IEEE 3rd International. IEEE, Anitha Ponnusamy and Ramanathan Palaniappan, Area-Efficient Carry Select Adder Using Negative Edge Triggered D-Flip flop, Applied Mechanics and Materials, Vol. 573(2014) pp , June Laxman Shanigarapu and Bhavana P. Shrivastava, Low-Power and high speed carry select adder, International Journal of Scientific and research Publications, Vol. 3, Issue 8, August D. Prasanna Kumari, R. Surya Prakash Rao, B. VijayaBhaskar A Future Technology For Enhanced Operation In Flip-Flop Oriented Circuits International Journal of Engineering Research and Applications, Vol. 2, Issue 4, July-August 2012, pp ISSN: