An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic PinnikaVenkateswarlu 1, Ragutla Kalpana 2
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1 An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic PinnikaVenkateswarlu 1, Ragutla Kalpana 2 1 M.Tech student, ECE, Sri Indu College of Engineering and Technology, R.R.Dist, Telangana, India 2 Associate Professor, ECE,Sri Indu College of Engineering and Technology, R.R.Dist, Telangana, India ABSTRACT: As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as well as one OR gate. Here also architecures like 8-bit, 16-bit, 32-bit, 64-bit square root carry select adder (SQRT CSLA) is compared with regular one and modified also. The results show there is a great reduction in area and power consumption. Our work shows the better performance in case of minimized delay, less area and low power.the obtained results from the simulation clearly proves our proposed CSLA scheme is dominates the regular SQRT CSLA. Keywords:ASIC, Power, area and delay efficient, BEC, SQRT CSLA. I. INTRODUCTION Addition is one ofthe fundamental arithmetic operations and it has been used extensively in many VLSI systems such as microprocessors, DSP and other specific application architectures. In addition to its main task, which is adding two numbers, it is the nucleus of many other useful operations such as, subtraction, multiplication, address calculation and etc. It is also the speedlimiting and more power consuming element as well. The design of faster, smaller and more efficient adder architecture has been aim and goal for many research efforts and has resulted in a large number of adder architectures. Each architecture provides different insight and thus suggests different implementations.the power consumption and propagation delay are two most important properties of the adder circuit architectures which basically are against each other. That is knowing, lowering the power causes longer propagation delay and vice versa, hence, most architectures referring to one of those important properties. Nevertheless, in some cases they booth may compromised to achieve to low energy consumption. All architectures provide different insight and therefore require different implementation. This chapter provides overall and essential information and abstract of the most adder architectures in system level. In general full Adder function can introduce either using boolean logic function (conventional architecture) or the majority-function. As discussed earlier CSLA can be used to overcome carry propagation delay problem by generating independent carries and later selects carry to get final sum. Due to this fact CSLA is not recommended for area efficient because of having multiple pairs of RCA that generates partial sum and also carry by employing carry input cin = 0 and cin=1, then the multiplexers are used to get final sum and carry are used. The Binary to Excess-1 converter (BEC) is used instead of RCA with Cin = 1 in the regular CSLA to achieve lower area and power consumption. The main advantage of this BEC logic comes from the lesser number of logic gates than Full Adder (FA) structure. Designing for power and energy efficient designs has become a necessity for modern VLSI technologies. Constant electrical field scaling which cause leakage current to increase exponentially along with increasing integration capacity are the main sources of growing static power dissipation. Reviewing power consumption in CMOS circuits shows dynamic power dissipation result of switching still dominates. It was confirmed that supply voltage has major role in both static and dynamic power dissipation and voltage reduction is the most efficient solution for low power circuits. Lowering the voltage causes transistors to operate in sub-threshold region. Increasing propagation delay is one of the main characteristics of transistor ISSN: Page 36
2 in sub-threshold region. This will be source of glitching which not only increases power dissipation but also can generate false signal. Pipelined and self-timed circuits are proposed to improve the resource utilization and efficiency of circuits. Synchronous and asynchronous are two main categories of pipelining architectures. Each one has advantages and disadvantages, however, asynchronous is more attractive for low-power design because it is clock less. Then there is specific circuit implementation that uses reversible logic to save energy. Adiabatic logic is the term given to these circuits. It requires several clock pulses with different phases to transfer energy from one point to the others. II. CALCUATION OF DELAY AND AREA OF THE BASIC ADDER BLOCKS counting the total number of AOI gates required for each logic block. A. RIPPLE CARRY ADDER The simplest addition architecture is based on a linear array of a full adder cell as it is depicted in figure 2. This architecture which also known as RCA has been subjected to be the smallest and the lowest power consuming. However according to the experimental results in this model, they show the average activity overhead (glitch) is about 50%. The worst case delay or the critical delay path in N- Bit RCA is given by: t = (N 1) t.1 Wheret is the carry propagation delay from the input to the output. The AND, OR and INVERTER (AOI) implementation of XOR gate is shown in fig.1. The operations of gates between the dotted lines are performing the operations in parallel and the numeric representation of each gate indicates the delay. Figure 2.A 4-bit Ripple Carry Adder B. CARRY SELECT ADDER Fig1:Delay and area Contributed by that gate. The delay and area evaluation methodology considers all gates to be made up of AND, OR, and INVERTER, each having delay equal to 1 unit and area equal to 1 unit. We then add up the number of gates in the longest path of a logic block that contributes to the maximum delay. The area evaluation is done by The main idea in a carry select adder is to split a sequential adder into two parts and performing the computationof most significant bit (MSB) partwith considering the two possibilities for carry-in bit in parallel. The right generated carry then will be selected using the carry-out bit of the least significant bit (LSB). In thiscase the critical delay path in N-bit full adder when it is divided to M-bit group is given by, t = Mt + + t.2 M =.3 ISSN: Page 37
3 Also conventional structure of the 16-bit regular SQRT CSLA is depicted in fig 4. It has five groups of different size RCA. Figure 3. A 4-bit Carry Select Adder C. MODIFIED SQRT CSLA USING BEC Instead of using a pair of RCA block, SQRT CSLA architecture has developed using a single ripple carry adder with Binary to Excess-1 converter, which replace the RCA block for cin=1, in order to reduce the area and power consumption as compare to the regular CSLA. To replace n- bit RCA block, it requires n+1-bit BEC architecture. 4- bit optimized Boolean logic has been obtained from the functional table of Binary to Excess-1 converter shown in Table1.The Boolean logic for 4-bit BEC has developed using ~NOT, &AND and ^XOR gates. It is very easy to develop higher bit size BEC architecture also because it is following same basic building block of AND and XOR gates for higher bits. Binary[3:0] Excess-1[3:0] Table.1 Functional Table Of The 4-Bit Bec Figure 4 Regular 16 bit SQRT CSLA As shown in fig.5 employs 4-bit BEC termed to be 16-bit SQRT CSLA Fig.5 16-bit SQRT CSLA D. HALF ADDER BASED CSLA USING COMMON BOOLEAN LOGIC: In our proposed wok, an area- efficient and low power half adder based CSLA using common Boolean logic is designed in order to enhance the overall system performance in terms of area and power as compare to other existing architectures. Half adder is used to generate the partial sum for cin=0 and common Boolean logic (CBL) is used for computing partial sum for cin=1.this architecture is used to remove the replicated adder cells in the conventional CSLA, save number of gate counts and achieve a low power. Through analyzing the truth table of a single bit full adder we propose that for ISSN: Page 38
4 generating output summation and carry signal for cin=0, need only one XOR gate and one AND gate respectively, the output summation signal for cin=1 is the inverse of itself as cin=0. III. PROPOSEDCSLA ARCHITECRURE USING HALF ADDER AND CBL method replaces the multiple pair of RCA from regular CSLA, needs only one half adder and Common Boolean Logic (CBL) which optimizing the CSLA in term of area and power. Half adder needs only one XOR and one AND gate to generate the summation and carry signal respectively and Common Boolean Logic requires only one NOT gate and one OR gate to generate the pair of output signal for cin=1. Through the multiplexer, we select the required output result according to the logic state of carry-in-signal. It is shown in Fig 6. Fig.7 Group 3 Of Half Adder Based CSLA Using CBL IV. SIMULATION RESULTS design CSLA along with Regular and CSLA using BEC have been developed for 8-bit, 16-bit, 32-bit, and 64-bit using VerilogHDL. Functional simulation is carried out using modelsim ALTERA edition 6.5b and synthesized in Cadence RTL compiler using GPDK 45nm technology. Word size Adder Area(µm) Power(µW) Delay(ns) 8-bit Fig. 6 The 16-Bit Half Adder Based SQRT CSLA Using CBL Internal structure of proposed CSLA is shown in fig.8. By manually counting the number of gates used for Group 3 is 20 (half adder, multiplexer, not, or gate). One input to the multiplexer comes from the half adder block and other input from the common Boolean logic. Through 2:1 multiplexer the carry signal is propagate to the next adder cell. This architecture has used 4:2 multiplexer to select the correct output is the combination of 2:1 multiplexer. 16-bit 32-bit 64-bit Table 2: Area Power Delay Comparison ISSN: Page 39
5 The 16-bit CSLA is developed by cascading two 8-bit CSLA and in similar manner we have cascaded the 16-bit CSLA and 32-bit CSLA to develop the 32-bit and 64-bit CSLA respectively. The result depicted in Table.2. The proposed design in this paper has been developed using VHDL and simulated using Mentor Graphics tool suite. The architecture is then further evaluated in FPGA using Xilinx 14.1 ISE Design Suite. To optimize the better result in terms of speed we have taken some measures in design suite. In Xilinx the design goal and strategy is kept balanced and the optimization goal is set to speed so that the speed improve. The device utilization summary is given here as the number of slice flipflops used is 96 from the available 1,536, number of input LUT s used are 121 from the available 1,536, the number of occupied slices are 101 while the available is 768 and the number of slices containing only related logic is 100% utilized whereas the number of slices containing unrelated logic is 0%. Thus the program written is very specific which doesn t contain any illogical like thing. The basic layouts, RTL schematic and final output obtain from the design suit are given below: of any digital system but the maindisadvantage is that the delay is high as compare to existing architectures. Fig.9 Comparison of Adders for Area Fig.10 Comparison of Adders for Power Fig.8 Simple layout The synthesized results of adders has been compared for the parameters of area, power and delay and observed from Fig.9, Fig.10and Fig.11 that the proposed architecture has very less area and has very less power consumption and moreover power delay product is very less so we can directly say that it has better result in terms of area, power and power delay-product, these three parameters determine the performance Fig.11 Comparison of Adders for Power-Delay Product ISSN: Page 40
6 V. CONCLUSION This paper presented a simple design is proposed for implementing the CSLA with the help of half adder and common Boolean logic. When the comparison between the SQRT CSLA and modified SQRT CSLA is considered, there is the difference in simple approach is proposed in this paper to reduce the area,delay and power of SQRT CSLA architecture. The reduced number of gates of this work offers the great advantage in the reduction of area, delay and also the total power. The compared results show that the proposed SQRT CSLA has delay, area and power are significantly reduced. REFERENCES [1] B. Ramkumar, H. M. Kittur, and P. M. Khannan, ASIC implantation of modified faster Carry select adder, Eur. J. Sci.Res.,Vol.42,no.1,pp 53-58,2010. BIO DATA Author 1 Pinnika Venkateswarlupursuing M.Tech Branch Digital Systems Computer Electronics in Sri Indu College of Engineering and Technology. His area of interest in Low power VLSI. Author 2 [2] Y.Kim 64-bit carry select adder with reduced area, Electron. Lett. vol.37, no.10, pp may [3] Milos D. Ercegovac and Thomas Lang, Digital arthimetic, Morgan Kaufmann, Elsevier INC, [4] J. O. Bedrij, Carry Select Adder, IRE Trans. Electronic Computers, vol.11, pp , [5] B.Ramkumar, and Harish M Kittur,(2012) Low Power Area Efficient Carry Select Adder,IEEE Transaction on Very Large Scale Integration(VLSI) System, PP.1-5. [6] S.Manju, V.Sornagopal,(2013) An Efficient SQRT Architecture of Carry Select Adder by Common Boolean Logic 2013 IEEE. [7] O. J. Bedrij, Carry-select adder, IRE Trans. Electron. Comput.Pp , Ragutla KalpanaCurrently working as an Associate Professor, Dept. of ECE in Sri Indu College of Engineering and Technology Author 3 [8] B. Ramkumar and Harish M Kittur, Low-Power and Area-Efficient Carry Select Adder, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 20, NO. 2, February [9] Shivani Parmar and Kirat pal Singh, Design of high speed hybrid carry select adder, IEEE, 2012 K. Ashok BabuCurrently working as a Professor & HOD Dept. of ECE in Sri Indu College of Engineering and Technology ISSN: Page 41
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