DESIGN AND ANALYSIS OF ONE BIT HYBRID FULL ADDER USING PASS TRANSISTOR LOGIC. Vaddeswaram, Guntur District, India

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1 Volume 116 No , ISSN: (printed version); ISSN: (on-line version) url: ijpam.eu DESIGN AND ANALYSIS OF ONE BIT HYBRID FULL ADDER USING PASS TRANSISTOR LOGIC Rakesh Chowdary Gutta 1,UhaNikitha Rachapalli 2,Piyusha Remala 3,Phaneendra vale 4,T V Rama Krishna 5 1,2,3,4,5 Department of Electronics and Communication Engineering, K L University, Vaddeswaram, Guntur District, India 1 rakeshchowdaryg@kluniversity.in Abstract: In this work, a hybrid full-adder is designed in CMOS and Pass transistor logic. The circuit is implemented for a 1-bit full-adder focusing on the performance parameters like delay, power and area. The proposed work is compared with the conventional full-adder circuits at different technologies like 50nm, 120nm and 180nm at 1.2V supply for 50nm technology the power is minimum and for the 180nm technology the power is maximum and the delay for 180nm technology is high whereas for 50nm technology is low which is an improved performance when compared with existing full-adder circuits. Keywords: Transmission gate, pass transistors, low power 1. Introduction Development in utilization of the batteryworked convenient gadgets as phones, individual computerized aides (PDAs), and notepads require low power and high speed. Full-adders, being a standout amongst the most central building piece of all the applications remains a concentration in the space of the specialists throughout the years [1],[2]. The upsides of standard (C-M-O-S) style based adders (28T) are against with the measuring in voltage and transistor. Where the power and quality are high [3], [2].Power is one of the requirement, subsequently the architects attempt to diminish the power while defining a framework. Control scattering relies on the exchanging action, hub and control circuit estimate [4]. Adder is one of the most important logic blocks in microprocessors and signal processors. In general, a onebit hybrid full-adder has three inputs and two outputs. The increasing demand for low-power circuits can be applied at different design levels, such as the conventional logic, layout, and the technology level. The circuits used in logic gates like speed, size, power consumption and the optimization of area.[2],[9]. These designs have been broadly divided into two styles, static style and dynamic style. Static full adders are more reliable, simple with the low power requirement but the on chip area requirement is usually larger when compared to dynamic logic full adder [3]. The merits of standard C-M-O-S style adders are strong against with the voltage and the size of the transistor, when the de-merits are high input capacitance and buffers. pass transistor logic is not suitable for low-power applications [9].Different logic styles have been used to design simple and complex ALU circuits as EXOR-EXNOR cells, full-adder cells, multipliers individually [1],[6]. Existing circuits normally use only single logic style for the full circuit design. The dynamic C-M- O-S style gives a operation with high speed because the logic is built with only high charging NMOS transistors.when the PMOS transistors are not present, the input capacitance is very low, and therefore improves the operation speed [1],[5]. However, it is facing with the several problems such as charge sharing and high clock load. The CMOS logic style has high switching-activity and low noise-immunity. Hybrid technology is the combination of two or more different logic styles. One bit hybrid full-adder consists of the CMOS logic design style, transmission gate logic and pass transistor logic [4],[6]. Most of the hybrid adders are lacking with poor driving capability. The aim of this proposed work is to have parameters with a performance of low-power and high speed when compared to existing circuits. The circuit is done in mentor graphics using different technologies. The 169

2 proposed hybrid full-adder consumes less power and high speed in all the technologies like 50nm, 120nm and 180nm than with the conventional fulladder and 16T full-adder. 2. Design_Style Arithmetic operations are used in many devices which plays a vital role. Full-adders are the basic logic blocks used in many applications. There are different logic styles to implement full-adder which having its own merits and de-merits. The design methodology is of two types: 1.Static logic and 2.Dynamic logic. Static logic requires more number of transistors so that it occupies more area on the chip. The advantage of static over dynamic is that it reliable and requires less power. The hybrid full-adder circuit proposed in paper is designed individually. Individual modules are designed in order to analyse the parameters such as power and delay and to see the variation in between the modules. There are three modules present. The MOD1 and MOD3 are the EXNOR modules which implements the output Sum. The MOD2 is the carry generation module which is used to reduce delay and creates short paths. The modules present are Figure. 1. Modules of a full-adder implemented using pass transistors (2T) which helps in reducing the number of transistors and power consumption is less [5],[6]. The output SUM is implemented followed by the second EXNOR module. Second EXNOR module is implemented using transmission gates (4T). The EXNOR related reports are present [5],[7]. The arrangement of transistors than that of normal 6T also leads to power reduction [4],[8]. In this proposed paper the modified EXNOR produces low power and high speed than conventional EXNOR. 2.2 Generation of the Carry_ Module Figure.1 (b) Carry generation module of a full-adder The carry generation module is implemented using four transistors PMOS2, PMOS3, NMOS5, NMOS6 as shown in fig. The input signal(cin) is propagated through a single transmission gate(pmos3, NMOS5). It reduces overall propagation path of a carry signal. The use of strong transmission gates leads to reduction in delay of the carry signal. 3. Operation of the Proposed Full Adder in Mentor Graphics Figure.1 (a). EXNOR module of a full-adder 2.1Exnor_module EXNOR module is the one, where the power consumption is high when compared to other modules. So, the modification should be done highly in EXNOR module for low power analysis. There are two EXNOR modules in the proposed circuit [1]. One of the EXNOR is The cascaded Full-adder is shown in above Figure2. For the efficient performance of the fulladder, we analysed the working operation of a sum and carry out modules. By using two EXNOR modules the output of the SUM is implemented. In the first EXNOR module the transistors NMOS1 NMOS2 are used. The logic behind these NMOS transistors are pass transistor logic, where it is good at logic 0. In pass transistors, based on the selection lines X and X bar, the input lines Y and Y bar leads to output of the EXNOR. The complete SUM 170

3 is implemented by cascading the EXNOR output with the second EXNOR module where it uses the two PMOS and two NMOS transistors. By following the full-adder truth table, carry out is identified as If X = Y, then COUT = Y, else COUT = CIN Here, if X is equal to Y then the output of carry out will be same as the Y, which is implemented by the pass transistors. Otherwise the carry input is taken and reflected as carry out, where it is implemented by the transmission gates PMOS and NMOS. Figure. 2. Proposed full-adder circuit For optimization performance, the tool uses the schematic testing, where we can analyse the full adder in the form of DC and TRANSIENT analysis. The low power and the high speed can be estimated by using the EXNOR and CARRY OUT modules. After the simulation the comparison of average power and delays are noticed between the conventional and proposed full-adder. The performance analysis of a full-adder is taken for different technologies when compared to other logic styles. The Advantages in CMOS design are its robustness against voltage and transistor sizing. The demerits are high input capacitance and it requires more number of buffers. Pass transistor logic design of full-adder requires less number of transistors, faster execution and consumes low power when compared to CMOS logic design. Transmission gate logic consists of both P- transistors and n-transistors connected in parallel. Transmission gate logic requires twenty transistors for implementation of one-bit fulladder. The objective of this paper work is to compare different parameters like power and delay using hybrid logic designs. Hybrid logic design is the combination of two or more logic designs. As per this logic design we had implemented the full adder using two different combination styles 1. The CMOS logic design and transmission gate logic style and 2. Transmission gate logic and pass transistor logic design. 4.1 Consumption of Average_Power The average power for conventional and proposed full-adder is considered. The average power of proposed hybrid full-adder is less when compared to other designs. This is because of the number of the transistors present in the circuit. The less usage of transistors leads to reduction in power. 4. Performance_ Analysis Performance of many logic styles gives parameters like delay, power, power dissipation, area occupied on chip and so on. Here we considered three different logic styles like CMOS, pass transistor logic and transmission gate logic. Conventional full adder generally uses only one logic design style, whereas hybrid fulladder uses more than one logic style. Hybrid logic design improves overall performance of full-adder than conventional logic full adder. CMOS logic design consists of twenty eight transistors due to this more power consumption takes place and chip area increases Figure. 3 Graph of Average power The power consumption is mainly divided in to i) Static power and ii) Dynamic power. Static power is low in CMOS logic when compared to dynamic power. It originates current leakages in the most of the circuits. Dynamic_power is high, due to its charging and discharging of the load capacitance. 171

4 C L = C FIXED + C VARIABLE Where C L is load capacitance, C FIXED is fixed capacitance and C VARIABLE is variable capacitance., C FIXED is inter-connect and technology dependent. It can be reduced by having efficient layout design. C VARIABLE is the part of diffusion capacitance and it is totally composed of input capacitances. Therefore proper sizing of the transistors can be done by variable capacitance. onal r Table 1 Comparison of average power and delay at different technologies Average power 16 T fulladder Delay nm 120nm 180nm Proposed 50nm 120nm nm full-adder Delay_ Propagation As the adder is fundamental block in most of the systems, delay is the one which can analyse the overall performance of a system. The speed response of the system mainly depends on the delay. As the delay is reduced, the speed of the circuit increases. So, the delay can be minimized by reducing the carry signal path. Here, the input signal (X or Y) is given to single transmission gate to generate carry signal. Figure. 5 Layout for a hybrid full-adder The area optimization takes place with the layout by reducing the number of transistors. The transmission gates present between the CIN and COUT will be in ON state. With increase in number of stages, the delay also increases. 5. Conclusion Figure. 4 Bar graph of delay at different technologies As the input is given to a one transmission gate the carry propagation path is reduced. The delay can be reduced further by reducing the transistors. The speed performance of the circuit depends upon the number of adder stages in the circuit. In the cascaded circuit the performance of the speed decreases due to increase in the number of adders. The usage of the weak inverters are independent of the adder stages. In the proposed full-adder, low power hybrid full-adder is designed. The EXNOR consumes more power, so in order to reduce the power, the transistors are reduced. The proposed circuit is implemented in different technologies like 50nm, 120nm, 180nm.at 1.2v and compared with the existing circuits. The proposed full adder consumes low-power and occupies less area. The proposed fulladder in which the EXNOR is designed using pass transistors consumes low power and high speed The layout of the proposed full adder results in area optimization. References 172

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