Contents. Preface. Abstract. 1 Introduction Overview... 1

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1 Abstract Current research efforts have yielded a large number of adder architectures resulting in a wide variety of adders that could be modified to yield optimal, least processing time delay and energy efficiency. There are two alternative circuit designs that one could modify and test for the desired traits, serial and parallel adders and their modifications. My research focus is on designing a 16 and 32-bit Kogge-Stone ( KS ) adder (an example of a parallel adder) which can operate under conditions of low energy input but still yield a desired, output. I introduced a new circuit derived from a real-time reconfigurable perceptron, called Output-Wired Inverter structure ( OWIS ) which operates under low energy conditions into a Kogge-Stone adder in order to characterize the output efficiency in both 16 and 32- bit systems. The results would be compared to the Kogge-Stone adder which is built by mirror structure ( MS ). We confirmed that the Kogge-Stone adder had a smaller delay (due to generated carry bit in parallel) but larger power consumption (due to complicated wiring and a larger number of transistors) than the Ripple Carry adder ( RCA ). The low power consumption made the Ripple Carry adder sometimes give a better performance (it can match the speed of the Kogge-Stone adder, while still requiring less power and energy). For example, comparing two 32-bit adders regarding worst delay and power consumption at 0.7 V voltage supply: TD RCA /TD KS = 5.24 * 10-7 / 1.81 * (1), P KS /P PCA = 7.91 * 10-4 / 1.18 * (2). We also determined that the adder built by mirror structure performed better (it can usually match the speed of an adder built by output-wired inverter structure, while still requiring much less power and energy) than output-wired inverter structure when the circuit is operating at above the threshold region. For example, comparing two 32-bit adders regarding worst delay and a power consumption at 0.5 V voltage supply: TD MS /TD OWIS = 2.21 * 10-5 / 6.35 * (1), P OWIS /P MS = 8.13 * 10-6 / 3.78 * (2). In this point, if someone wants to design a circuit at low power supply, the mirror structure is definitely a good choice. The most interesting thing is that when the power supply became lower, output-wired inverter structure improved performance by sharply reducing power consumption as compared to the mirror structure. Simulations were performed at above threshold using Spectre simulator in Cadence at.35 µm (with V thn is approximately 0.43 V and V thp is approximately V) and HSPICE at 70nm (using BPTM 70 nm with V thn of 0.2V and V thp of -0.22V). I

2 Acknowledgement This work represents the compilation of information that I have obtained in pursuit of the Master s Degree in Microelectronic engineering at the University of Oslo department of Informatics. Work on this project began in January 2004 and was completed in December The project has provided me with the experience of planning and organizing a project which will be useful in my future career endeavors. It has also stimulated my interest in the field of microelectronic engineering as well as in neuroscience which is something that was not anticipated at the onset of this project. I would especially like to take the moment to thank my supervisor Snorre Aunet for his patient guidance and discussions, and Steve Nelson for proofreading this manuscript. I would also like to thank my family for their support and confidence in me while studying toward the Master s Degree. II

3 Contents Preface Abstract i ii 1 Introduction Overview Simple Circuit Analysis Example The EKV model Characteristic of one NMOS transistor Characteristic of one PMOS transistor Characteristic of one inverter Power Consumption Simulations of Output-Wired Inverters Structure at 0.35 µm process One input, two input circuits and their functions Three input circuits and functions Discussion regarding circuit functions implemented by Output-wired inverter structure Simulations of Mirror Structure at 0.35 µm process One input, two input circuits and their functions Three input circuits and functions Discussion regarding circuit functions implemented by Mirror structure Parallel and Serial Adders and Their Building Blocks Full Adder Ripple Carry adder Carry look-ahead adder Prefix-tree adders Simulations of 16 and 32 Bit Kogge-Stone Adder at 0.35 µm process Realize adder function Simulation of the 16 bit Kogge-Stone adders implemented by both output-wired inverter structure and mirror structure at 0.35 µm process (V dd = 0.7V) Simulation results of the 16 and 32 bit kogge-stone adders at 0.35 µm process at different voltage levels Discussion regarding simulation results of the 16 and 32 bit kogge-stone adders at 0.35 µm process at different voltage levels III

4 7 Simulations of 16 and 32 Bit Ripple Carry Adder at 0.35 µm process Simulation results of the 16 and 32 bit Ripple Carry adders at 0.35 µm process at different voltage levels Discussion regarding simulation results of the 16 and 32 bit Ripple Carry adders at 0.35 µm process at different voltage levels HSpice simulation at 70 nm process Finding the suitable transistor s size Simulation of 16 bit Kogge-Stone adders implemented by both output-wired inverter structure and mirror structure at 70 nm process at different voltage levels Simulation results of 16 and 32 bit Kogge-Stone adders at 70 nm process at different voltage levels Discussion regarding simulation results of 16 and 32 bit Kogge-Stone adders at 70 nm process at different voltage levels Discussion and Conclusion Performance of 16 and 32 bit Kogge-Stone adders Performance of 16 and 32 bit Ripple Carry adders Kogge-Stone adders VS Ripple Carry adders µm process in Candence VS 70 nm process in Hspice Output-wired inverter structure VS Mirror structure Low-power supply VS Standard power supply Future work Bibliography 85 Appendix A 87 A.1 Schematics from Cadence A.2 Net list and Code from Hspice simulation List of figures 150 List of tables 154 IV

5 Chapter 1 Introduction The addition of two binary numbers is one of the most common and important arithmetic functions in modern digital VLSI system. Many research efforts have focused on designing faster and more efficient adder architectures and resulted in a larger number of adder architectures. Some examples of architectures are the Ripple carry adder which, generates carries in series, the carry look-ahead adder which attempts to speed-up the carry propagation by using additional logics, group generate and propagate, and the parallel prefix adder which extends from the idea of carry look-ahead computation. The parallel prefix adders are a more general form where a network is used to pre-calculate the carry signals. Some well know parallel prefix adders are the Kogge-Stone adder [4], Brent-Kung adder [8] and Han-Carlson adder [9]. In this paper we aim to build a low-power 16 bit and 32 bit Kogge-Stone adder. Simulation results are achieved by using Spectre simulator in Cadence for a 0.35 µm complementary metal oxide semiconductor (CMOS) implementation and Hspice at 70 nm in all circuits. 1.1 Overview The second chapter presents the basic characteristics of a simple circuit such as N- channel metal oxide semiconductor (NMOS) transistors, P-channel metal oxide semiconductor (PMOS) transistors and INVERTER in a low power supply. In the third chapter we introduce our building block, a new circuit called output-wired inverter structure in our paper. This circuit can be used to realize different Boolean logics by adjusting their substrate potentials. Later we will use this circuit to build a Kogge-Stone adder. The mirror structure will be presented in chapter four for comparison. The fifth and sixth chapters explain the design and assembly of the Kogge-Stone adder and the simulation results. Hspice simulation was introduced in the seventh chapter. My conclusions are presented in the final chapter.. Essential measurements and simulation results are presented in chapters throughout the thesis, while schematics for the circuits are included in Appendix A. 1

6 Chapter 2 Simple Circuit Analysis Example In this chapter we will analyze the simple circuits shown in Fig. 2.1, 2.12, and 2.15 as they apply to N-channel metal oxide semiconductor (NMOS) transistors, P-channel metal oxide semiconductor (PMOS) transistors, and an inverter s characteristics in a low power supply. Simulation results shown below are achieved by using Spectre simulator in Cadence for a 0.35 µm complementary metal oxide semiconductor (CMOS) implementation in all circuits. Schematics can be found in Appendix A (Fig A.1.1 and A.1.2). 2.1 The EKV model The traditional models which are presented in our book usually aimed for strong inversion and are unusable in moderate and weak inversion. Here we introduce a new model, called EKV (Enz-Krummenacher-Vittoz) model [7], which can also handle moderate and weak inversion. In order to maintain the intrinsic symmetry of the device, the source voltage V S, the gate voltage V G and the drain voltage V D are all refer to bulk here. Only three basic parameters are needed for a first order characterization and modeling of the transistor. These are: V T0 : zero biased threshold voltage. n: a slope factor usually smaller than 2 which tends to 1 for very large values of gate voltage V G. W β = μ Cox : the transfer parameter, measured in A/V 2, which can be adapted by the L designer by changing the channel width-to-length ratio W/L. C ox is the gate oxide capacitance per unit area and µ is the carrier mobility in the channel. This last parameter may be conveniently replaced by 2 I s = 2nβU T : Specific current of the transistor (typically 20 to 200nA for W=L), where U kt T = is the thermal voltage (26mV at 300 q K). The drain current I D of the transistor may be expressed as: I D = I F I R (Equation 2-1-1) where I F (V G, V S ) is the for ward component of current, independent of V D and I R (V G, V D ) is the reverse component of current, independent of V S. The forward (reverse) component can be modeled with an acceptable precision in a very wide range of current as 2

7 3 + = T D S T G S R F nu nv V V I I 2 exp 1 ln ) ( 0 2 ) ( (Equation 2-1-2) If (R) << I S (V G < V T0 + nv S (D) ), this component is in weak inversion (also called sub threshold) and equation can be approximated by the exponential expression = T D S T G S R F nu nv V V I I ) ( 0 ) ( exp (Equation 2-1-3) If I F (R) >> I S (V G > V T0 + nv S (D) ), this component is in strong inversion (also called above threshold) and equation can be approximated by the quadratic expression ( ) 2 ) ( 0 2 ) ( 0 ) ( 2 4 D S T G T D S T G S R F nv V V n nu nv V V I I = = β (Equation 2-1-4) If I F (R) is neither much smaller nor much larger than I S ; this component of current is in moderate inversion and must be expressed with full expression of equation The value of the V S (D) for which the argument in equation and becomes zero is called the pinch-off V P, given by n V V V T G P 0 = (Equation 2-1-5) The component I F (R) is in weak inversion for V S (D) >V P and in strong inversion for V S (D) <V P, with some margin needed to be outside the transition range of moderate inversion.

8 2.2 Characteristic of one NMOS transistor Fig 2.1 Circuit of an NMOS transistor, V dd equals 0.7 V Drain Current I dsn versus V ds with V gs as a parameter See figure 2.2: I dsn : Current between drain and source. V ds: The drain-to-source potential. V gs: The gate-to-source potential. Fig 2.2 L n =0.35 um, W n =0.5 um, V gs =0.2 ~0.35 V, I dsn & V ds U=R*I; Rout=1/g ds = U ds / I ds (the output resistances of the device is defined as U ds / I ds which is the inverse of slope of the line.) Comparing three lines, it is evident that when V ds s value changes from 0~0.7 V, L1 current changes most by increasing, L2 in the middle and L3 s current changes least. It is 4

9 clear that resistance of the three lines in this order L3>L2>L1. So, we can make a conclusion that if we apply more gate voltages in NMOS, the smaller the output resistance is Width of NMOS and drain current I dsn That there is another interesting thing we should notice is the current I dsn will not always increase when the width of NMOS increases. Here, we have a series of figures and it shows how V gs affects the relationship between W n and I dsn. W n, W p : width of the NMOS or PMOS. L n, L p : length of the NMOS or PMOS. First, we set L n =0.35 um, and when change W n, we find that: 1. When W n >0.07 um, Idsn rises if W n increases. 2. When um<w n <0.07 um, how current I dsn changes is depended how the V gs changes (I will explain this by showing figures ). 3. When W n < um, the result is an invalid response (the width is too smaller for the simulations). In the figures , I choose four lines which are W n equals um, 0.06 um, um and 0.07 um. See how current I dsn changes with V gs (0~0.7 V). Fig 2.3 L n =0.35 um, W n =0.055 ~ 0.07 um, V gs =0 V, I dsn & V ds 5

10 Fig 2.4 L n =0.35 um, W n =0.055 ~ 0.07 um, V gs =0.1 V, I dsn & V ds Fig 2.5 L n =0.35 um, W n =0.055 ~ 0.07 um, V gs =0.2 V, I dsn & V ds 6

11 Fig 2.6 L n =0.35 um, W n =0.055 ~ 0.07 um, V gs =0.3 V, I dsn & V ds Fig 2.7 L n =0.35 um, W n =0.055 ~ 0.07 um, V gs =0.4 V, I dsn & V ds 7

12 Fig 2.8 L n =0.35 um, W n =0.055 ~ 0.07 um, V gs =0.5 V, I dsn & V ds Fig 2.9 L n =0.35 um, W n =0.055 ~ 0.07 um, V gs =0.6 V, I dsn & V ds 8

13 Fig 2.10 L n =0.35 um, W n =0.055 ~ 0.07 um, V gs =0.7 V, I dsn & V ds Drain Current I dsn versus V gs when V ds equals 0.7 V See figure 2.11: I dsn : Current between drain and source. V ds: The drain-to-source potential. V gs: The gate-to-source potential. Fig 2.11 L n =0.35 um, W n =0.5 um, nwell=0 V, I dsn & V gs 9

14 2.3 Characteristic of one PMOS transistor Fig 2.12 Circuit of a PMOS transistor, V dd equals 0.7V Drain Current I dsp versus V ds with V gs as a parameter See figure2.13: I dsp : Current between drain and source. V ds: The drain-to-source potential. V gs: The gate-to-source potential. Fig 2.13 L p =0.35 um, W p =0.5 um, V gs =-0.35 ~ -0.2 V I dsp & V ds 10

15 U=R*I; Rout=1/g ds = Uds/ Ids (the output resistances of the device is defined as U ds / I ds which is the inverse of slope of the line.) Comparing three lines, it is evident that when V ds s value change from -0.7~ 0 V, L1 current changes most by increasing, L2 in the middle and L3 s current changes least. It is clear that output resistance of the three lines is in this order L3>L2>L1. So, we can make a conclusion that if we apply more gate voltages in PMOS, the bigger the output resistance is Width of PMOS and drain current I dsp I didn t observer anything in PMOS that when width of PMOS increase, the current Idsp will decrease. It seems that when width of PMOS increase, the current Idsp will increase too. When W p <0.077 um, the result is an invalid responses Drain Current I dsp versus V gs when V ds equals -0.7 V See figure 2.14: I dsp : Current between drain and source. V ds: The drain-to-source potential. V gs: The gate-to-source potential. Fig 2.14 L p =0.35 um, W p =0.5 um, nwell=0.7 V, I dsp & V gs 11

16 2.4 Characteristic of one inverter Fig 2.15 Circuit of an inverter, V dd equals 0.7 V First, we can observe the Idsn and Idsp of an inverter when gate voltage change from 0 to 0.7 V: See figure 2.15 and figure 2.16 (for example here I used L p =L n =1.2 um, W n =1.7 um, W p =13.8 um). Fig 2.16 L p = L n =1.2 um, W n =1.7 um, W p =13.8 um, I ds & V g 12

17 We found that when nwell became smaller, both Idsn and Idsp became bigger. When Vg is between 0.3 V and 0.4 V, the current is biggest. 2.5 Power Consumption There are three major components of power dissipation in a CMOS integrated circuit: dynamic power, short-circuit power, and static power [6]. 1) Dynamic power: Dynamic dissipation due to charging and discharging capacitance. Device sizing, combined with supply voltage reduction, is a very effective approach in reducing the energy consumption of a logic network. 2) Short circuit power: Power consumed because of the current flowing from power supply to ground during transistor switching. The short-circuit component has only rarely been considered, and it is quite common to ignore it, or estimate its contribution to about 10% of the dynamic power. 3) Static power: Due to leakage (which translates into stand-by power) and static current. For the future technology nodes, it becomes more and more important. 13

18 Chapter 3 Simulations of Output Wired Inverters Structure at 0.35 μm process In this chapter we present an idea for new real-time reconfigurable perceptron, also called threshold element. The circuit example contains three inverters with shorted outputs [1] (see Fig 3.1). I called it output-wired inverter structures ( owis for convience) in my thesis. Spectre simulation results for a 0.35 µm CMOS implementation are shown. We are able to use owis to realize different logic functions for example inverter, nand2, nor2 and carry and so on. The purpose of this chapter is to design an optimally functional output-wired inverter structures based on their sizes. Schematics can be found in Appendix A (Fig A.1.3, A.1.5 and A.1.7). For our simulation, V dd equals 0.7 V. The low is defined as any output lower than V dd /2, and high as any output larger than V dd /2. Fig 3.1 The perceptron presented in this paper (In this case the schematic is made for the purpose of an nwell process and the substrate and gate of the NMOS shorted) 14

19 3.1 One input, two input circuits and their functions Table 3.1 Truth table for NOR2: Y X F Table 3.2 Truth table for NAND2: Y X F Table 3.3 Truth table for INVERTER: Input Output Fig 3.2 X and Y pulses The truth tables for NOR2, NAND2 and INVERTER are shown above (Table ). We performed simulations with our circuit example shown in fig 3.7. First, for our nwell process, we used V b1 =V b2 =V b3 =0 V in NMOS and V b1 =V b2 = V b3 =V dd /2 =0.35 V in PMOS. When we set one of the inverter s input voltages to V dd ; and at the same time set the X input signal pulse which has a width of 20 us and period of 40 us; set the Y input signal pulse which has a width of 40 us and period of 80 us (see Figure3.2), the circuit 15

20 (see Figure 3.3) performs the NOR2 function (see Figure 3.4). When we set one of the inverter s input voltages to ground instead of V dd, while keeping the X and Y input signal pulses the same, the circuit (see Figure 3.5) performs the NAND2 function (see Figure 3.6). If all three inputs have a common origin, the circuit (see Figure 3.7) behaves like an inverter (see Figure 3.8) Circuit and function of NOR2 at 0.35 μm process Fig 3.3 Circuit of NOR2 built by owis Fig 3.4 L n =L p = 0.5 um, W n =0.7 um, W p =3.25 um, nwell=0.35 V, NOR2 function We start with L n =L p =0.3 µm, W n =0.45 µm, W p =1.95 µm and try to observe how the NOR2 circuit behaves when we change the transistor s value of L, W n and W p. Ideally 16

21 the High output should be 0.7 V and the Low output should be 0 V, in this system, a worst high refers to the lowest output which can be considered as a High output, that is, above 0.35 V. A worst low refers to the highest output which can be considered as a Low output, that is, under 0.35 V. See table3.4: Table 3.4 Find suitable size for NOR2 function, V dd =0.7 V L=Ln=Lp (µm) Wn (µm) Wp (µm) worst High (mv) worst Low (mv) Analysis: from the table 3.4, we find that it is better to hold L bigger than 0.3 µm; otherwise NOR2 s function output is not close to the ideal output (Recall that 0.7 V is an ideal high output and 0 V is an ideal low output). At the same time, we also find that increasing W n causes the low output L to be come close to the ideal of 0 V while the high output H is compromised and deviates further from the ideal value of 0.7 V, and increasing W p causes the high output H to be come close to the ideal of 0.7 V while the low output L is compromised and deviated further from the ideal value of 0 V. If make all values bigger, the power consumption will be sacrificed. That s why we can t get the perfect answer, but choose the proper one, the one yielding the high and low output that are close to the ideal outputs and utilizing the least amount of power. In our simulation, we use L n =L p =0.5 um, W n =0.7 um, W p =3.25 um. 17

22 3.1.2 Circuit and function of NAND2 at 0.35 μm process Fig 3.5 Circuit of NAND2 built by owis Fig 3.6 L n =L p = 0.5 um, W n =0.7 um, W p =3.25 um, nwell=0.35 V, NAND2 function We start with L n =L p =0.3 µm, W n =0.45 µm, W p =1.95 µm and try to observe how the NAND2 circuit behaves when we change transistor s value of L, W n and W p. See table 3.5: 18

23 Table 3.5 Find suitable size for NAND2 function, V dd =0.7 V L=L n =L p (µm) W n (µm) W p (µm) worst High (mv) worst Low (mv) Analysis: From table3.5 we find identical rules as in table 3.4 which is better to hold L bigger than 0.3 µm, otherwise NAND2 s output function is not good. At the same time, we also find that increasing W n causes the low output L to be come close to the ideal value of 0 V while the high output H is compromised and deviates further from the ideal value of 0.7 V, and increasing W p causes the high output H to come close to the ideal value of 0.7 V while the low output L is compromised and deviates further from the ideal value of 0 V. If make all values bigger, the power consumption will be sacrificed. That s why we can t get the perfect answer, but choose the proper one, the one yielding the high and low output that are close to the ideal outputs and utilizing the least amount of power. In our simulation, we use L n =L p =0.5 um, W n =0.7 um, W p =3.25 um Circuit and function of INVERTER at 0.35 μm process Fig 3.7 Circuit of Inverter built by owis 19

24 Fig 3.8 L n =L p = 0.5 um, W n =0.7 um, W p =3.25 um, nwell=0.35 V, INVERTER function 3.2 Three input circuits and functions Table 3.6 Truth table for NOR3: X Y Z F Table 3.7 Truth table for NAND3: X Y Z F

25 Table 3.8 Truth table for Carry : X Y Z F Fig 3.9 X, Y and Z pulses The truth tables for NOR3, NAND3 and Carry are shown above (Table ). Then, we use the circuit example which contains three identical inverters shorted together again, See figure 3.1. This time for our nwell process we will use Vb1=Vb2=Vb3=0 V in NMOS and make Vb1=Vb2=Vb3 change from 0 to V dd (0.7 V in my circuit) in PMOS. The basic idea is that the threshold voltages of the active devices may be dynamically changed by adjusting their substrate potential, so we are be able to realize different logic functions like NOR3, Carry and NAND3. Usually, Carry function is easiest to get but NOR3 and NAND3 is difficult to get simultaneously due to nwell change. NOR3 function often appears around nwell=0 V (at least appears 0 V, so it has three functions); and NAND3 often appears around nwell=0.7 V (at least appears 0.7 V, so it has three functions); Carry often appears in between. The definition of the NOR3: the output undergoes the transition from high to low if, and only if, the number of high inputs increases from 0 to 1 or more [1]. 21

26 The definition of the Carry : the output undergoes the transition from high to low if, and only if, the number of the high inputs from 1 to 2 or 3, or Carry =x y +x z +y z [1]. The definition of the NAND3: the output undergoes the transition from high to low if, and only if, the number of the high inputs from 2 to 3 [1]. I started with L p =L n =0.35 µm, W n =0.5 µm and W p =2.5 µm which is balanced by only one inverter (V dd /2 in and V dd /2 out, nwell set 0.35 V). We used an x-pulse with a width of 10 us and a period of 20 us. The y-pulse had a width of 20 us and a period of 40 us while the z-pulse had a width of 40 us and a period of 80 us. These were the three inputs (see Fig. 3.9). When we change the nwell in PMOS from 0 to V dd, will find that it only have two functions which are NOR3 and Carry. If we want to get NAND3 function, we should make the PMOS strong enough (As you know, the PMOS is good at pulling up to 0.7 V and NMOS is good at pulling down to 0 V) to get the output higher which corresponded to input (011,101,110). We increased the W p until output of the (011,101,110) became high when nwell=0.7 V. Unfortunately, if we keep this W p we found that the output also became high which corresponded to the input (001,010,100) when nwell=0 V. This is what we don t want because we want to maintain in a low output to get the NOR3 function. It s clear that this kind of width and lengthen couldn t realize three functions when we change the nwell on PMOS. See figure 3.10 fig 3.11 and fig 3.12 Fig 3.10 L n =L p = 0.35 um, W n =0.5 um, W p =2.5 um, nwell=0.7 V, NOR3 function 22

27 Fig 3.11 L n =L p = 0.35 um, W n =0.5 um, W p =2.5 um, nwell=0.35 V, Carry function Fig 3.12 L n =L p = 0.35 um, W n =0.5 um, W p =2.5 um, nwell=0 V, Which is still Carry function Then I increased the length slightly. Set L n = L p = 0.5 um, W n =0.7 um and W p =3.275 um which is balanced. We will find that it only realizes two functions, as before, the Carry and NOR3 functions. Again, we try to increase W p (for example W p =5um). Finally, when nwell is 700 mv, we have NOR3 and when nwell is 0 V, we have the NAND3 function. But, we noticed that both the NOR3 function in nwell=0 V and the NAND3 function in nwell=700 mv is not close to ideal (high is not exactly V dd and low is not exactly 0). The output which corresponded to input (001,010,100) is just a little bit lower than V dd /2 and the output which corresponded to input (011,101,110) is just a little bit higher than 23

28 V dd /2.see figure. I still want try to make a better one, so I decided to increase the length more. See figure 3.13 fig 3.14 and fig Fig 3.13 L n =L p = 0.5 um, W n =0.7 um, W p =3,275 um, nwell=0.7 V, NOR3 function Fig 3.14 L n =L p = 0.5 um, W n =0.7 um, W p =3,275 um, nwell=0.35 V, Carry function 24

29 Fig 3.15 L n =L p = 0.5 um, W n =0.7 um, W p =3,275 um, nwell=0 V, NAND3 function This time, I set L n = L p =1.2 um, W n =1.7 um and W p =13.8 um which is almost balanced, and I got the three functions very quick. When nwell=0.7 V, it has the NOR3 function and a worst low of about mv; when nwell =0 V, it has the NAND3 function and a worst high of about mv. See figure 3.16, fig 3.17 and fig Fig 3.16 L n =L p = 1.2 um, W n =1.7 um, W p =13.8 um, nwell=0.7 V, NOR3 function 25

30 Fig 3.17 L n =L p = 1.2 um, W n =1.7 um, W p =13.8 um, nwell=0.35 V, Carry function Fig 3.18 L n =L p = 1.2 um, Wn=1.7 um, W p =13.8 um, nwell=0 V, NAND3 function 26

31 3.3 Discussion regarding circuit functions implemented by output-wired inverter structure Comparing to carry function, we notice that nand3 or nor3 function is difficult to get for three input functions and they are very sensitive to the transistor size. In next chapter, we will discuss how to use mirror structure to realize inverter, nand2, nor2 as well as Carry functions. 27

32 Chapter 4 Simulations of Mirror Structure at 0.35 μm process In this chapter, we introduce a circuit called mirror structure [10]. We called it ms later for convience. When we give different signals to the input, it will realize different logic functions, for example nand2, nor2 and inverter just like output-wired inverter structure which we mentioned in the previous chapter, but the mirror structure is not able to realize nand3, nor3 functions. Spectre simulation results for a 0.35 µm CMOS implementation are shown. Schematics can be found in Appendix A (Fig A.1.4, A.1.6 and A.1.8). Purpose: To characterize the mirror structure used for building the Kogge-Stone adder. This will be compared to the wired-output inverter structure as regards output, power consumptions, worst delay and power delay. For our simulation, V dd here equals 0.7 V. the low is defined as any output lower than V dd /2, and high is defined as any output larger than V dd /2. 28

33 4.1 One input, two input circuits and their functions Figure 4.1 Mirror structure circuit Figure 4.2 A and B pulses We start simulations with our circuit example (see Figure 4.1). First, for our nwell process, we used Vb1=Vb2=Vb3=0 V in NMOS and Vb1=Vb2 = Vb3 =Vdd/2 =0.35 V in PMOS. When we set one of the inputs(here for example input C) voltages V dd, at same time, we set the input A signal pulse which has a width of 20 us and period of 40 us; set input B signal pulse which has a width of 40 us and period of 80 us(see Figure4.2), the circuits (see Figure 4.3) perform the NOR2 function (see Figure 4.4); When we set one of the input(here input C) voltages to ground instead of V dd, and set the input A signal pulse which has a width of 20 us and period of 40 us; set the input B signal pulse which has a width of 40 us and period of 80 us, the circuit (see Figure 4.5) does the NAND2 function (see Figure 4.6); If we don t set any input to fast voltages, the circuit (see Figure 4.7) behaves like a inverter (see Figure 4.8). 29

34 4.1.1 Circuit and function of NOR2 at 0.35 μm process Fig 4.3 Circuit of NOR2 built by ms Fig 4.4 L n =L p = 0.5 um, W n =0.7 um, W p =3.25 um, nwell=0.35 V, NOR2 function 30

35 4.1.2 Circuit and function of NAND2 at 0.35 μm process Fig 4.5 Circuit of NAND2 built by ms Fig 4.6 L n =L p = 0.5 um, W n =0.7 um, W p =3.25 um, nwell=0.35 V, NAND2 function 31

36 4.1.3 Circuit and function of INVERTER at 0.35 μm process Fig 4.7 Circuit of Inverter built by ms Fig 4.8 L n =L p = 0.5 um, W n =0.7 um, W p =3.25 um, nwell=0.35 V, Inverter function 32

37 4.2 Three input circuits and functions Fig 4.9 X, Y and Z pulses We used an x-pulse with a width of 10 us and a period of 20 us. The y-pulse had a width of 20 us and a period of 40 us while the z-pulse had a width of 40 us and a period of 80 us. These were the three inputs (see Fig 4.9). Mirror structure performs only Carry Function (see Fig 4.10) at that moment, which is different from the output-wired inverters structure. Fig 4.10 L n =L p = 0.5 um, W n =0.7 um, W p =3.25 um, nwell=0.35 V, Carry function 33

38 4.3 Disscusion regarding circuit functions implemented by mirror structure Compared to the output-wired inverters structure (refer figure 3.4, 3.6, 3.8 and 3.14) we find out that the mirror structure has much better stability. It s clear that the logic one approximately equals 0.7 V and logic zero approximately equals 0 V in the figure. The transistors length and width don t have so big effect on the performance compare to out-wired inverters structure. We will not explain how to use mirror structure to build a whole 16 bit and 32 bit Kogge-Stone adder in detail later because it is exactly same like building Kogge-Stone adder by output-wired inverters structure which we will introduce in next chapter. See the whole circuit in Appendix A (see figure A.18 and A.19). In the next chapter, we will use output-wired inverters structure and mirror structure as basic cell to build the Kogge-Stone parallel adder separately and see the difference. 34

39 Chapter 5 Parallel and Serial Adders and Their Building Blocks In this chapter my major tasks is to use majority three which are either output-wired inverters structure or mirror structure to build the most common Kogge-Stone adder, 16 bit and 32 bit. Before introducing how to build the circuit, I want to tell some basic conceptions about full adder, ripple carry adder and look-ahead Adder which will be a big help for understanding the Kogge-Stone adder later. Spectre simulation for a 0.35 µm CMOS implementation is shown. Schematics can be found in Appendix A (Fig A.1.9 to A.1.14). 5.1 Full Adder The following Boolean expressions describe the full adder [2]. p = a b and g = a b (Equation 5-1-1) Where a and b are the input operands and p and g are propagate and generate signals respectively. Carry is propagated if p is high (see Table 5.1) or is generated if g is high (see Table 5.2). In other words, a carry is generated if both operand bits are 1, and an incoming carry is propagated if one of the operand bits is 1 and the other is 0. Below are two examples of carry propagation and generation (see Fig 5.1 and 5.2). Fig 5.1 Example of carry propagation 35

40 Fig 5.2 Example of carry generation Thus, the sum S and carryout C o signals can be expressed as: S = a b c i and C 0 = g + p Ci (Equation 5-1-2) where C i is the carry-in signal. Table 5.1 Truth table for XOR2: Y X F Table 5.2 Truth table for NAND2: Y X F Table 5.3 Truth table for full adder: Ai Bi Ci Co S Carry

41 5.2 Ripple Carry adder (RCA) The ripple carry adder is a simple adder which generates carries in series (see Fig5.3). It is made up of a series of full adder. It requires the bit output of a previous carry output to act as a carry input signal for the next bit in series. For this reason it is general slow to propagate the signal then in parallel adder. Fig 5.3 N-bit ripple carry adder 5.3 Carry look-ahead adder (CLA) The main idea behind carry look-ahead [3] addition is an attempt to generate all incoming carries in parallel and avoid waiting until the correct carry propagates from the stage (FA) of the adder where it has been generated. It uses the look-ahead technique rather than the carry-rippling technique to speed-up the carry propagation. Let p i = a i b i and g i = a i * b i. P denotes propagate and G denotes generate. Then, s i = p i c i and c i+1 = g i + p i * c i. Expanding the above given equations for N bit adder gives: c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 g 0 + p 1 p 0 c 0. c n-1 = g n-1 + p n-1 g n p n-1 p n-2 p 1 p 0 g p n-1 p n-2 p 1 p 0 c Prefix-tree adders The prefix-tree adder is an extension of the carry look-ahead computation [4] which includes Kogge-Stone adder, Brent-kung adder and Han-carlson adder. Let a n-1, a n-2,, a 0 and b n-1, b n-2,, b 0 be n-bit binary numbers to be added. Let c 0 designate the input carry and c n designate the output carry. For each bit, "propagate"(p i ) and "generate"(g i ) signals are defined, as described in the previous section. Furthermore, for parallelizing the computation of a carry two additional terms are defined: Group Carry Generate (G i:j ) and Group Carry propagate (P i:j ). For each group of bits the Group Carry Generate signal G i:j means that the carry is generated somewhere between stages I and J, and it is 37

42 propagated from that location to stage I. This is implies c i+1 =1 and, in particular, if j = 0, then G i:0 = c i. For each group of bits the Group Carry propagate P i:j means that the carry is propagated from stage J to stage I, i.e. c i+1 =c j. So the formal definition of G i:j and P i:j is expressed using the following relationship: [G i:j, P i:j ] = [g i, p i ] if i = j [G i:j, P i:j ] = [G i:k, P i:k ] o [G k-1:j, P k-1:j ] if i j Where i k j+1 and o operator [4] is introduced by Kogge and Stone adder. See figure5.4 and 5.5. Finally, once the final carries G i:0 for all i < n have been computed, the sub bits are calculated as: S i = p i G i:0 for n>i>1 and S i = p i for i= 0. Figure 5.4 Carry operator Figure 5.5 Carry operator of 2 bit adder 38

43 The Kogge-Stone is ome type of prefix-tree adder. Below is a diagram of 16-bit four stages-two four level cell size type Kogge-Stone adder, See figure 5.6 and 5.7. Figure 5.6 Prefix graph of 16-bit prefix-2 Kogge---Stone adder 39

44 Figure 5.7 Prefix graph of 16-bit prefix-2 Kogge---Stone adder (explaination) 40

45 When I extended 16 bits to 32 bit, the circuit looked like this: see figure 5.8. Figure 5.8 Prefix graph of 32-bit prefix-2 Kogge---Stone adder These prefix-2 Kogge--Stone adders are made up of three parts of basic cells. See figure 5.13, figure 5.14 and figure 5.15 which are built by nand2 (see Fig 5.9), nor2 (see Fig 5.10), inverter (see Fig 5.11) and major3 (see Fig 5.12). output-wired inverter structure and mirror structure are used to build these cells separately. Figure 5.9 NAND2 cell built by either owis or ms Figure 5.10 NOR2 cell built by either owis or ms 41

46 Figure 5.11 INVERTER cell built by either owis or ms Figure 5.12 Major3 cell built by either owis or ms Figure 5.13 Basic cell-one represented by Empty Square 42

47 Figure 5.14 Basic cell-two represented by Circle Figure 5.15 Basic cell-three represented by Crossed Square After done building the Kogge-Stone separately adder by output-wired inverter structure and mirror structure, we will compare these two different results. 43

48 Chapter 6 Simulations of 16 and 32 Bit Kogge-Stone Adder at 0.35 μm process In this chapter, I present you with the simulation results of the16 and 32 bit Kogge-Stone (KS) adders. Spectre simulation results for a 0.35 µm CMOS implementation are shown below. Schematics can be found in Appendix A (Fig A.1.21 to A.1.24). I have included some figures which come from a 16 bit adder (we won t show all the figures from the 32 bit adder here) and tables (data from both 16 and 32 bit adder) to help you understand how my circuit functions. 6.1 Realize adder function After completing our circuit, we should first check whether it works. In our simulation we set all signal bits A 0 ~A 15 to the same pulse (width 20 us and period 40 us); set all signal bits B 0 ~B 15 to the same pulse (width 40 us and period 80 us), see fig It will give four combinations of input which include B i A i equals 00, 01, 10, 11 for each identical bit, so we can check the results to see if the circuit works (see figure 6.2, 6.3, 6.4 and 6.5). Figure 6.1 A 0 15 and B 0 15 pulses Figure 6.2 B i A i equals 00 44

49 Figure 6.3 B i A i equals 01 Figure 6.4 B i A i equals 10 Figure 6.5 B i A i equals 11 45

50 6.2 Simulation of the 16 bit kogge-stone adders implemented by both output-wired inverter structure and mirror structure at 0.35 μm process (V dd =0.7 V) After performing simulations, we observed that although we put the same signal in each bit, the first sum bit S 0 (see figure 6.6) is different from the second sum bit S 1 (see figure 6.7). This is because the S 0 does not receive any carry input. At the same time, sum bits S 1 to S 15 have the same logic output because they all receive a carry from the previous bit. We also find that bits S 1 to S 15 are not stable when the circuit is built using the outputwired inverter structure. Logic one is not always kept at 700 mv, but mv or mv instead. If we use mirror structure instead of output-wired inverters structure, we will get a more stable Sum output. See figure 6.10 and Now we look carefully at the graphs we generated and check each bit carefully. In figure 6.6 and 6.10, when B 0 A 0 is 00, bit S 0 is 0; when B 0 A 0 is 01 or 10, bit S 0 equals 1; when B 0 A 0 is 11, bit S 0 equals 0. In figure 6.7 and 6.11, the situation is a little different. When both B 1 ~B 15 and A 1 ~A 15 inputs are11...1which corresponds S 1 ~S 15 equals1 because bits S receive a carry in bit from the previous bit. Here, we are more interested in finding out the worst delay [5] which happens when the first bit generates a carry bit and this bit leads to generate a series carry bit later (see figure 6.8, 6.9, 6.12 and 6.13) because it will take the longest wait time. For observing this situation, we set all signal bitsb 0 ~B 15 equal to 1.1 and A 1 ~A 15 equals 0...0, then we set bit A 0 to change from 0 to1 as a pulse width of 20 us and a period 40 us. We will find that mirror construct circuit has a longer worst delay than the output-wired inverter structure circuit, but seems more stable. There are two definitions mentioned in this chapter. One is propagation delay [6], and another is power-delay product [6]. Propagation delays: the propagation delay t p of a gate defines how quickly it responds to a change at its input(s). It expresses the delay experienced by a signal when passing through a gate. It is measured between the 50% transition points of the input and output waveforms. Power delay product (PDP): the propagation delay and power consumption of a gate are related ---the propagation delay is mostly determined by the speed at which a given amount of energy can be stored on the gate capacitors. The faster the energy transfer (or the higher the power consumption), the faster the gate becomes. 46

51 Figure 6.6 First sum bit S 0 of 16-bit KS adder built by owis (A 0, B 0 are inputs) Figure 6.7 Second sum bit S 1 of 16-bit KS adder built by owis (A 1, B 1 are inputs) 47

52 Figure 6.8 Carry bits C 0 ~C 7 of 16-bit KS adder built by owis Figure 6.9 Carry bits C 8 ~C 15 of 16-bit KS adder built by owis 48

53 Figure 6.10 First sum bit S 0 of 16-bit KS adder built by ms (A 0, B 0 are inputs) Figure 6.11 Second sum bit S 1 of 16-bit KS adder build by ms (A 1, B 1 are inputs) 49

54 Figure 6.12 Carry bits C 0 ~C 7 of 16-bit KS adder built by ms Figure 6.13 Carry bits C 8 ~C 15 of 16-bit KS adder built by ms 50

55 6.3 Simulation results of the 16 and 32 bit kogge-stone adders at 0.35 μm process at different voltage levels Now, we try to record the worst delay, power consumption, and power delay of 16 and 32 bit circuits. T d : worst delay time. I: average current flow to ground. V dd : power supply voltage Simulation results of the 16 and 32 bit kogge-stone adders implemented by output-wired inverter structure An example of 16 bit adder built by output-wired inverter structure : At 700 mv power supply: We estimate the worst delay of 16 bit KS adder is approximately 1.46 * 10-7 S. Power consumption of 16 bit KS adder: P = V dd * I 0.7 V * (4.97 * 10-4 A) 3.48 * 10-4 W. Power delay of 16 bit KS adder: PDP = P * T d = V dd * I * T d 0.7 V * (4.97 * 10-4 A) * (1.46 * 10-7 S) 5.08 * J. Table bit KS adder built by output-wired inverter structure : (0.35 um process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * Table bit KS adder built by output-wired inverter structure : (0.35 um process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * *

56 6.3.2 Simulation results of the 16 and 32 bit kogge-stone adders implemented by mirror structure An example of 16 bit adder built by mirror structure : At 700 mv power supply: We estimate the worst delay of 16 bit KS adder is approximately 4.41 * 10-7 S. Power consumption of 16 bit KS adder: P = V dd * I 0.7 V * (6.35 * 10-8 A) 4.45 * 10-8 W. Power delay of 16 bit KS adder: PDP= P * T d = V dd * I * T d 0.7 V * (6.35 * 10-8 A) * (4.41 * 10-7 S) 1.96 * J. Table bit KS adder built by mirror structure : (0.35 um process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * Table bit KS adder built by mirror structure : (0.35 um process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * Discussion regarding simulation results of the 16 and 32 bit kogge-stone adders at 0.35 μm process at different voltage levels Here we have recorded the data from three different power supplies which are 500 mv, 600 mv and 700 mv. The circuit couldn t function well under 400mV voltage supply. There could be several reasons for this. For example, the N- and P-transistor were not perfectly balanced or the building blocks for the Kogge-Stone adder have too little voltage gain and so on. Comparing data from table 6.1, 6.2, 6.3 and 6.4, we found that the circuit has a bigger worst delay if we use the mirror structure ( ms ) to build an adder than a circuit which utilizes the output-wired inverter structure ( owis ) at the same voltage supply. However, the speed of an adder built by ms can catch up to an adder built by owis, while still requiring much less power and energy. The most interesting thing is when the power supply decreases; power consumption of the adder built by owis will decrease much more significantly than the power consumption of an adder built by ms. That s why the power delay of the adder built by owis would decrease when the power supply concurrently decreases, but an adder built by ms behaves oppositely. Output-wired inverter structure would be greatly improved in performance as the power supply becomes lower and lower. 52

57 Chapter 7 Simulations of 16 and 32 Bit Ripple Carry Adder at 0.35 μm process In this chapter, I present the simulation results of the16 and 32 bit Ripple Carry adders (RCA). Since building a ripple Carry is not my major task in this thesis, I won t explain how to build a Ripple Carry adder in detail here, but we are still very interested in the data generated from this type of circuit because we will do a comparison with the Kogge- Stone adder to help us understand the circuit s characteristics well. The ripple carry adder is a simple adder which generates carries in series. It is made up of a series of full adder. (Recall 5.2 in chapter 5). The same transistor size used previously and Spectre simulation results for a 0.35 µm CMOS implementation are shown here. Schematics can be found in Appendix A (Fig A.1.15 to A.1.20). 7.1 Simulation results of the 16 and 32 bit Ripple Carry adders at 0.35 μm process at different voltage levels T d : worst delay time. I: average current flow to ground. V dd : power supply voltage Simulation results of the 16 and 32 bit Ripple Carry adders implemented by output-wired inverter structure An example of 16 bit adder built by output-wired inverter structure : At 700 mv power supply: We estimate the worst delay of 16 bit RCA adder is approximately 2.63 * 10-7 S. Power consumption of 16 bit RCA adder: P = V dd * I 0.7 V * (4.97 * 10-4 A) 5.93 * 10-5 W. Power delay of 16 bit RCA adder: PDP = P * T d = V dd * I * T d 0.7 V * (4.97 * 10-4 A) * (1.46 * 10-7 S) 1.56 * J. Table bit RCA built by output-wired inverters structure : (0.35 um process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * *

58 Table bit RCA built by output-wired inverters structure : (0.35 um process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * Simulation results of the 16 and 32 bit Ripple Carry adders implemented by mirror structure An example of 16 bit adder built by mirror structure : At 700 mv power supply: We estimate the worst delay of 16 bit RCA adder is approximately 7.47 * 10-7 S. Power consumption of 16 bit RCA adder: P = V dd * I 0.7 V * (4.97 * 10-4 A) 1.40 * 10-8 W. Power delay of 16 bit RCA adder: PDP = P * T d = V dd * I * T d 0.7 V * (4.97 * 10-4 A) * (1.46 * 10-7 S) 1.05 * J. Table bit RCA built by mirror structure : (0.35 um process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * Table bit RCA built by mirror structure : (0.35 um process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * *

59 7.2 Discussion regarding simulation results of the 16 and 32 bit Ripple Carry adders at 0.35 μm process at different voltage levels As with the Kogge-Stone adder, we recorded the data from three different power supplies which are 500 mv, 600 mv and 700 mv. Comparing data from table 7.1, 7.2, 7.3 and 7.4, we found that the circuit has a bigger worst delay if we use the mirror structure ( ms ) to build an adder than utilizes the output-wired inverter structure ( owis ), which was approximately a 3 times difference at the same voltage supply. However, the speed of an adder built by ms can catch up to the adder built by owis, while still requiring much less power and energy. The most interesting thing is that as the power supply decreases; the power consumption of the adder built by owis will decrease much more significantly than the power consumption of an adder built by ms. That s why the power delay of the adder built by owis would decrease when the power supply decreases, but an adder built by ms behaves in an opposite fashion. Output-wired inverter structure would be greatly improved in performance as the power supply becomes lower and lower. 55

60 Chapter 8 HSpice simulation at 70 nm process In this chapter we will use a powerful general purpose analog circuit simulator-- SPICE [13] to verify our circuit designs and to predict the circuit behavior. The Berkeley Predictive technology 70 nm Spice model card [12] was used here. All the netlist and code can be found in Appendix A (A.2).We will simulate the entire 16 bit and 32 bit Kogge-Stone circuits which were implemented by output-wired inverter structure and mirror structure individually. I also have included some figures which come from the 16 bit adder (we won t show figures from the 32 bit adder individually here) and tables (data from both 16 and 32 bit adder) to help you understand how my circuit functions. 8.1 Finding the suitable transistor s size Here we chosed size L n = L p = 0.07 um, W n = 0.1 um and W p = 0.15 um for 70 nm process. We also included the Spice code for balanced an inverter at 70 nm process (see Appendix A, A.2.1) Simulation result for balanced inverter Simulaiton result for a balanced inverter refers figure

61 Wave D0:sw0:v(in) D0:sw0:v(out) Symbol Voltages (lin) 700m 650m 600m 550m 500m 450m 400m 350m 300m 250m 200m 150m 100m 50m 0 file inv.sp 0 200m 400m 600m Voltage X (lin) (VOLTS) Figure 8.1 A balanced inverter (yellow represents input signal, red represents output signal) 57

62 8.2 Simulation of 16 bit Kogge-Stone adder implemented by both output-wired inverter structure and mirror structure at 70 nm process at different voltage levels We set all signal bitsb 0 ~B 15 equals 1.1(B 0 ~B 31 equals 1.1 for 32 bit circuit) and A 1 ~A 15 equals (A 1 ~A 31 equals for 32 bit circuit), then we set bit A 0 to change from 0 to1 at a pulse width of 20 us and period of 40 us which corresponds to the worst delay situation. Spice code for all the simulations could be found in Appendix A (A.2) Simulation of 16 bit Kogge-Stone adder at 70 nm process (V dd = 0.7 V) Wave D0:tr0:v(ina0) D0:tr0:v(outg15t0) D0:tr0:v(s15) Symbol Voltages (lin) 600m 400m 200m 0 file ks16wd.sp Voltages (lin) 600m 400m 200m 0 Voltages (lin) 400m 200m 0 20u 40u 60u Time (lin) (TIME) 80u Figure bit KS adder which is built by output-wired inverter structure. Yellow represents input signal A 0, red represents output signal C 15 and blue represents output signal S 15 (V dd = 0.7 V) 58

63 Wave D0:tr0:v(ina0) D0:tr0:v(outg15t0) D0:tr0:v(s15) Symbol Voltages (lin) 600m 400m 200m 0 file ks16wd.sp Voltages (lin) 600m 400m 200m 0 Voltages (lin) 600m 400m 200m u 40u 60u Time (lin) (TIME) 80u Figure bit KS adder which is built by mirror structure. Yellow represents input signal A 0, red represents output signal C 15 and blue represents output signal S 15 (V dd = 0.7 V) 59

64

65 Wave D0:tr0:v(ina0) D0:tr0:v(outg15t0) D0:tr0:v(s15) Symbol Voltages (lin) 600m 400m 200m 0 file ks16wd.sp Voltages (lin) 600m 400m 200m 0 Voltages (lin) 600m 400m 200m u 40u 60u Time (lin) (TIME) 80u Figure bit KS adder which is built by mirror structure. Yellow represents input signal A 0, red represents output signal C 15 and blue represents output signal S 15 (V dd = 0.6 V) 61

66 8.2.3 Simulation of 16 bit Kogge-Stone adder at 70 nm process (V dd = 0.5 V) Wave D0:tr0:v(ina0) D0:tr0:v(outg15t0) D0:tr0:v(s15) Symbol Voltages (lin) 400m 200m 0 file ks16wd.sp Voltages (lin) 400m 200m 0 Voltages (lin) 200m 0 20u 40u 60u Time (lin) (TIME) 80u Figure bit KS adder which is built by output-wired inverter structure. Yellow represents input signal A 0, red represents output signal C 15 and blue represents output signal S 15 (V dd = 0.5 V) 62

67 Wave D0:tr0:v(ina0) D0:tr0:v(outg15t0) D0:tr0:v(s15) Symbol Voltages (lin) 400m 200m 0 file ks16wd.sp Voltages (lin) 400m 200m 0 Voltages (lin) 400m 200m u 40u 60u Time (lin) (TIME) 80u Figure bit KS adder which is built by mirror structure. Yellow represents input signal A 0, red represents output signal C 15 and blue represents output signal S 15 (V dd = 0.5 V) 63

68 8.2.4 Simulation of 16 bit Kogge-Stone adder at 70 nm process (V dd = 0.4 V) Wave D0:tr0:v(ina0) D0:tr0:v(outg15t0) D0:tr0:v(s15) Symbol Voltages (lin) 400m 200m 0 file ks16wd.sp Voltages (lin) 400m 200m 0 Voltages (lin) 300m 200m 100m 0 20u 40u 60u Time (lin) (TIME) 80u Figure bit KS adder which is built by output-wired inverter structure. Yellow represents input signal A 0, red represents output signal C 15 and blue represents output signal S 15 (V dd = 0.4 V) 64

69 Wave D0:tr0:v(ina0) D0:tr0:v(outg15t0) D0:tr0:v(s15) Symbol Voltages (lin) 400m 200m 0 file ks16wd.sp Voltages (lin) 400m 200m 0 Voltages (lin) 400m 200m u 40u 60u Time (lin) (TIME) 80u Figure bit KS adder which is built by mirror structure. Yellow represents input signal A 0, red represents output signal C 15 and blue represents output signal S 15 (V dd = 0.4 V) 8.3 Simulation results of 16 and 32 bit Kogge-Stone adder at 70 nm process at different voltage levels T d : worst delay time. I: average current flow to ground. V dd : power supply voltage Simulation results of the 16 and 32 bit kogge-stone adders implemented by output-wired inverter structure An example of 16 bit adder built by output-wired inverter structure : At 700 mv power supply: We estimate the worst delay of 16 bit KS adder is approximately 2.30 * S. Power consumption of 16 bit KS adder: P = V dd * I 0.7 V * (4.97 * 10-4 A) 5.04 * 10-3 W. Power delay of 16 bit KS adder: PDP = P * T d = V dd * I * T d 0.7 V * (4.97 * 10-4 A) * (1.46 * 10-7 S) 1.16 * J. 65

70 Table bit KS adder built by output-wired inverter structure : (70 nm process): Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * * * * Table bit KS adder built by output-wired inverter structure : (70 nm process): Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * * * * Simulation results of the 16 and 32 bit kogge-stone adders implemented by mirror structure An example of 16 bit adder built by mirror structure : At 700 mv power supply: We estimate the worst delay of 16 bit KS adder is approximately 1.18 * 10-9 S. Power consumption of 16 bit KS adder: P = V dd * I 0.7 V * (8.1 * 10-8 A) 1.20 * 10-6 W. Power delay of 16 bit KS adder: PDP= P * T d = V dd * I * T d 0.7 V * (8.1 * 10-8 A) * (4.41 * 10-7 S) 1.42 * J. Table bit KS adder built by mirror structure : (70 nm process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * * * *

71 Table bit KS adder built by mirror structure : (70 nm process) Power supply (mv) Worst delay ( S) Power consumption ( W) Power delay ( J) * * * * * * * * * * * * Discussion regarding simulation results of 16 and 32 bit Kogge-Stone adder at 70 nm process at different voltage levels When we used the 70 nm process in Hspice to simulate the circuit, the circuit had the ability to function with a very low power supply. The lowest power supply for four key parts (Nand2, Nor2, Inverter, Carry ) to function is 0.2 V for my circuits, but the lowest power supply for the entire 16 bit and 32 bit Kogge-Stone adder to function is 0.4 V. One always could modify the circuits and enable them to work at an even lower supply voltage (for example at a subthreshold level), but here I just recorded the data when the power supply voltages are 400, 500, 600 and 700 mv. Comparatively, at the same power supply, the circuit resulted in a smaller time delay but bigger power consumption when the spice simulation at the 70 nm process was used than with the Cadence simulation at 0.35 um. 67

72 Chapter 9 Discussion and Conclusion In this chapter, I will use charts to analyze the data which we obtained from previous chapters (include chapter 6, 7 and 8). It may help us to define the characteristics of the Kogge-Stone and Ripple Carry adders as well as determine any differences between the two. 9.1 Performance of 16 and 32 bit Kogge-Stone adders Data from the Kogge-Stone adder can be obtained from chapter 6 (table 6.1, 6.2, 6.3 and 6.4) for 0.35 μm process simulation in Cadence and chapter 8 (table 8.1, 8.2, 8.3 and 8.4) for 70 nm process Hspice simulation. Worst Delay, Power Consumption and Power- Delay-Product were recorded Performance of 16 and 32 bit Kogge-Stone adders implemented by output-wired inverter structure at 0.35 μm process Worst Delay mv 600mv 700mv P16(nS) P32(nS) Figure 9.1 Worst Delay (0.35 µm process), 16 and 32 bit Kogge-Stone adder built by output-wired inverter structure 68

73 Power Consumption 500mv 600mv 700mv P16(uW) P32(uW) Figure 9.2 Power Consumption (0.35 µm process), 16 and 32 bit Kogge-Stone adder built by output-wired inverter structure Power Delay mv 600mv 700mv P16(pJ) P32(pJ) Figure 9.3 Power Delay (0.35 µm process), 16 and 32 bit Kogge-Stone adder built by output-wired inverter structure 69

74 9.1.2 Performance of 16 and 32 bit Kogge-Stone adders implemented by mirror structure at 0.35 μm process Worst Delay P16(nS) P32(nS) mv 600mv 700mv Figure 9.4 Worst Delay (0.35 µm process), 16 and 32 bit Kogge-Stone adder built by mirror structure Power Consumption mv 600mv 700mv P16(pW) P32(pW) Figure 9.5 Power Consumption (0.35 µm process), 16 and 32 bit Kogge-Stone adder built by mirror structure 70

75 Power Delay 500mv 600mv 700mv P16(fJ) P32(fJ) Figure 9.6 Power Delay (0.35 µm process), 16 and 32 bit Kogge-Stone adder built by mirror structure Performance of 16 and 32 bit Kogge-Stone adders implemented by output-wired inverter structure at 70 nm process Worst Delay mv 500mv 600mv 700mv P16(pS) P32(pS) Figure 9.7 Worst Delay (70 nm process), 16 and 32 bit Kogge-Stone adder built by output-wired inverter structure 71

76 Power Consumption 400mv 500mv 600mv 700mv P16(uW) P32(uW) Figure 9.8 Power Consumption (70 nm process), 16 and 32 bit Kogge-Stone adder built by output-wired inverter structure Power Delay 4 3,5 3 2,5 2 1,5 1 0, mv 500mv 600mv 700mv P16(pJ) P32(pJ) Figure 9.9 Power Delay (70 nm process), 16 and 32 bit Kogge-Stone adder built by output-wired inverter structure 72

77 9.1.4 Performance of 16 and 32 bit Kogge-Stone adders implemented by mirror structure at 70 nm process Worst Delay mv 500mv 600mv 700mv P16(nS) P32(nS) Figure 9.10 Worst Delay (70 nm process), 16 and 32 bit Kogge-Stone adder built by mirror structure Power Consumption 3 2,5 2 1,5 1 P16(uW) P32(uW) 0, mv 500mv 600mv 700mv Figure 9.11 Power Consumption (70 nm process), 16 and 32 bit Kogge-Stone adder built by mirror structure 73

78 4,5 4 3,5 3 2,5 2 1,5 1 0,5 0 Power Delay 400mv 500mv 600mv 700mv P16(fJ) P32(fJ) Figure 9.12 Power Delay (70 nm process), 16 and 32 bit Kogge-Stone adder built by mirror structure Analyses for Kogge-Stone adder (an example of parallel adder): Notice: Here, ms represents mirror structure and owis represents output-wired inverter structure for convenience. Worst delay: From the charts above, we can make the conclusion that the Kogge-Stone adder s worst delay is heavily dependent on power supply. The lower the power supply is, the longer the delay becomes. The 32 bit adder s delay is approximately times that of the 16 bit adder s delay at the same voltage supply (Refer figure 9.1, 9.4, 9.7 and 9.10). 16 and 32 bit circuits built by ms usually have a longer worst delay than the same bit circuits built by owis at the same voltage supply. Power Consumption: It seems that the amount of power consumption is related to the power supply. The higher the power supply is, the larger the power consumption becomes. The 32 bit adder s power consumption is approximately 1.8~2.5 times that of the 16 bit adder s power consumption at the same voltage supply. We also notice the adder built by ms has a significantly lower power consumption than the adder built by owis when the power supplies are 700 mv, 600 mv and 500 mv at 0.35 μm processes, individually, and 700 mv, 600 mv, 500 mv and 400 mv at 70 nm processes, individually. We also found that when the power supply decreases, the power consumption of the adder built by owis will decrease much more significantly than the power consumption of an adder built by ms. (Refer figure 9.2, 9.5 and recall 6.4, in chapter 6). Power Delay Product: The adder built by ms usually has a significantly smaller PDP than the same bit adder built by owis when the same voltage supply was used. In the 0.35 μm process, we found that the PDP of the adder built by owis would decrease 74

79 when the power supply decreases, but an adder built by ms behaves in an opposite fashion (Refer figure 9.3 and 9.6). 9.2 Performance of 16 and 32 bit Ripple Carry adder Data from the Ripple Carry adder can be obtained from chapter7 (table 7.1, 7.2, 7.3 and 7.4) for 0.35 μm process simulation in Cadence. Similarly, as with the Kogge-Stone adders, Worst Delay, Power Consumption, and Power-Delay-Product were recorded Performance of 16 and 32 bit Ripple Carry adders implemented by output-wired inverter structure at 0.35 μm process Worst Delay mv 600mv 700mv S16(nS) S32(nS) Figure 9.13 Worst Delay (0.35 µm process), 16 and 32 bit Ripple Carry adder built by output-wired inverter structure 75

80 Power Consumption 500mv 600mv 700mv S16(uW) S32(uW) Figure 9.14 Power Consumption (0.35 µm process), 16 and 32 bit Ripple Carry adder built by output-wired inverter structure Power Delay mv 600mv 700mv S16(pJ) S32(pJ) Figure 9.15 Power Delay (0.35 µm process), 16 and 32 bit Ripple Carry adder built by output-wired inverter structure 76

81 9.2.2 Performance of 16 and 32 bit Ripple Carry adders implemented by mirror structure at 0.35 μm process Worst Delay mv 600mv 700mv S16(nS) S32(nS) Figure 9.16 Worst Delay (0.35 µm process), 16 and 32 bit Ripple Carry adder built by mirror structure Power Consumption S16(pW) S32(pW) mv 600mv 700mv Figure 9.17 Power Consumption (0.35 µm process), 16 and 32 bit Ripple Carry adder built by mirror structure 77

82 Power Delay 500mv 600mv 700mv S16(fJ) S32(fJ) Figure 9.18 Power Delay (0.35 µm process), 16 and 32 bit Ripple Carry adder built by mirror structure I Analyses for Ripple Carry adder (an example of serial adder): Notice: Here, ms represents mirror structure and owis represents output-wired inverter structure for convenience. Worst delay: From the charts above, we can make the conclusion that the Ripple Carry adder s worst delay is also heavily dependent on the power supply. The lower the power supply is, the longer the delay becomes. The 32 bit adder s delay is exactly 2 times that of the 16 bit adder s delay at the same voltage supply (Refer figure 9.13 and 9.16). The 16 and 32 bit circuits built by ms usually have a longer worst delay than the same bit circuits built by owis at the same voltage supply. Power Consumption: It is evident that the power consumption is related to the power supply. The higher the power supply is, the larger the power consumption becomes. The 32 bit adder s power consumption is 2 times that of the 16 bit adder s power consumption at the same voltage supply (Refer figure 9.14 and 9.17). We also noticed that the adder built by ms has a smaller power consumption than the adder built by owis when the power supplies are 700 mv, 600 mv and 500 mv individually. We also found that when the power supply decreases, the power consumption of the adder built by owis will decrease much more significantly than the power consumption of an adder built by ms (Refer figure 9.14, 9.17 again and recall 7.2, in chapter 7). Power Delay Product: The adder built by ms usually has a significantly smaller PDP than the same bit adder built by owis when the same voltage supply was used. In the 0.35 μm process, we found that the PDP of the adder built by owis would decrease when power supply decreases, but the adder built by ms behaves in an opposite fashion (Refer figure 9.15 and 9.18). 78

83 9.3 Kogge-Stone adders VS Ripple Carry adder As expected, the KS adder is faster than the RCA when the same power supply, technology node, and transistor size are used. The Kogge-Stone adder has a smaller worst delay due to the avoidance of waiting for a carry input from the previous bit (it generates a carry in parallel instead). The biggest disadvantage of the Kogge-Stone adder is that it consumes more power than a Ripple Carry adder due to complicated wiring and large numbers of transistors. The Ripple Carry adder can match the speed of the Kogge-Stone adder, while still requiring less power and energy, see figure For example, comparing two 32-bit adders regarding worst delay and power consumption at 0.7 V voltage supply: TD RCA /TD KS = 5.24 * 10-7 / 1.81 * (1), P KS /P PCA = 7.91 * 10-4 / 1.18 * (2) (Data come from table 6.2 and 7.2). The Serial adder can give a better performance for a lower power supply [5], [11] which was confirmed. Figure bit KSA VS 32-bit RCA at 0.35 µm process (Power&delay on top, power delay& delay on bottom) 79