Contents 1 Introduction 2 MOS Fabrication Technology

Transcription

1 Contents 1 Introduction Introduction Historical Background [1] Why Low Power? [2] Sources of Power Dissipations [3] Dynamic Power Static Power Low-Power Design Methodologies Chapter Summary Review Questions References MOS Fabrication Technology Introduction Basic Fabrication Processes [1, 2] Wafer Fabrication Oxidation Mask Generation Photolithography Diffusion Deposition nmos Fabrication Steps [2, 3] CMOS Fabrication Steps [2, 3] The n-well Process The p-well Process Twin-Tub Process Latch-Up Problem and Its Prevention Use of Guard Rings Use of Trenches Short-Channel Effects [6] Channel Length Modulation Effect xiii

2 xiv Contents Drain-Induced Barrier Lowering Channel Punch Through Emerging Technologies for Low Power Hi-K Gate Dielectric Lightly Doped Drain Source Silicon on Insulator Advantages of SOI FinFET Chapter Summary Review Questions References MOS Transistors Introduction The Structure of MOS Transistors The Fluid Model The MOS Capacitor The MOS Transistor Modes of Operation of MOS Transistors [2] Electrical Characteristics of MOS Transistors Threshold Voltage Transistor Transconductance g m Figure of Merit Body Effect Channel-Length Modulation MOS Transistors as a Switch [3] Transmission Gate Chapter Summary Review Questions References MOS Inverters Introduction Inverter and Its Characteristics MOS Inverter Configurations Passive Resistive as Pull-up Device nmos Depletion-Mode Transistor as Pull up nmos Enhancement-Mode Transistor as Pull up The pmos Transistor as Pull Up pmos Transistor as a Pull Up in Complementary Mode Comparison of the Inverters Inverter Ratio in Different Situations An nmos Inverter Driven by Another Inverter An nmos Inverter Driven Through Pass Transistors... 84

3 Contents xv 4.5 Switching Characteristics Delay-Time Estimation Ring Oscillator Delay Parameters Resistance Estimation Area Capacitance of Different Layers Standard Unit of Capacitance Cg The Delay Unit Driving Large Capacitive Loads Super Buffers BiCMOS Inverters Buffer Sizing Chapter Summary Review Questions References MOS Combinational Circuits Introduction Pass-Transistor Logic Realizing Pass-Transistor Logic Advantages and Disadvantages Pass-Transistor Logic Families Gate Logic Fan-In and Fan-Out nmos NAND and NOR Gates CMOS Realization Switching Characteristics CMOS NOR Gate CMOS Complex Logic Gates MOS Dynamic Circuits Single-Phase Dynamic Circuits Two-Phase Dynamic Circuits CMOS Dynamic Circuits Advantages and Disadvantages Domino CMOS Circuits NORA Logic Some Examples Chapter Summary Review Questions References Sources of Power Dissipation Introduction Short-Circuit Power Dissipation [1]

4 xvi Contents 6.3 Switching Power Dissipation [1] Dynamic Power for a Complex Gate Reduced Voltage Swing Internal Node Power Switching Activity [2, 3] Switching Activity of Static CMOS Gates Inputs Not Equiprobable Mutually Dependent Inputs Transition Probability in Dynamic Gates Power Dissipation due to Charge Sharing Glitching Power Dissipation Leakage Power Dissipation [4] p n Junction Reverse-Biased Current Band-to-Band Tunneling Current Subthreshold Leakage Current Conclusion Chapter Summary Review Questions References Supply Voltage Scaling for Low Power Introduction Device Feature Size Scaling [1] Constant-Field Scaling Constant-Voltage Scaling Short-Channel Effects Architectural-Level Approaches Parallelism for Low Power Multi-Core for Low Power Pipelining for Low Power Combining Parallelism with Pipelining Voltage Scaling Using High-Level Transformations Multilevel Voltage Scaling Challenges in MVS Voltage Scaling Interfaces Converter Placement Floor Planning, Routing, and Placement Static Timing Analysis Power-Up and Power-Down Sequencing Clock Distribution Low-Voltage Swing Dynamic Voltage and Frequency Scaling Basic Approach DVFS with Varying Work Load The Model

5 Contents xvii Workload Prediction Discrete Processing Rate Latency Overhead Adaptive Voltage Scaling Subthreshold Logic Circuits Chapter Summary Review Questions References Switched Capacitance Minimization Introduction System-Level Approach: Hardware Software Codesign Transmeta s Crusoe Processor The Hardware The Software Bus Encoding Gray Coding One-Hot Coding Bus-Inversion Coding T0 Coding Clock Gating CG Circuits CG Granularity Gated-Clock FSMs FSM State Encoding FSM Partitioning Operand Isolation Precomputation Glitching Power Minimization Logic Styles for Low Power Static CMOS Logic Dynamic CMOS Logic PTL Synthesis of Dynamic CMOS Circuits Synthesis of PTL Circuits Implementation and Experimental Results Some Related Techniques for Dynamic Power Reduction Chapter Summary Review Questions References Leakage Power Minimization Introduction Fabrication of Multiple Threshold Voltages Multiple Channel Doping

6 xviii Contents Multiple Oxide CMOS Multiple Channel Length Multiple Body Bias VTCMOS Approach Transistor Stacking MTCMOS Approach Power Gating [8] Clock Gating Versus Power Gating Power-Gating Issues Isolation Strategy State Retention Strategy Power-Gating Controller Power Management Combining DVFS and Power Management Dual-V t Assignment Approach (DTCMOS) [10] Delay-Constrained Dual-V t CMOS Circuits [12] Energy-Constrained Dual-V t CMOS Circuits[13] Dynamic V th Scaling Chapter Summary Review Questions References Adiabatic Logic Circuits Introduction Adiabatic Charging Adiabatic Amplification Adiabatic Logic Gates Pulsed Power Supply Stepwise Charging Circuits Stepwise Driver Using Tank Capacitors Partially Adiabatic Circuits Efficient Charge Recovery Logic Positive Feedback Adiabatic Logic Circuits N 2N2P Inverter/Buffer Some Important Issues Chapter Summary Review Questions References Battery-Aware Systems Introduction The Widening Battery Gap [1] Overview of Battery Technologies Nickel Cadmium Nickel Metal Hydride

7 Contents xix Lithium Ion Rechargeable Alkaline Li Polymer Battery Characteristics [4, 5] Rate Capacity Effect Recovery Effect Memory Effect Usage Pattern Battery Age Principles of Battery Discharge Battery Modeling Battery-Driven System Design Multi-battery System Battery-Aware Task Scheduling Task Scheduling with Voltage Scaling [12] Wireless Sensor Networks Energy-Aware Routing Assisted-LEACH Conclusion Chapter Summary Review Questions References Low-Power Software Approaches Introduction The Hardware Machine-Independent Software Optimizations Compilation For Low Power Combining Loop Optimizations with DVFS Loop Unrolling Loop Tiling Loop Permutation Strength Reduction Loop Fusion Loop Peeling Loop Unswitching Power-Aware Software Prefetching Compilation For Low Power Experimental Methodology and Results Conclusions Chapter Summary Review Questions References Index

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