Signal Technologies 1

Transcription

1 Signal Technologies 1

2 Gunning Transceiver Logic (GTL) - evolution Evolved from BTL, the backplane transceiver logic, which in turn evolved from ECL (emitter-coupled logic) Setup of an open collector bus system using BTL devices A reduced voltage swing An open collector output stage The falling signal edge is actively generated by the driver and rising edge is generated by the passive pull-up up network The resistor R in the passive pull-up up network is matched to the resistance of the loaded backplane 2

3 Gunning Transceiver Logic Open collector bus system using GTL devices GTL has a fast edge rate and reduced voltage output levels from BTL The GTL driver has an open collector output, but the diode in the e open collector output that is found in BTL is not present in GTL The receiver as with BTL is designed as a differential amplifier, guaranteeing stable threshold voltages at the receiver A pull-up up resistor R at the line end is matched to the loaded trace impedance to avoid line reflections 3

4 Gunning Transceiver Logic Plus (GTLP) High-speed, high-performance backplane transceivers Operate like the GTL family except for two major differences: Optimized with slower edge rates for the distributed loads found in multi-slot backplanes, Supports live insertion applications with internal pre-charge circuitry to PCB Simplified partial schematic of a typical GTLP devices to backplane GTLP is commonly designed with two ports, an LVTTL/TTL I/O which is referred to as the A Port or a GTLP I/O which is referred ed to as the B Port Both ports are bidirectional 4

5 Controlled edge rates GTLP Device Features (1) Incorporates output edge control (OEC) circuitry to address the output switching noise problem with high-speed devices Edge control incorporates wave-shaping techniques that optimize GTLP devices for driving backplanes Control the output level transition to minimize switching noise and EM interface and reduce signal-settling settling time GTLP transition waveform The area of the output transition are addressed by the GTLP output control circuitry The ability to vary rise and fall times allows adjusting for various far- end loads 5

6 Bushold (A port) GTLP Device Features (2) Designed to tolerate floating input conditions hold an undriven data-bus line in a valid logic state Simplified schematic diagram of bushold circuitry Uses a low drive inverters in the device input stage that provides feedback to the input of the device and the bus When the signal driving the input is removed, the inverter will maintain the last received valid signal level on the device input and bus line until it is overdriven by the next incoming signal Voltage-in versus current-in sweep of bushold device I I(HOLD) is the bushold input minimum drive. This is the minimum amount of current the circuit is capable of supplying I I(OD) is the bushold input over-drive current to change state. This is the minimum amount of current that is necessary to overcome the bushold 6 circuit and cause the input to change states

7 GTLP Backplane Design Considerations Termination resistor should match the backplane impedance for best signal integrity The impedance is a function of natural trace impedance (Z 0 ), stub length, connector impedance, device impedance, and card spacing Closer spacing reduces the effective impedance and requires a smaller termination resistor R T vs. slot spacing with GTLP waveform with matched vs. over- medium and high drive devices matched and under-matched termination! 7

8 Typical GTLP backplane GTLP Backplane The bus is pulled high to the termination voltage (V TT =1.5V) through the termination resistance (R TT =22 Ohm) when the GTLP driver s s open drain output stage is off and pulled low when GTLP driver s s open drain output stage is on The advantage of the open drain backplane is that there is no bus s contention, it is simple to implement and there is less power consumption 8

9 Low Voltage Differential Signalling (LVDS) 9

10 Introduction LVDS allows data transmission at hundreds and even thousands of megabits per second Its low swing and its current-mode driver outputs create low noise and provide low power consumption across large range of data rates LVDS drivers can transmit signal over long traces LVDS devices usually require controlled-impedance circuit-board traces, connectors, and cables to maintain signal integrity 10

11 Scope of LVDS Applications The high-speed and low power/noise/cost benefits of LVDS broaden the scope of LVDS applications far beyond those for traditional technologies. The following table provides some examples of LVDS applications. 11

12 LVDS Principle of Operation (1) Simplified diagram of an LVDS driver and receiver connected via 100Ohm differential impedance medium Current source boosts PSRR (a) (b) Current flowing from the driver s s true output down through the 100Ohm termination resistor; Current flowing from the driver s s inverted output up through the 100Ohm termination resistor 12

13 LVDS Principle of Operation (2) LVDS outputs consist of a current source (nominal 3.5mA) which drives a differential trace or line. The basic receiver has high dc input impedance, so the majority of the driver current flows across the 100 Ohm termination resistor, generating about 350mV across the resistor and receiver input When the driver switches, it changes the direction of current flow across the resistor, thereby creating a valid one or zero logic state Commutation of a single_current_source current to make it flow in both directions gives LVDS power advantage 13

14 LVDS Principle of Operation (3) Voltages generated across the LVDS terminating resistor assuming no losses or distortion over the interconnect between the driver and terminating resistor at the receiver OD : differential output voltage OH : single-ended voltages because they are measured with respect to ground OS : halfway between V OL and V OH V OD V OL /V OH V OS 14

15 LVDS Principle of Operation (4) Single-ended ended and differential LVDS waveforms generated when switching from high to low and back to high. 15

16 LVDS Principle of Operation (5) LVDS receivers can tolerate +/- 1V of common-mode mode voltage difference between the driver and receiver This is useful in situations where there might be up to 1V of difference between the drivers ground and receiver s s ground due to resistive voltage drops over long backplane or cable distances, or due to ground potential variations from one chassis to another 16

17 LVDS Configurations (1) Point-to to-point configuration. This provides the best signal quality due to the clear path. Bidirectional half-duplex configuration allows bidirectional communication over a single twisted pair. Data can flow in only one direction at a time. 17

18 LVDS Configurations (2) Multi-drop configuration connects multiple receivers to a driver. This configuration is useful in data distribution applications. In this configuration, stub lengths must be as short as possible, although acceptable stub lengths are always dependent upon the application. 18

19 LVDS Summary 19

20 LVDS Summary (continued) 20

21 High-Speed Transceiver Logic (HSTL) Stub-Series Terminated Logic (SSTL) 21

22 Introduction HSTL and SSTL families are used primarily for Memory chip interfaces Parallel data in/out interfaces for SerDes devices Single ended or differential interfaces that operate at frequencies above 200MHz HSTL accepts minimal input swing from 0.65V to 0.85V (nominally) with the output swing typically 0 to 1.5V 22

23 Single HSTL Circuit 23

24 HSTL I/O Levels Specification includes both dc and ac levels Devices switches state after crossing the ac threshold and does not switch back as long as the input stays beyond the dc threshold 24

25 HSTL Output Buffers 25

26 SSTL SSTL are particularly intended for single and Double Data Rate (DDR) SDRAMS and support frequencies above 333MHz Ideal for main memory applications with long transmission line stubs due to trace routing of Dual Inline Memory Modules (DIMMs( DIMMs) Long stubs are isolated from buses using an external stub resistor 26

27 SSTL DDR Memory System 27

28 Emitter Coupled Logic (ECL) 28

29 Introduction Emitter coupled refers to the fact that emitters of a driver stage constitute an output connecting to the next stage A differential amplifier provides high impedance inputs and voltage gain with the circuit Emitter follower output restores the logic levels and provides low output impedance for strong line driving and high fan-out Positive and negative supply voltages required for standard ECL 29

30 Applications and Uses Board-level applications: Clock and data distribution, backplane transmission, multiplexing, translation (voltage level shifting and interfacing to other logic families), state machines System applications: High-speed test equipment, optical networking equipment, ultra high-speed terabit routers, network attached storage devices, OC192 SONET, 10Gigabit Ethernet, enterprise computing servers, and high- performance workstations Differential uses: Clock distribution and interfacing Single-ended ended uses: Logic circuits 30

31 Basic Device Operation (1) ECL typical emitter follower output, termination and input structure 31

32 Circuit Operation Basic Device Operation (2) The driver s s output stages are emitter follower circuits. They provide level shifting from the differential amplifier to ECL output levels and provide a low output impedance for driving transmission lines The emitter follower output s s transistors operate in their active regions with dc current flowing at all times. This increases switching speeds and helps maintain fast turn-off times The ECL output impedance is low, typically on the order of 4-88 Ohm, which provides superior driving capability ECL input circuit is a current switching differential amplifier with high input impedance. In order to provide adequate input stage headroom, the common-mode mode voltage is around (Vcc 1.3V) 32

33 ECL Standards (1) Most ECL family devices adhere to one of two standards, the 10K standard or the 100K standard The terms 10K and 100K specify whether the devices adhere to the 10K or the 100K input and output dc electrical characteristics (i.e., the signaling levels) Five kinds of ECL family outputs 10K/ 100K dc signaling levels (~800mV) CML dc signaling levels (~800mV, but also 400mV) Reduced swing output levels (~400, but also 200, 600mV) Vendor-specific variable, adjustable, or selectable output levels (~0 to 800mV) Note: output voltage values listed in parentheses are peak-to to- peak differential signal voltages 33

34 10K is not temperature compensated ECL Standards (2) 100K is temperature compensated 34

35 ECL Interfaces Standard (a) single-ended ended ECL interconnect, (b) differential ECL interconnect, and (c) differential driver with independent single le- ended receivers A typical ECL circuit interface may be defined as a differential driver device sending two complementary signals over a pair of standard, controlled impedance lines to an ECL differential receiver device, as in (b). 35

36 Advantages and Disadvantages of Standard Interface Advantage of single-ended ended (SE) interconnects are decreased board routing and reduced system power demand Disadvantages of SE include higher jitter, phase error, and duty cycle skew, high noise sensitivity, critically narrow voltage margins, poor receiver sensitivity and higher EMI emission Differential interconnect advantages include high common- mode noise rejection, wide signal interface windows, high receiver sensitivity and low EMI emission Differential interconnect disadvantages include increased board routing and increased system power dissipation 36

37 Differential Interface (1) Differential signals are used in most ECL interfacing and clock distribution applications because of their low skew and high noise immunity The timing of 0-to0 to-1 1 or 1-to1 to-0 0 transition does not depend critically on device voltage thresholds which may change with temperature or between devices The differential definition of logical 0 and 1 provides an outstanding noise immunity, since noise created by power supply variations or coupled from external sources tends to be a common-mode mode signal 37

38 Differential Interface (2) A standard differential driver signal is characterized by a received signal swing Receiver sensitivity is specified by data sheets as the peak-to to-peak (Vpp( Vpp) input swing voltage Input swing greater than the allowed maximum may cause degraded frequency performance and increase the input propagation delay Input swings less than the specification minimum will cause diminished receiver output amplitude and possible errors 38

39 Differential Interface (3) Differential input high noise immunity is illustrated in the following lowing figure Each input signal to a differential receiver is characterized by a Vin high voltage (V IH ) level and a Vin low voltage (V IL ). Proper operation is achieved when the V IH level falls within spec limits, V IHCMR (voltage input high common-mode mode range) minimum to maximum 39

40 Curent Mode Logic (CML) 40

41 Introduction CML is ECL technologies that are being implemented in many of the newest high-speed devices CML serial signaling rates typically range from 1Gbps to over 10Gbps and higher and the data rate that CML can support depends upon the manufacturing process technology CML applications include: output/input stages of SERDES transceivers, point-to to-point configurations, SDH/SONET transmission equipment, high-speed backplane interconnects, high-speed serial links and others 41

42 CML Output Structure Consists of a common-emitter differential transistor pair with 50 Ohm collector resistors, which can supply source termination when driving 50 Ohm transmission lines The driver s s constant-current current sink sinks the same current regardless of the load placed upon the outputs or the values of pull-ups ups or termination resistors used (within limits) The constant current sink in CML structure creates less switching noise so output rise and fall times of less than 100ps are possible 42

43 CML Input Structure As shown in this figure, the CML input structure has a internal 50 Ohm input impedance for ease of termination Some devices do not have such internal termination resistors and allow external termination resistor to be used for greater flexibility 43

44 A CML Specification Example The table lists key specifications for a typical vendor s s implementation V TR and V CP specify the single-ended ended true and complement voltage of the driver output V OD is the driver s s differential output voltage magnitude V OS is the driver s s common-mode mode voltage R T is the termination resistor V ID(min) the receiver s s differential input threshold voltage Switching levels for a CML 800mV differential output example 44

45 AC/DC Coupled Coupled CML (1) AC - coupled CML circuit with two termination resistor pulled up to V T DC - coupled CML circuit with termination resistors pulled up to V CC 45

46 AC/DC Coupled Coupled CML (2) DC - coupled CML circuit with all resistors internal to the chips DC - coupled CML circuit with open-collector driver 46

47 AC/DC Coupled Coupled CML (3) CML output waveforms for AC and DC coupling (a) AC- coupled, loaded with internal 50 Ohm collector resistor and (b) DC-coupled, loaded with 25 Ohm equivalent, internal 50Ohm collector resistor in parallel with 50 Ohm termination resistor (a) (b) 47

48 Difference Between CML and ECL The main difference between ECL and CML is that ECL contains emitter follower circuits in the output stage and CML does not. It results in the dc voltage level (common-mode mode dc voltage) of the ECL outputs to be lower than the CML outputs by approximately one diode voltage drop plus another 100mV to 200mV 48

49 Emphasis and Equalization Transmission media generally have a low-pass frequency response, cause the distortion of signals at receive side A means of improving the signal quality is to transmit the high-frequency components with a larger amplitude than the low-frequency components One method by which higher frequencies are amplified more prior to transmission is called pre-emphasis/de emphasis/de- emphasis and sometimes, transmit equalization Amplification of the higher frequencies of a signal can also be done at the receiver to open up the eye of the received signal. The process is called equalization, or sometime as receive equalization 49

50 Pre-Emphasis/De Emphasis/De-Emphasis Driver output voltages plotted as single-ended ended and referenced to ground illustrating both pre-emphasis emphasis and de-emphasis emphasis 50

51 Adaptive Equalization Example Adaptive cable equalizer consists of CML input/output buffer 51