Using High-Speed Transceiver Blocks in Stratix GX Devices

Transcription

1 Using High-Speed Transceiver Blocks in Stratix GX Devices November 2002, ver. 1.0 Application Note 237 Introduction Applications involving backplane and chip-to-chip architectures have become increasingly complex and, therefore, operate at higher data rates. Because these complex applications utilize protocols that require increasing bandwidth, there is a need for devices to offer more flexibility while also satisfying multi-gigabit data rate requirements. Altera s Stratix TM GX family of devices meets both needs with its embedded transceivers. Stratix GX transceivers can receive and transmit at data rates up to gigabits per second (Gbps), and also have embedded circuitry to implement high-speed serial bus protocols. Stratix GX devices include 4 to 20 full-duplex transceiver channels, each incorporating clock data recovery (CDR) technology and embedded serializer/deserializer (SERDES) capability. The transceiver channels are grouped in integrated, four channel blocks and are designed for low power consumption and small die size. This application note discusses the following: Stratix GX transceiver I/O banks Transceiver clock distribution Transceiver internal test modes Applications & protocols supported with Stratix GX devices Related Links Stratix GX FPGA Family Data Sheet AN 202: Using High-Speed Differential I/O Interfaces in Stratix Devices Stratix GX Transceiver I/O Banks Stratix GX devices contain seven I/O banks. Figure 1 shows the Stratix GX transceiver blocks located in I/O bank five. Each transceiver block contains four, full-duplex transceiver channels. Stratix GX devices can have up to twenty full-duplex transceiver channels in five transceiver blocks. Table 1 lists the number of transceiver blocks per Stratix GX device. Altera Corporation 1 AN

2 Figure 1. Location of Stratix GX Transceiver Blocks I/O Bank 3 I/O Bank 4 I/O Banks 1 and 2 Support: Differential I/O Standards with DPA: - True LVDS - LVPECL V PCML - HyperTransport Technology Single-Ended I/O Standards: , 2.5-, 1.8-V LVTTL - GTL+ - CTT - SSTL-2 Class I and II - SSTL-3 Class I and II I/O Bank 2 I/O Bank 1 Regular I/O Blocks Support 3.3-, 2.5-, 1.8-V LVTTL 3.3-V PCI, PCI-X GTL GTL+ AGP CTT SSTL-18 Class I and II SSTL-2 Class I and II SSTL-3 Class I and II HSTL Class I and II I/O Bank 5 Contains Transceiver Blocks I/O Bank 5 Individual Power Bus I/O Bank 7 I/O Bank 6 Table 1 lists the number of transceiver blocks per Stratix GX device as well as the number of full-duplex transceiver channels. Table 1. Number of Transceiver Blocks per Stratix GX Device Device Number of Transceiver Blocks Full-Duplex Transceiver Channels EP1SGX10C 1 4 EP1SGX10D 2 8 EP1SGX25C 1 4 EP1SGX25D 2 8 EP1SGX25F 4 16 EP1SGX40D 2 8 EP1SGX40G 5 20 Each transceiver block contains four channels, a transmit PLL, four receive PLLs, and other associated control circuitry. Figure 2 shows the high-level structure of the Stratix GX transceiver block. 2 Altera Corporation

3 Figure 2. Stratix GX Transceiver Block PLD Logic Array Receiver Channel 0 Channel 0 Transmitter Channel 0 Receiver Pins Transmitter Pins PLD Logic Array Receiver Channel 1 Channel 1 Transmitter Channel 1 Receiver Pins Transmitter Pins PLD Logic Array and/or Global Clock PLD Logic Array XAUI Receiver State Machine XAUI Transmitter State Machine Channel Aligner State Machine Transmitter PLL Reference Clock Pins PLD Logic Array Receiver Channel 2 Channel 2 Transmitter Channel 2 Receiver Pins Transmitter Pins PLD Logic Array Receiver Channel 3 Channel 3 Transmitter Channel 3 Receiver Pins Transmitter Pins Altera Corporation 3

4 Each Stratix GX transceiver channel consists of a transmitter and receiver. The transmitter contains: Transmitter logic array interface 8B/10B encoder Transmitter PLL Serializer Output buffer The receiver contains: Input buffer Clock recovery unit (CRU) Deserializer detector and word aligner Rate matcher and channel aligner 8B/10B decoder Receiver logic array interface You can set all the Stratix GX transceiver functions through the Quartus II software. You can set programmable pre-emphasis, programmable equalizer, and programmable current driver dynamically as well. Each Stratix GX transceiver is also capable of Built-In Self Test (BIST) generation and verification as well as various loopback modes. Figure 3 shows the block diagram for the Stratix GX transceiver. Stratix GX transceivers provide physical coding sublayer (PCS) and physical media attachment (PMA) implementation for protocols such as 10 gigabit attachment unit interface (XAUI). The PCS portion of the transceiver consists of the logic array interface, 8B/10B encoder/decoder, pattern detector, word aligner, rate matcher, channel aligner, and the BIST and PRBS pattern generator/verifier. The PMA portion of the transceiver consists of the serializer/deserializer, the CRU, and the I/O buffers. 4 Altera Corporation

5 Figure 3. Stratix GX Transceiver Block Diagram Transmitter Receiver BIST Generator Reverse Parallel Loopback Demultiplexer (1-to-2) and Receiver FIFO BIST Verifier 8B/10B Decoder Multiplexer (2-to-1) and Transmitter FIFO Rate Matcher and Channel Aligner PRBS Generator 8B/10B Encoder Parallel Loopback Detector and Word Aligner PRBS Verifier Transmitter PLL Parallelto-Serial Serial-to- Parallel Clock Recovery Unit Receiver PLL Enable Serial Loopback Reverse Serial Loopback Reference Clock Altera Corporation 5

6 Transmitter Path The following describes the data path through the Stratix GX transceiver transmitter (see Figure 3). Data travels through the Stratix GX transceiver transmitter via the following modules: Transmitter logic array interface 8B/10B encoder Transmitter PLL Serializer (parallel to serial converter) Output buffer Transmitter Logic Array Interface The data path starts at the logic array via the transmitter logic array interface. The transmitter logic array interface includes the multiplexer and transmitter synchronization FIFO. The transmitter synchronization FIFO transfers the data from the logic array clock domain to the clock domain of the transmitter channel. The multiplexer takes a 16- or 20-bit data bus and converts it into a double-speed 10- or 8-bit data buses, respectively. If the data from the logic array is not 16-bit or 20-bit (double width mode), the multiplexer is bypassed. Figure 4 shows the operation of the multiplexer and transmitter synchronization FIFO. Figure 4. Transmitter Multiplexer & Synchronization FIFO Operation Transmitter Synchronization FIFO 8- or 10-bit data 8- or 10-bit data 8-, 10-, 16-, or 20-bit data Logic Array Clock 8-, 10-, 16-, or 20-bit data Transmit PLL Clock 2-to-1 Multiplexer 8- or 10-bit data The transmitter synchronization FIFO is four words deep with a maximum clock rate of 160 MHz. The write clock of the transmitter synchronization FIFO is the clock from the logic array, whereas the read clock is the reference clock from the transmitter PLL. The logic array clock must be a multiple of the fast clock generated by the transmitter PLL. 6 Altera Corporation

7 8B/10B Encoder The 8B/10B encoder translates an 8-bit parallel data stream into a 10-bit code for future serial transmission. Figure 5 shows the 8B/10B encoder and its associated signals. Figure 5. 8B/10B Encoder & Associated Signals Data [7..0] Force disparity Control 8B/10B Encoder Data [9..0] Besides the 8-bit data bus, the inputs to the 8B/10B encoder also include the force disparity signal (for the InfiniBand protocol) and the control signal. The force disparity signal generates the disparity of the 10-bit code by either starting the 8B/10B encoder with a positive disparity pattern (i.e., force disparity = high), or negative disparity pattern (i.e., force disparity = low). Positive disparity is defined as more 1 s than 0 s in the 10-bit generated code. This disparity signal forces the disparity of all channels to be the same during the first training sequence. One feature of the 8B/10B encoder is that it forces at least one transition for every five bits of data sent. This feature enables the receiving device to acquire and maintain lock. When high, the control signal input tells the encoder that the input word is a control character Kx.y and not data Dx.y (see Table 2). Table 2. 8B/10B Encoder Control Character Codes Control Characters K28.0, K28.1, K28.2, K28.3, K28.4, K28.5, K28.6, K28.7, K23.7, K27.7, K29.7, and K30.7 The 8B/10B encoder operates in two modes: XAUI mode and standard mode. When the 8B/10B encoder is in XAUI mode, the XAUI transmit state machine controls the data to the encoder. In XAUI mode, the XAUI state machine controls the 8B/10B encoder and all four transmitter channels operate together. In standard mode, each transmitter channel operates independently. The 8B/10B encoder can also be bypassed. Altera Corporation 7

8 Transmitter PLL Each transceiver block has one transmitter PLL, which receives the reference clock and generates the following signals: High-speed serial clock used by the serializer Slow-speed reference clock used by the receiver Slow-speed clock used by the logic array (divisible by 2) Figure 6 shows the transmitter PLL s inputs and outputs and Table 3 shows the transmitter PLL specifications. Figure 6. Transmitter PLL Input Sources Local transceiver block reference input pins Global clock Inter-transceiver block 1 (IQ1) clock Inter-transceiver block 2 (IQ2) clock 2 CLK input buffer to local interconnect to other transceiver blocks, bypassing the transmitter PLL High-speed serializer clock (0 and 180 phase) Low-speed parallel clock to receiver PLL, transmitter, and logic array Transmitter PLL Table 3 shows the transmitter PLL specifications. Table 3. Transmitter PLL Specifications Parameter Specification Input reference frequency range 62.5 MHz to 650 MHz Input reference duty cycle 60%/40% Input reference jitter 100 ps (peak-to-peak) Data rate support to Gbps Multiplication factor (W) (1), (2) 2, 4, 5, 8, 10, 16, or 20 Note to Table 3: (1) You can only use multipliers 2 and 5 when the transmitter PLL reference clock source is the local transceiver block reference input pins. (2) All transmitter channels in a transceiver block use the same multiplication factor. 8 Altera Corporation

9 The transmitter PLL supports an operation range from 622 Mbps to Gbps data rate with programmable PLL multiplication factor (W). Table 4 shows the reference clock and multiplier settings for common Stratix GX device protocols. Table 4. Reference Clock & Multiplier Settings for Applicable Standards CDR Applications Data Rate (Gbps) Frequency Multiplication (W) Reference Clock Frequency (MHz) Min Max Min Max 1G Ethernet InfiniBand Gigabit Ethernet XAUI RapidIO 1.25, 2.5, Fibre Channel to SFI-5, SPI to PCI Express SMPTE 292M Custom applications to , 5, 8, 10, 16, Serializer (Parallel to Serial Converter) The serializer converts parallel data from the 8B/10B encoder, or PLD logic array, to serial data. The serializer can support 8-, 10-, 16-, or 20-bit words when used with the transmitter multiplexer. The serializer drives the serial data to the output buffer (see Figure 7). The serializer can drive the serial bit-stream at a data rate range of 622 Mbps to Gbps. The serializer outputs the least significant bit (LSB) of the word first. Altera Corporation 9

10 Figure 7. Serializer Block Diagram Serializer D7 D7 D6 D6 D5 D5 Parallel data in (from 8B/10B encoder) 8 D4 D3 D4 D3 D2 D2 D1 D1 D0 D0 Serial data out (to output buffer) Low-speed parallel clock High-speed serial clock Figure 8 shows the serial bit order of the serializer output. Figure 8. Serializer Bit Order Parallel clock Serial clock Parallel data in (hex) Serial data out Output Buffer The Stratix GX transceiver buffers support 1.5-V pseudo current mode logic (PCML) up to Gbps. The buffer s signaling levels are compatible with low voltage positive emitter coupled logic (LVPECL), low voltage differential signaling (LVDS), and 3.3-V PCML signaling when AC coupled. The Stratix GX transceiver is capable of driving 40 inches of FR4 trace across two connectors. The internal termination, in the input and output buffers, supports AC and DC coupling with programmable differential termination settings of 100-, 120-, or 150-Ω. 10 Altera Corporation

11 The output buffer consists of: Programmable current driver Programmable pre-emphasis circuit Internal transmitter termination Figure 9 shows the block diagram of the output buffer. Figure 9. Transmitter Output Buffer Block Diagram Output Buffer Programmable Termination Serializer Programmable Current Driver Programmable Pre-Emphasis Circuit Output Pins Programmable Current Driver The programmable current driver controls the output differential voltage (V OD ) to handle different length, backplane, and receiver requirements. You can program the output buffer V OD to drive either short or long distances through connectors and cable. The programmable current driver brings the signal to the appropriate levels at the receiver by boosting the output signal levels to compensate for transmission line losses. Figure 10 shows how V OD can be programmed to any value between 400 and 1,600 mv by setting the current level. You can change the V OD setting with the Quartus II software or dynamically via a signal accessible within the FPGA logic array without reconfiguring the device. Altera Corporation 11

12 Figure 10. V OD Signal Levels Single-Ended Waveform V A ±V OD V B Differential Waveform +800 V OD (Differential) = V A V B +V OD V OD (Differential) V OD V Differential Table 5 shows the setting per current and impedance levels. Table 5. Programmable V OD (Differential) Current Level (ma) V OD (mv) 100 Ω 120 Ω 150 Ω , ,000 1,200 1, ,200 1, , ,600 Programmable Pre-Emphasis Module The programmable pre-emphasis module in each transmit buffer boosts the high-frequency components in the transmit data signal, which may be lost in the transmission media, while attenuating the lower-frequency components. This process maximizes the data eye opening at the far-end receiver. Pre-emphasis is particularly useful when driving data over a backplane, with low-quality coaxial cables, or over long distances. Figures 11 and 12 show conceptual eye diagrams of a Gbps signal at the transmitter and receiver with and without pre-emphasis. You can set pre-emphasis with the Quartus II software or dynamically via a signal accessible within the FPGA logic array without reconfiguring the device. 12 Altera Corporation

13 Figure 11. Eye Diagram of Transmitted Signal Without Pre-Emphasis After 40 Inches of FR4 Board Trace Transmitter without Pre-Emphasis Receiver without Pre-Emphasis Figure 12. Eye Diagram of Transmitted Signal With Pre-Emphasis After 40 Inches of FR4 Board Trace Transmitter with Pre-Emphasis Receiver with Pre-Emphasis Altera Corporation 13

14 Table 6 shows possible settings for the pre-emphasis level. Table 6. Programmable Pre-Emphasis V OD (Differential) Pre-Emphasis Level 5% 10% 15% 20% 25% Table 6 shows that the pre-emphasis levels can be set at 5%, 10%, 15%, 20%, and 25% of the programmed V OD setting. The maximum voltage level at the transmitter differential pins is 1,600 mv (differential). V OD (differential) is the voltage difference between V A and V B (see Figure 10). The current drive, the pre-emphasis setting, and the selected termination should be such that the resulting V OD is 1,600 mv or less. For example, a 16-mA current drive selection is only permitted with 100-Ω termination and disabled pre-emphasis. The maximum current setting for the 150-Ω termination resistor is 10 ma with only a 5% pre-emphasis level permitted. The following equation explains how these three factors are related. V OD (differential) 1600 mv = (pre-emphasis) (current drive) (termination) Example 1: 16 ma, 100 Ω, no pre-emphasis V OD (differential) = (1.00) (16) (100.0) = 1,600 mv 1,600 mv Example 2: 10 ma, 150 Ω, 5% pre-emphasis V OD (differential) = (1.05) (10) (150.0) = 1,575 mv 1,600 mv 14 Altera Corporation

15 Internal Transmitter Termination The output buffer also includes programmable on-chip termination circuitry of 100-, 120-, or 150-Ω differential termination for different protocols (i.e., 10 Gigabit Ethernet XAUI and InfiniBand using 100-Ω termination; Fibre Channel using 150-Ω termination). With on-chip termination, you do not need to add external components, which use board space. Plus, the termination resistors are located as close as possible on the pins, which reduces signal distortion and allows a cleaner signal by eliminating stubs from the device. A central calibration block controls the resistance and can calibrate the differential termination either only once after power-on or reset, or continuously. This option is set during configuration with the Altera Quartus II software. The on-chip termination only supports AC-coupled connections for 10 Gigabit Ethernet XAUI, Gigabit Ethernet, Fibre Channel, and RapidIO protocols (with the exception of InfiniBand, which requires both DC and AC coupling). If you use AC coupling, you need to provide an external capacitor. The resistance is accurate to within ±5% of temperature, voltage, and process changes. You can choose termination for different channels independently. The default setting for on-chip termination in the transmitter output buffer is 100 Ω differential. Figure 13 shows the internal transmitter termination inside the 1.5-V PCML output buffer. Figure 13. Internal Transmitter Termination V CM 50, 60, or 75 Ω 50, 60, or 75 Ω Receiver Path The following describes the data path through the Stratix GX transceiver receiver (see Figure 2). Data travels through the Stratix GX transceiver receiver via the following modules: Input buffer Receiver loopback buffer CRU Receiver PLL detector, word aligner, & data realigner Channel aligner & rate matcher 8B/10B decoder Receiver logic array interface Altera Corporation 15

16 Input Buffer The input buffer receives the differential serial data, terminates the data, adjusts the data for inter-symbol interference (ISI) reduction, and after detection the data is sent to the receiver s clock recovery unit (CRU). Figure 14 shows the structure of the input buffer. The input buffer contains: Internal receiver termination Equalizer module Signal detector Figure 14. Receiver Input Buffer Input Buffer Programmable Termination Input pins Programmable Equalizer Signal Detector To CRU Internal loopback from transmitter Loopback Buffer Internal Receiver Termination The input buffer includes programmable on-chip termination of 100-, 120-, or 150-Ω differential termination (see Figure 15). The internal receiver termination scheme behaves identically to the internal transmitter termination scheme. (See Internal Transmitter Termination on page 15 for more information on Stratix GX internal termination). 16 Altera Corporation

17 Figure 15. Internal Receiver Termination 50, 60, or 75 Ω V CM 50, 60, or 75 Ω Equalizer Module To negate the effect of high-frequency signal loss in the cable, the receiver s equalizer module boosts the signal gain at higher frequencies. Also, to extend the permissible length of a transmission medium, the receiver must compensate for protocol inter-symbol interference (ISI) that distorts the signal. Each receiver input buffer includes a programmable equalizer, which automatically compensates for ISI dielectric and skin effect losses. The equalizer allows the Stratix GX transceivers to operate at Gbps across various lengths of transmission media, and can boost signals by up to nine decibels (db). The programmable equalizer settings are based on the total trace length of FR4 of 0 inches (i.e., no equalization), 20 inches, and 40 inches. For example, if you know that the trace length to the Stratix GX transceiver receiver is 20 inches, you can set the equalizer to compensate for the signal losses so that the signal detector receives the data correctly. The equalizer is disabled when the transceiver is in a loopback mode. You can set the equalizer with the Quartus II software or dynamically via a signal accessible within the FPGA logic array without reconfiguring the device. Signal Detector Input data goes through the equalizer to the signal detector. The signal detector is a peak-detector based, differential-signal-level, hysteresis detector. The peak detector finds the signal based on the voltage level setting programmed by the designer. Altera Corporation 17

18 Each channel has a programmable, signal-loss-threshold-differential voltage level. Table 7 shows the four center selection levels and their required differential voltages for a high and low. The V MIN_ON is the minimum differential voltage that should arrive at the receiver for the signal detector output to go high. The V MAX-OFF is the maximum differential voltage below which the signal detector output will go low. Table 7 lists the minimum required times that the incoming signal should remain either above V MIN_ON or below V MAX_OFF for the signal detector to change its state in either direction. Table 7 also shows the detection/loss of signal (LOS) T MIN_OFF time for a typical differential input voltage of 1,200 mv. When the signal detector does not detect the signal, the receiver PLL is reset to the reference clock phase instead of the input data. For example, on one of the four settings the signal detector output is high when the differential levels are above 640 mv and low when the differential levels are below 590 mv. The example is from the 10 Gigabit Ethernet XAUI protocol setting with center voltage at 615 mv. You can specify the threshold settings through the Altera Quartus II software. Table 7. Receiver Signal Detector Specification Threshold Setting V min-on (mv) V max-off (mv) T min-on (ms) T min-off (ms) Receiver Loopback Buffer The loopback buffer allows you to loop the transmitter s differential serial output back to the receiver (i.e., serial loopback mode, see Channel Loopback Modes on page 34). In serial loopback mode, the buffer s inputs are at maximum levels, so equalization is not required. The receiver s input pins are also pulled low in serial loopback mode. 18 Altera Corporation

19 Clock Recovery Unit The CRU uses the reference clock and the serial data input at the receiver to generate a high-speed clock based on the transitions inside the data. The CRU feeds the high-speed clock to the serial side of the serializer/deserializer (SERDES). Next, the receiver uses the recovered clock throughout the remaining blocks of the receiver, and can feed it to the logic array for use in other logic. Figure 16 shows the CRU and the associated control block. The clock control block contains the run-length violation (RLV) detection circuit. Figure 16. CRU & Associated Control Block Diagram Input Buffer Loss of signal Input pins Reference clock from receiver PLL Clock Recovery Unit Retimed data to deserializer Recovered clock Data lock Loopback data Control Block freq_lock Run length violation Reset Loopback control The reference clock and data rate must be within 100 parts per million (ppm) in terms of its frequency content as per the overall system specification. When no data is incoming, the data/clock recovery circuit runs off of a reference clock source to keep the synchronizer voltage controlled oscillator (VCO) close to the optimum recovered clock rate while waiting for the real data. The CRU supports an operation range from 622 Mbps to Gbps data rate. Table 8 shows the CRU specifications. Table 8. CRU Specifications Parameter Minimum Maximum Serial input data rate 622 Mbps Gbps Run length tolerance 80 UI - Frequency offset tolerance 100 ppm +100 ppm Bit error rate Lock time (frequency) - 1 ms Lock time (data) ms Altera Corporation 19

20 Run Length Violation Detection Circuit The programmable run length violation (RLV) detection circuit monitors the transitions in the data used to generate the clock. The RLV detection circuit in the CDR block detects and reports when the data in the bit stream exceeds a preset maximum number of consecutive 1 s or 0 s. You can set the maximum level based on your protocol during configuration, and the RLV detection circuit will return an error signal if the data exceeds the maximum. The value of the RLV threshold ranges from 4 to 160 unchanging data bits, depending on the resolution (i.e., whether the input symbol width is set for 8-bit or 10-bit wide data). The default setting is 128 or 160, depending on the input symbol width setting. Receiver PLL Each receiver channel contains a receiver PLL, which takes an input reference and multiplies it up to the receiver input s data rate. All four receiver PLLs within a transceiver must use the same multiplier. The CRU uses the high-speed serial clock to generate a clock based on the input data stream s transitions. The input to the receiver PLL comes from one of the following sources: the transmitter PLL, the inter-transceiver block clock, global clocks, I/O bus or generic routing, or the local transceiver block reference input pins. Figure 17 shows the possible input sources and outputs for the receiver PLL. Figure 17. Receiver PLL Input Sources Local transceiver block reference input pins Global clocks, I/O bus, or generic routing Transmitter PLL output clock Inter-transceiver block 2 (IQ2) clock Receiver PLL High-speed serializer clock to CRU When the CRU asserts its frequency lock signal (i.e., FREQ_LOCK), the CRU is locked to data. The FREQ_LOCK is asserted when the following conditions occur: the signal detector of the receiver input buffer states a signal is detected (i.e., SIGDET=1), the receiver PLL VCO frequency and its reference clock (i.e, RXPLL_INPUT_REF) frequency are within 100 ppm (i.e., FREQ_LOCK=1), and the PLL is very close to absolute phase lock to the reference clock (i.e., PHASELOCK=1). 20 Altera Corporation

21 During initialization, the receiver PLL will normally lock to the external reference until SIGDET=1, FREQ_LOCK=1, and PHASELOCK=1, at which point the receiver PLL will switch to the incoming data (data mode). In data mode, the receiver PLL uses a phase detector to keep the recovered clock aligned properly with the data. If the PLL does not stay locked to data because of data problems (i.e., frequency drift or severe amplitude reduction), the receiver PLL will lock back to the reference clock if AUTOMATIC BACK TO REFERENCE is asserted and if either SIGDET=0 or FREQ_LOCK=0. Table 9 shows the specifications for the receiver PLL. Table 9. Receiver PLL Specifications Parameter Specifications Input reference frequency range 62.5 MHz to 650 MHz Input reference duty cycle 60%/40% Input reference jitter 100 ps (peak-to-peak) Data rate support 622 Mbps to Gbps Multiplication factor (W) 2, 4, 5, 8, 10, 16, or 20 Note to Table 9: (1) You can only use the 2, 4, or 5 multipliers if the output of the transmitter PLL is the receiver PLL reference clock source. Frequency Detector The frequency detector determines whether the incoming reference clock and data are within a prescribed ppm difference (i.e., to assert FREQ_LOCK). You can change the acceptable frequency difference threshold from the default of 1,000 ppm to any value between and 2,000 ppm, in 64 steps of ppm each. This feature allows users to set their own ppm level and lock to the reference clock either dynamically or with the Quartus II software. Altera Corporation 21

22 Lock-to-Reference Mode and Lock-to-Data Mode The receiver PLL acquires the proper frequency from a reference clock in lock-to-reference mode, which compares the phase and frequency. This may take up to 1 ms at the lowest data rate. Once the receiver PLL is phase and frequency locked to the reference clock, it switches to lock-to-data mode when SIGDET=1 (i.e., the input levels are valid). When the receiver PLL is in lock-to-data mode, it generates a clock that is phase locked to the data; thus, the receiver PLL sends out data that is optimally retimed with the extracted clock. The receiver PLL switches back to lock-to-reference mode if SIGDET=0 (i.e., the input levels are not valid), or if the frequency difference between the receiver PLL output and the data exceeds the allowed ppm difference. You can set the lock-to-data and lock-toreference mode either dynamically or with the Quartus II software. You can manually switch between reference mode and data mode. Deserializer (Serial to Parallel Converter) The deserializer converts incoming high-speed serial data to either 8- or 10-bit-wide parallel data synchronized to the CRU s recovered clock. The deserializer drives the parallel data to the pattern detector and word aligner module, (see Figure 18). The data rate of the deserializer output bus is the input data rate divided by the width of the output data bus. For example, for a 10-bit bus and a serial input data rate of 2.5 Gbps, the parallel data rate is 2,500/10, or 250 MHz. The first bit into the deserializer is the least significant bit (LSB) of the data bus out of the deserializer. 22 Altera Corporation

23 8 Figure 18. Deserializer Block Diagram Serial data in (from CRU) Deserializer D7 D6 D7 D6 D5 D5 D4 D3 D4 D3 Parallel data out (to word aligner) D2 D2 D1 D1 D0 D0 High-speed serial clock Low-speed parallel clock Figure 19 shows the serial bit order of the deserializer input. Figure 19. Deserializer Serial Bit Order Serial clock Parallel clock Serial data in Parallel data out (hex) Detector, Word Aligner & Data Realigner Because the parallel data from the deserializer may need to be realigned, the pattern detector, word aligner & data realigner modules line up the parallel data to the correct boundary by searching for the protocol s comma pattern. Figure 20 shows the receiver s pattern detector, word aligner, and data realigner input and output circuitry. Altera Corporation 23

24 Figure 20. Receiver Detector, Word Aligner & Data Realigner Data [9..0] Word Aligner Align success Align enable Data [9..0] Detector detect A1A2 or A1A1A2A2 detect Data Realigner Realign enable Detector After the data leaves the deserializer, it may enter the pattern detector. The pattern detector searches for a comma pattern across the entire incoming data that is word-aligned. The pattern detector checks for the pattern in every bit position. You can program the pattern detector to recognize one 7-bit pattern, one 10-bit pattern, two consecutive 8-bit characters (e.g., A1A2), or four consecutive 8-bit characters (e.g., A1A1A2A2). For 7-bit and 10-bit patterns, both the positive and negative disparities (i.e., true and complement) will be checked by the pattern detector. For the two consecutive 8-bit characters, only the positive disparity is checked. The pattern detect signal goes high every time the pattern is detected in the deserialized bit stream. Otherwise, the pattern detect signal goes low. The programmable pattern detector gives the receiver the flexibility to support various standards requiring different comma patterns. Table 10 shows preprogrammed comma patterns supported by Stratix GX transceivers. A custom pattern can be specified during device configuration with the Quartus II software. The pattern detector can be bypassed. 24 Altera Corporation

25 Table 10. Comma s Supported by the Detector s Types Bit Length Example Bit 8B/10B commas /K28.5/ or / K28.1/ or / K28.7 / 7 or 10 b XXX or b XXX A1, A2 detect A1 followed by A2 8 b followed by b A1A1, A2A2 detect A1, followed by A1, followed by A2, followed by A2 8 b followed by b followed by b followed by b Custom Any 16 Any Word Aligner The word aligner used with the pattern detector block aligns the incoming data to a word boundary by detecting and aligning a programmable synchronization pattern. Based on the location determined by the pattern detector block, the word aligner will align the outgoing data to the determined word boundary. This unique pattern of 1 s and 0 s either cannot occur as part of valid data or is a pattern that repeats at defined intervals. Data Realigner There are two data realigner modes, automatic and manual, and they determine the word boundary. Table 11 shows the data realignment modes. Table 11. Data Realignment Modes Data Realignment Mode Automatic data realignment Manual data realignment Effective Mode Gigabit Ethernet, or XAUI state machine controlled, or user-controlled Manual data realignment and manual synchronization Altera Corporation 25

26 Automatic data realignment uses the 10 Gigabit Ethernet XAUI or Gigabit Ethernet synchronizer state machine to do the following: Locate the pattern in the incoming data Determine the word boundary Change the word boundary The output of the data realigner is coordinated using a selection register that is controlled by either the XAUI or Gigabit Ethernet state machine. (State machine selection is done during configuration.) The selected state machine uses the pattern detect signal from the pattern detector and a known protocol to update the register that controls the data realignment. For protocols other than the 10 Gigabit Ethernet XAUI or Gigabit Ethernet, you can control whether or not to accept the state machine s word boundary, which is done with the ENCDT (i.e., pattern detect enable) signal. When ENCDT is high, the word boundary will be allowed to change. Conversely, when ENCDT is low, the word boundary does not change. In the user-controlled automatic mode, the SYNC_STATUS/RESYNC signal acts as a RESYNC signal. Whenever the pattern is detected in the incoming data stream and the internal state machine determines a word boundary that is different than the existing word boundary, the RESYNC signal will be asserted. The RESYNC signal is de-asserted when the word boundary is allowed to change to the boundary selected by the internal logic. In the state machine-controlled automatic mode the SYNC_STATUS/RESYNC signal acts as a SYNC_STATUS signal, signifying the conditions for word boundary selection have been satisfied. When the data realigner operates in manual mode, the selection register that coordinates the word aligner is updated using the logic array s realignment port. The realignment port causes the word boundary of the incoming data stream to slip by one bit. The manual realignment mode is supported for both the 8-bit and the 10-bit data path. Continual bit manual realignment may be done. For an eight-bit data path, for every eight cycles, data will be re-sent with the data slipped by a bit. Each time a bit slips, the bit which arrives at the receiver earlier is skipped. Internal logic will still search for the appropriate pattern in the incoming data stream, but the internal word logic will not change the word boundary to where it has found the pattern. However, you can change the boundary if necessary. 26 Altera Corporation

27 Channel Aligner and Rate Matcher The next stage the data enters after the pattern detector and word aligner is the channel aligner and rate matcher. Figure 21 shows the channel aligner and rate matcher and associated state machine blocks. Both the channel aligner and the rate matcher are bypassed for protocols other than 10 Gigabit Ethernet XAUI or Gigabit Ethernet. Figure 21. Channel Aligner & Rate Matcher Data [12..0] Recovered clock Channel Aligner Rate Matcher Data [12..0] Logic array clock Master clock (1) Deskew State Machine Gigabit Ethernet State Machine XAUI State Machine To other channels (2) To other channels (2) Notes to Figure 21: (1) This is the recovered clock from channel 0 or output from the receiver PLL. (2) When using the XAUI interface, the channel 0 state machine controls this output. Altera Corporation 27

28 Channel Aligner The channel aligner lines up all channels with a common clock, which is one of the channel s recovered clocks. The channel aligner consists of a channel alignment symbol detector and a 16-byte deep channel aligner FIFO buffer. The channel aligner is only active when the transceiver block is operating in XAUI mode. Each receiver channel has its own CDR block, and the data arrives at each receive pin at slightly different times. The channel aligner with its deskew FIFO makes sure that the data proceeds in each receiver out of the FIFO synchronized to the clock edge of the recovered clock of channel 0. The XAUI deskew state machine controls the channel aligner and operates in accordance with the Standards Document: IEEE Draft P802.3 ae /D3.2, Clauses 46, 47, 48, and 51. The mechanism is summarized as follows: Each channel searches the incoming data for the /A/ character In each channel, when /A/ is found, the deskew FIFO is enabled When /A/ is found in all channels, the XAUI deskew state machine enables the reading of data from the deskew FIFO The XAUI deskew state machine now monitors the reception of /A/ columns that are not aligned and responds as specified by the relevant 10 Gigabit Ethernet XAUI standard clause. Rate Matcher Stratix GX transceiver blocks use rate matchers to adjust for differences between the recovered clock and the PLL reference clock. If the reference clock is not frequency locked to the receiver s logic array clock, the rate matcher inserts, or removes, SKIP code groups (i.e., column of /R/) into, or from, the IDLE stream to match the particular protocol s rate. After channel alignment, the receiver performs rate matching. The rate matching circuit contains a 12-word deep FIFO buffer, which operates in either rate matching mode (i.e., through the Gigabit and XAUI state machine) or generic FIFO buffer mode. There is one state machine per transceiver block for 10 Gigabit Ethernet XAUI, and one state machine per transceiver channel for Gigabit Ethernet (GIGE). 28 Altera Corporation

29 The rate matcher is a Gigabit Ethernet-, or 10 Gigabit Ethernet XAUI-, specific block that controls reading and writing from the FIFO buffer, while the generic FIFO controls reading and writing with write-enable or read-enable signals specified from the logic array. The FIFO buffer modes are: rate matching XAUI, rate matching GIGE, and generic FIFO. In rate matching XAUI mode, the FIFO write clock (i.e., wrclk) is connected to the recovered clock of channel 0. The write-enable and read-enable signals (i.e., we and re) are controlled by the protocol, which inserts or deletes //R// (i.e., idle) groups into the data stream. Writing and reading is controlled by the number of //R// groups seen. The rate matcher in XAUI mode keeps track of the number of writes and reads to the FIFO with the FIFO counter register. The rate matcher in XAUI mode deletes /R/ from all the channels when the FIFO counter is above 9, and inserts /R/ to all the channels when the FIFO counter is below 4, which prevents FIFO overflow and underflow, respectively. In rate matching GIGE mode, the clock connections are the same as rate matching XAUI mode, but instead of inserting or deleting //R// groups, /I2/ ordered sets are inserted or deleted to control writing and reading of the FIFO. In the rate matching GIGE mode, FIFO overflow and underflow are handled in the same way as rate matching XAUI mode, except each channel performs its own rate matching. In generic FIFO mode, the designer controls the FIFO using re and we signals. 8B/10B Decoder After leaving the channel aligner and rate matcher, the receive data enters the 8B/10B decoder. The 8B/10B decoder translates a 10-bit parallel data stream into 8-bit data. Figure 22 shows the block diagram of the 8B/10B decoder. Data leaving the decoder is 10-bits wide, and contains the control bit and disparity error bit as well as the 8-bit decoded data. Figure 22. 8B/10B Decoder Block Diagram Data [7..0] Data [9..0] Disparity Error 8B/10B Decoder Error Detect K Code Data and control [9..0] Invalid code [1..0] Altera Corporation 29

30 The error detect signal is set when the detector detects an invalid code. The K code signal is set when the output data is a valid command byte (Kx.y) and not a data byte (Dx.y). The disparity error signal, which is synchronous to the data, is set when the decoder detects a running disparity error. The invalid code control signals are input back into the decoder after the initial data transmission. The designer can control which codes are invalid for a particular protocol. Table 12 shows the options for the invalid codes, which are specified during device configuration. Table 12. INVALID_CODE Setting Group Setting Invalid Codes 1 K28.1, K28.3, K28.4, K K28.6 The 8B/10B decoder can operate in two modes: XAUI mode or standard mode. In XAUI mode, all four channels operate together and the XAUI state machine controls the decoding process where various idle codegroups are mapped to a 10-Gigabit Medium Independent Interface (XGMII)-specific 8B/10B idle code, and error code-groups are specially handled depending on their occurring location. In standard mode, each receiver channel operates independently. The 8B/10B decoder can also be bypassed. Receiver Logic Array Interface Before the data goes to the Stratix GX logic array, it may need to go through the demultiplexer and receiver synchronization FIFO for phase alignment. To bring the data rate to a speed supported by the logic array, the phase alignment stage allows receiver data going to the logic array to be either single- or double-width. In single-width mode, the demultiplexer selects the 8-bit or 10-bit data bus from the 8B/10B decoder at the same rate as the decoder. In double-width mode, the byte deserializer expands the data to contain a 16- or 20-bit data bus width at half the rate from the 8B/10B decoder. 30 Altera Corporation

31 Because the synchronizer FIFO essentially sees only a bank of registers, it provides a simpler clock scheme boundary from which to transfer data (i.e., from the transceiver channels to the logic array). The FIFO s write clock comes from the logic array clock, a multiple of 1 or 2 of the recovered clock(s), low-speed parallel clock from transmitter PLL, or the recovered clock from channel 0 (i.e., in XAUI mode), whereas the FIFO s read clock comes from the logic array. Figure 23 shows the demultiplexer and synchronization FIFO. Figure 23. Receiver Demultiplexer & Synchronization FIFO 8- or 10-bit data 8 or or 20 8, 10, 16, or 20 Receiver Synchronization FIFO 8-, 10-, 16-, or 20-bit data Logic array clock Low-speed parallel clock from transmitter PLL Recovered clock from channel Recovered clock from channel 0 (XAUI mode) Master Clock Transceiver Clock Distribution All Stratix GX devices provide 16 dedicated global clock networks, 16 regional clock networks (i.e., four per device quadrant), and 8 dedicated fast regional clock networks. There are 12 dedicated clock pins (i.e., CLK[11..0]) to drive either global or regional clock networks. The recovered clocks (i.e., from the transceiver blocks) drive four additional clock networks (i.e., CLK[15..12]). However, the recovered clocks can either drive four regional clock networks or four global clock networks (i.e., only one recovered clock per transceiver block can drive the global or regional clock networks). Figure 24 shows the global and regional clock connections for the side pins and transceiver blocks. Altera Corporation 31

32 Figure 24. Global & Regional Clock Connections from Side Pins & Transceiver Blocks (EP1SGX40 Device) Notes (1), (2) RCLK1 RCLK0 RCLK2 RCLK3 G0 G1 G2 G3 G8 G9 G10 G11 RCLK11 RCLK10 RCLK8 RCLK9 FPLL7CLK CLK0 CLK1 CLK2 CLK3 FPLL8CLK PLL 7 PLL 1 PLL 2 PLL 8 l0 l1 g0 l0 l1 g0 l0 2 l1 g0 l0 l1 g0 Regional Clocks Global Clocks Regional Clocks 4 Transceiver Reference (3) Block Clock 4 Transceiver Reference (3) Block Clock 4 Transceiver Reference (3) Block Clock 4 Transceiver Reference (3) Block Clock 32 Altera Corporation

33 Notes to Figure 24: (1) PLLs 1,2 7, and 8 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs. PLLs 7 and 8 do not drive global clocks. (2) In EP1SGX40 devices that have five transceiver blocks, only four transceiver blocks can drive the global and local clock networks. (3) The high-speed serial data stream in each transceiver block generates the recovered clocks. Each transceiver block has four recovered clocks from the four transceiver channels. One of the four clocks drive the global and local clock networks. Figure 25 shows the clock routing throughout the Stratix GX transceiver channel. Figure 25. Stratix GX Transceiver Clock Routing Low-Speed Parallel Clock Transmitter Synchronization FIFO Multiplexer 8B/10B Encoder Serializer Transmitter logic array clock WR WR WR RD RD RD High-Speed Transmitter Serial Clock Transmitter PLL Receiver PLL and CRU Recovered clock Divide by 1 or 2 High-Speed Transmitter Serial Clock Receiver logic array clock Recovered Clock WR WR WR WR WR RD RD RD RD RD Receiver Synchronization FIFO Demultiplexer 8B/10B Decoder Rate Matcher Channel Aligner Word Aligner Recovered clock from channel 0 Deserializer f See the Stratix GX FPGA Family Data Sheet for more information on transceiver clocks. Altera Corporation 33

34 Transceiver Internal Test Modes The Stratix GX transceiver has many internal test modes for verifying functionality within the device. Each receiver/transmitter channel pair has a BIST generator and verifier as well as a PRBS generator and verifier. The BIST generator can produce regular PRBS data of 2 8 or 2 10 patterns, or or unique bit combinations. The PRBS generator can produce regular PRBS data of 2 8 patterns, or unique bit combinations. Along with these internal generators and verifiers, the transceiver also has the capability to test the Stratix GX device through various loopback modes. By combining PRBS, BIST, and loopback operation, the transceiver can perform these self-tests at full-speed and between two devices. This section describes the following Stratix GX transceiver operation modes: Channel loopback BIST generator & verifier PRBS generator & verifier Channel Loopback Modes One method of testing the Stratix GX transceiver is using its channel loopback modes. Loopback is defined where data from the transmitter section is routed directly to the receiver section. Reverse loopback is defined where data from the receiver section is routed directly to the transmitter. The data can either be serial or parallel. There are three different channel loopback modes: Serial loopback Reverse serial loopback Parallel loopback Reverse parallel loopback Serial Loopback In serial loopback mode, which is controlled via the logic array, the output of the transmitter s serializer loops back to the input of the receiver s deserializer. While in the serial loopback mode, the transmitter s output buffer still transmits data coming from the serializer with 80% of the selected V OD setting. To deactivate the input buffer, internal pull-down circuitry used only for serial loopback mode is activated on the input buffer s pin pair. 34 Altera Corporation

35 Reverse Serial Loopback In reverse serial loopback mode, the retimed data from the CRU loops back to the transmitter s output buffer. Parallel Loopback In parallel loopback mode, the data from the transmitter synchronizer FIFO is looped back to the pattern detector and word aligner. The parallel loopback mode can be either 10-bit parallel loopback, which comes from the 8B/10B encoder, or 8-bit parallel loopback, which bypasses the 8B/10B encoder. Reverse Parallel Loopback In reverse parallel loopback mode, the data from the receiver demultiplexer loops back to the transmitter synchronizer FIFO. 1 All loopback mode settings, with the exception of serial loopback mode, are established at device configuration and can be selected within the Quartus II software. Serial loopback mode is controlled through the logic array and can be changed dynamically. Loopback operations are only allowed when the transmitter and receiver are placed on adjacent channels. BIST Generator & Verifier The BIST generator creates multiple data patterns, which can be verified by the BIST verifier. If the incoming data does not match the locally generated data in the verifier, the test fails. In BIST test mode 0, the BIST generator can produce a PRBS pattern in the transmitter with a corresponding PRBS pattern in the verifier at the receiver. Both generator and verifier can work with 10- or 8-bit data patterns. (However, in the latter case, the generator will fill the upper two bits with 1 s). If operating in 10-bit mode, or patterns in 8-bit mode, the pattern generator produces unique bit combinations in the PRBS bit stream. This feature is very useful for testing both transmitter and receiver performance. Table 13 summarizes the BIST and its corresponding pattern test modes. If BIST is enabled (BISTEN=1), the modes in Table 13 will be the modes of the BIST generator. Altera Corporation 35

36 Table 13. BIST Generator Test Modes BIST Test Mode The BIST operates in three channel loopback modes: BIST 8B parallel loopback BIST parallel loopback BIST serial loopback Generated 0 PRBS repetitive patterns with 8B/10B bypass 1 00-FF incremental pattern includes K28.5 /S/ and /T/ 2 High Frequency (D21.5) 3 Low Frequency (K28.7) 4 Mixed Frequency BIST 8B Parallel Loopback Mode The BIST 8B parallel loopback path (see Figure 26) runs through the transmitter synchronization FIFO, the multiplexer (optional), the demultiplexer (optional), and the receiver synchronization FIFO. 36 Altera Corporation