The ST7588T is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 132 segment and 80

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1 ST Sitronix ST7588T 81 x 132 Dot Matrix LCD Controller/Driver INTRODUCTION The ST7588T is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 132 segment and 80 common+1icon driver circuits. This chip is connected directly to a microprocessor, accepts 3-line serial peripheral interface (SPI), 4-line serial peripheral interface (SPI), I 2 C interface or 8-bit parallel interface, display data can stores in an on-chip display data RAM of 81 x 132 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components. FEATURES Single-chip LCD controller & driver Driver Output Circuits 132 segment outputs / 81 common outputs On-chip Display Data ram Capacity: 81X132=10,692 bits Microprocessor Interface 8-bit parallel bi-directional interface with 6800-series or 8080-series 4-line A mode SPI (write only) 4-line B mode SPI (write only) 3-line 8 bit A mode SPI (write only) 3-line 8 bit B mode SPI (write only) 3 line 9 bit SPI (write only) I 2 C (Inter-Integrated Circuit) Interface (write only) On-chip Low Power Analog Circuit Generation of LCD supply voltage (externally V OUT voltage supply is possible) Generation of intermediate LCD bias voltages Oscillator requires no external components (external clock also possible) Voltage converter (x2, x3, x4, x5, x6) Voltage regulator (temperature gradient -0.1%/ C) Voltage follower On-chip electronic contrast control (128 steps) External RESB (reset) pin Logic supply voltage range: V DD1: 1.8V to 3.3V V DD2: 2.4V to 3.3V Temperature range: -30 to +85 C ST7588T 6800, 8080, 4-Line, 3-Line interface (without I 2 C interface) ST7588Ti I 2 C interface Ver 1.2 1/ /12/22

2 PAD ARRANGEMENT (COG) Chip Size: 7,708 μm 980 μm Bump Pitch: PAD NO 1~185, 248~276: 45μm (COM/SEG) PAD NO 186~187, 188~189, 191~192, 193~194, 195~196, 197~198, 199~200, 201~202, 213~214,215~216: 119μm PAD NO 187~188, 189~190, 192~193, 194~195, 196~197, 198~199, 200~201, 209~211, 212~213, 214~215, 216~217, 218~220: 73μm PAD NO 190~191: 134μm; PAD NO 202~203: 77μm; PAD NO 204~205, 206~207: 75μm PAD NO 203~204, 205~206: 175μm; PAD NO 207~208: 150μm; PAD NO 211~212, 217~218: 102μm PAD NO 220~221: 93μm; PAD NO 208~209: 68μm; PAD NO 221~243, 244~247: 70μm PAD NO 243~244: 145μm Bump Size: PAD NO 1~156, 174~185, 248~259: 30(x) μm 80(y) μm PAD NO 157~173, 260~276: 80(x) μm 30(y) μm PAD NO 186~202, 209~247: 55(x) μm 60(y) μm PAD NO 203~208: 45(x) μm 60(y) μm Bump Height: 17 μm Chip Thickness: 480 μm Ver 1.2 2/ /12/22

3 PAD CENTER COORDINATES (49 duty) Pad No. Pin Name X Y 001 none none none none none none none none none none none none SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123] SEG[122] SEG[121] SEG[120] SEG[119] SEG[118] SEG[117] SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109] Pad No. Pin Name X Y 036 SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] Ver 1.2 3/ /12/22

4 Pad No. Pin Name X Y 071 SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] Pad No. Pin Name X Y 107 SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] Ver 1.2 4/ /12/22

5 Pad No. Pin Name X Y 143 SEG[1] SEG[0] COMS COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] none none none none none none none none none Pad No. Pin Name X Y 179 none none none none none none none SYNC CL DOF CSB VSS RESB A /WR(R/W) /RD(E) D D D D D D D D T T T T T T VSS VSS VSS MS MODE MODE Ver 1.2 5/ /12/22

6 Pad No. Pin Name X Y 215 PS PS PS V DD V DD V DD V DD V DD V OUT V OUT V OUT CAP3N CAP3N CAP3P CAP3P CAP5P CAP5P CAP1N CAP1N CAP1P CAP1P CAP2P CAP2P CAP2N CAP2N CAP4P CAP4P VRS V V V Pad No. Pin Name X Y 246 V V COMS COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] COM[35] COM[34] COM[33] COM[32] COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] COM[25] COM[24] none none none none Ver 1.2 6/ /12/22

7 PAD CENTER COORDINATES (65 duty) Pad No. Pin Name X Y 001 COM[35] COM[34] COM[33] COM[32] none none none none none none none none SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123] SEG[122] SEG[121] SEG[120] SEG[119] SEG[118] SEG[117] SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109] Pad No. Pin Name X Y 036 SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] Ver 1.2 7/ /12/22

8 Pad No. Pin Name X Y 071 SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] Pad No. Pin Name X Y 107 SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] Ver 1.2 8/ /12/22

9 Pad No. Pin Name X Y 143 SEG[1] SEG[0] COMS COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] none Pad No. Pin Name X Y 179 none none none none none none none SYNC CL DOF CSB VSS RESB A /WR(R/W) /RD(E) D D D D D D D D T T T T T T VSS VSS VSS MS MODE MODE Ver 1.2 9/ /12/22

10 Pad No. Pin Name X Y 215 PS PS PS V DD V DD V DD V DD V DD V OUT V OUT V OUT CAP3N CAP3N CAP3P CAP3P CAP5P CAP5P CAP1N CAP1N CAP1P CAP1P CAP2P CAP2P CAP2N CAP2N CAP4P CAP4P VRS V V V Pad No. Pin Name X Y 246 V V COMS COM[63] COM[62] COM[61] COM[60] COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] Ver / /12/22

11 PAD CENTER COORDINATES (81 duty) Pad No. Pin Name X Y 001 COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123] SEG[122] SEG[121] SEG[120] SEG[119] SEG[118] SEG[117] SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109] Pad No. Pin Name X Y 036 SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] Ver / /12/22

12 Pad No. Pin Name X Y 071 SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] Pad No. Pin Name X Y 107 SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] Ver / /12/22

13 Pad No. Pin Name X Y 143 SEG[1] SEG[0] COMS COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] COM[32] Pad No. Pin Name X Y 179 COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] COM[39] SYNC CL DOF CSB VSS RESB A /WR(R/W) /RD(E) D D D D D D D D T T T T T T VSS VSS VSS MS MODE MODE Ver / /12/22

14 Pad No. Pin Name X Y 215 PS PS PS V DD V DD V DD V DD V DD V OUT V OUT V OUT CAP3N CAP3N CAP3P CAP3P CAP5P CAP5P CAP1N CAP1N CAP1P CAP1P CAP2P CAP2P CAP2N CAP2N CAP4P Pad No. Pin Name X Y 251 COM[77] COM[76] COM[75] COM[74] COM[73] COM[72] COM[71] COM[70] COM[69] COM[68] COM[67] COM[66] COM[65] COM[64] COM[63] COM[62] COM[61] COM[60] COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] CAP4P VRS V V V V V COMS COM[79] COM[78] Ver / /12/22

15 BLOCK DIAGRAM DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 WR(R/W) /RD(E) A0 /RES CSB Figure 1 Block diagram Ver / /12/22

16 PIN DESCRIPTIONS LCD driver outputs Pin Name I/O Description No. of Pins LCD segment driver outputs This display data and the M signal control the output voltage of segment driver. SEG0 to SEG131 O Display data M (Internal) Segment driver output voltage Normal display Reverse display H H V0 V2 H L V SS V3 132 L H V2 V0 L L V3 V SS Power save mode V SS V SS LCD column driver outputs This internal scanning data and M signal control the output voltage of common driver. COM0 to COM79 O Display data M(Internal) Common driver output voltage Normal display Reverse display H H V SS H L V0 80 L H V1 L L V4 Power save mode V SS COMS O Common output for the icons. The output signals of these pins are same. If not using, they should be left open. 2 MICROPROCESSOR INTERFACE Pin Name I/O Description No. of Pins Microprocessor interface select input pin PS2 PS1 PS0 State bit 8080 parallel interface bit 6800 parallel interface PS[2:0] I line serial interface A mode line serial interface B mode line (8 bit) serial interface A mode line (8-bit) serial interface B mode line (9-bit) serial interface I 2 C serial interface CSB I Chip select input pins Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB0 to DB7 is high impedance. There is no CSB pin in I 2 C interface, so this pin can fix to H 1 RESB I Reset input pin When RESB is L, initialization is executed. 1 A0 I It determines whether the data bits are data or a command. A0= H : Indicates that D0 to D7 are display data. A0= L : Indicates that D0 to D7 are control data. There is no A0 pin in three line or I 2 C interface, so this pin can fix to H 1 Ver / /12/22

17 Pin Name I/O Description No. of Pins Read/Write execution control pin : PS2 MPU type /WR(R/W) Description /WR(R/W) I H 6800-series R/W Read/Write control input pin R/W= H : read R/W= L : write 1 L 8080-series /WR Write enable clock input pin The data on D0 to D7 are latched at the rising edge of the /WR signal When in the serial interface must fix to H Read/Write execution control pin : PS2 MPU Type /RD (E) Description /RD (E) I H 6800-series E Read/Write control input pin R/W= H : When E is H, D0 to D7 are in an output status. R/W= L : The data on D0 to D7 are latched at the falling edge of the E signal. 1 L 8080-series /RD Read enable clock input pin When /RD is L, D0 to D7 are in an output status. When in the serial interface must fix to H D7 to D4 D1 to D3 (SDA) D0 (SCL) When the parallel interface selected: 8-bit interface This is an 8-bit bi-directional data bus that connected to the standard 8-bit microprocessor data bus. When chip select is not active, D0 to D7 is high impedance. When the serial interface selected: 3 or 4-line D0: serial input clock (SCL) D1 to D3: serial input data (SDA) D4, D5, D6, D7 : must fix to H When chip select is not active, D0 to D7 is high impedance. D7 to D6 (SA) D2 to D5 (SDA_OUT) D1 (SDA_IN) D0 (SCL) I/O When the serial interface selected (PS2~0="H" ): I 2 C D0: SCL, serial clock input. D1: SDA_IN, serial input data. D2 to D5: SDA_OUT, serial data acknowledge for the I 2 C interface. By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully I 2 C interface compatible. Having the acknowledge output separated from the serial data line is advantageous in chip on glass (COG) applications. In COG applications, a potential voltage divider on SDA track is formed by the I 2 C pull-up resistor and the ITO track resistance (due to the track resistance from the SDA_OUT pad to the system). It is possible that during the acknowledge cycle the IC will not be able to create a valid logic 0 level because of the ITO track resistance. By splitting the SDA_IN input from the SDA_OUT output, the device could be operated in the mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDA_OUT pad to the system SDA line to guarantee a valid low level. D6 and D7 are slave address bit 0 and 1 which can be set as 00 to 11. D1 to D5 must be connected together (SDA) Chip select input pin CSB is not used and must be fixed to H 8 Ver / /12/22

18 Pin Name I/O Description No. of Pins Use this pin can select 49 duty, 65duty or 81 duty mode Mode1 Mode0 Duty MODE0, MODE1 I duty duty duty MS I This pin selects the Master/Slave operation mode. The Master will output the synchronous timing signals that are required for LCD display, while the Slave uses the synchronized timing signals from Master for LCD display. MS= H : Master operation mode; MS= L : Slave operation mode. 1 SYNC O This is the liquid crystal alternating current signal terminal. 1 /DOF O This is the LCD blanking control terminal. 1 CL Power Supply Pins I/O This is the display clock output terminal and must be floating. MS H L CL Output Input This pin must be floating if not used. Pin Name I/O Description No. of Pins V SS Power Ground. 9 V DD1 V DD2 V OUT V0, V1, V2, V3, V4 Test Pin Power Power Power Power Digital Supply Voltage. The 2 supply rails V DD1 and V DD2 could be connected together. If Digital Option pin is high, must be this level. Analog Supply Voltage. The 2 supply rails V DD1 and V DD2 could be connected together. If using external voltage generator, the external supply voltage should connect to V OUT pad as an external voltage input. V OUT must series one capacitor to V DD2. This is a multi-level power supply for the liquid crystal operation. V OUT V0 V1 V2 V3 V4 V SS VRS Power Monitor Voltage Regulator reference level, must be left open. 1 Pin Name I/O Description No. of Pins T0~T5 Test These pins are reserved for test only ITO Limitations PIN Name ITO Resistance SYNC, /DOF, PS0~2, M0, M1, MS No Limitation T0~5 Floating V DD1, V DD2, V SS, VRS, V OUT <100Ω D1~D5 (if operated as I 2 C mode) <300Ω CSB, CL, E, R/W, A0, D0~D7 <1KΩ V0, V1, V2, V3, V4, CAP1P, CAP1N, CAP2P, CAP2N, CAP3P, CAP3N, CAP4P, CAP5P <100Ω RESB <10KΩ Ver / /12/22

19 FUNCTIONAL DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input There is CSB pin for chip selection. The ST7588T can interface with an MPU when CSB is "L". When these pins are set to any other combination, A0, /RD (E), and /WR(R/W) inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Selection Interface ST7588T has eight types of interface with an MPU, which are six serial and two parallel interfaces. This parallel or serial interface is determined by PS0, PS1 and PS2 pin as shown in Table 1. Table 1 Parallel / Serial Interface Mode Type PS2 PS1 PS0 Interface mode Parallel Serial bit 8080-series MPU mode bit 6800-series MPU mode line serial interface A mode line serial interface B mode line (8 bit) serial interface A mode line (8-bit) serial interface B mode line (9-bit) serial interface I 2 C serial interface Parallel Interface The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS0 as shown in Table 2. The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in Table 3. Table 2 Microprocessor Selection for Parallel Interface PS2 CSB A0 E_RD RW_WR DB0 to DB7 MPU bus H CSB A0 E RW DB0 to DB series L CSB A0 /RD /WR DB0 to DB series Table 3 Parallel Data Transfer Common 6800-series 8080-series A0 E_RD (E) RW_WR (RW) E_RD (/RD) RW_WR (/WR) Description H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction) NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, the interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, RW_WR as in case of 6800-series mode. Ver / /12/22

20 Serial Interface 4-Line SPI When the ST7588T is active (CSB= L ), serial data (DB1~3) and serial clock (DB0) inputs are enabled. While not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either by software or the Register Select (A0) Pin. When the A0 pin is used, data is display data when A0 is high and is command data when A0 is low. When A0 is not used, the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data Direction command ( ) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are sent, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data. (1) 4-Line SPI A Mode (PS0 = "L", PS1 = "H", PS2 = "L") CSB SDA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 SCL A0 Figure 2 4-Line SPI Timing (2) 4-Line SPI B Mode (PS0 = "L", PS1 = "H", PS2 = "H") CSB SDA DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 SCL A0 Figure 3 4Lline SPI Timing Ver / /12/22

21 3-Line SPI (1) 3-Line SPI (8 bit) To write data to the DDRAM, set address and No. of Data Bytes before transferring data, then data will be latched at the rising edge of SCL. The DDRAM column address pointer will be increased by one automatically. 1. Set Page Address: Y3 Y2 Y1 Y0 Set Column Address (H): X7 X6 X5 X4 Set Column Address (L): X3 X2 X1 X0 2. Set No. of Data Bytes (H): DA10 DA9 DA8 Set No. of Data Bytes (M): DA7 DA6 DA5 DA4 Set No. of Data Bytes (L) & Start DA3 DA2 DA1 DA0 3. Transfer Data bytes. Figure 4 3-pin SPI (8 bit) A mode Timing (A0 is not used) 1. Set Page Address: Y0 Y1 Y2 Y Set Column Address (H): X4 X5 X6 X Set Column Address (L): X0 X1 X2 X Set No. of Data Bytes (H): DA8 DA9 DA Set No. of Data Bytes (M): DA4 DA5 DA6 DA Set No. of Data Bytes (L) & Start DA0 DA1 DA2 DA Transfer Data bytes. Figure 5 3-pin SPI (8 bit) B mode Timing (A0 is not used) Ver / /12/22

22 This command is used in 3-Line SPI mode only. It will be 3 continuous commands; they contain the data length and inform the LCD driver the following bytes will be display data. After sending out these 3 commands, the following messages will be display data. If data is halted during transmitting, it is not valid data. New data will be transferred serially with most significant bit first. NOTE: In spite of transmission of data, if CSB is disabled, state stops abnormally. Next state is initialized. (2) 3-Line SPI (9 bit) In 3-Line mode, default message from MCU is command, the 2 bytes command of Set Data Direction & Display Data Length must be set before display data send from MCU, after the display data is sent over, the next message is turned to be command. CSB SDA A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0 SCL Figure 6 3-line SPI Timing I 2 C Interface The I 2 C interface receives and executes the commands sent via the I 2 C Interface. It also receives RAM data and sends it to the RAM. The I 2 C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. (1) BIT TRANSFER One data bit is transferred during each clock pulse. Data on the SDA line must remain stable during the HIGH period of the clock pulse, because data changes at this moment will be regarded as a control signal. Bit transfer is illustrated in Figure 8. (2) START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 9. (3) SYSTEM CONFIGURATION The system configuration is illustrated in Figure 10. Transmitter: the device that sends the data to the bus. Receiver: the device that receives the data from the bus. Master: the device that initiates transmission, generates clock signals, and terminates a transfer. Slave: the device addressed by a master. Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message. Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted. Synchronization: procedure to synchronize the clock signals of two or more devices. (4) ACKNOWLEDGE Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is Ver / /12/22

23 addressed must generate an acknowledgement after the reception of each byte. A master receiver must also generate an acknowledgement after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledgement related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledgement on the last byte that has been clocked out of the slave. In this situation, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I 2 C Interface is illustrated in Figure 7. Figure 7 Acknowledgement on the I 2 C Interface Figure 8 Bit transfer Figure 9 Definition of START and STOP conditions MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER (1) SLAVE RECEIVER (2) SLAVE RECEIVER (3) SLAVE RECEIVER (4) SDA SCL Figure 10 System configuration Ver / /12/22

24 (5) I 2 C Interface protocol The ST7588T supports command, data write addressed slaves on the bus. Before any data is transmitted on the I 2 C Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses ( , , , and ) are reserved for the ST7588T. The least significant bit of the slave address is set by connecting the input SA0 and SA1 to either logic 0 (V SS) or logic 1 (V DD1). The I2C Interface protocol is illustrated in Figure 11. The sequence is initiated with a START condition (S) from the I 2 C Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I 2 C Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is regarded as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended ST7588T device. If the A0 bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I 2 C INTERFACE-bus master issues a STOP condition (P).If the R/W bit is set to logic 1 the chip will output data immediately after the slave address if the A0 bit, which was sent during the last write access, is set to logic 0. If the master generates no acknowledgement after a byte, the driver stops transferring data to the master. Write mode acknowledgement from ST7588 acknowledgement from ST7588 acknowledgement from ST7588 acknowledgement from ST7588 acknowledgement from ST7588 S S A 1 slave address S A 0 0 A 1 A control byte 0 A data byte R/W Co 2n>=0bytes command word A 0 A control byte 0 A data byte A P Co 1 byte n>=0bytes MSB...LSB S A 1 S A 0 slave address R / W C o A control byte A Co Figure 11 2-line Interface protocol Last control byte to be sent. Only a stream of data bytes is allowed to follow. 0 This stream may only be terminated by STOP or RE-START condition. 1 Another control byte will follow the data byte unless a STOP or RE-START condition is received. Ver / /12/22

25 Data Transfer The ST7588T uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 12. Moreover, when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure 13. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. MPU signal A0 /WR D0 to D7 N D(N) D(N+1) D(N+2) D(N+3) Internal signals /WR BUS HOLDER COLUMN ADDRESS N D(N) D(N+1) D(N+2) D(N+3) N N+1 N+2 N+3 Figure 12 Write Timing Figure 13 Read Timing Ver / /12/22

26 DISPLAY DATA RAM (DDRAM) The ST7588T contains an 81X132 bit static RAM that stores the display data. The display data RAM store the dot data for the LCD. It has an 81(10 pagex8 bit +1 pagex1 bit) X 132. There is a direct correspondence between X-address and column output number. It is 81-row by 132-column addressable array. Each pixel can be selected when the page and column addresses are specified. Page Address Circuit This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the Set Page instruction. Page Address 11 is a special RAM area for the icons and display data D0 is only valid. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 132-bit RAM data to the display data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the MPU cannot access Line Address of icons. Column Address Circuit Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in Figure 14. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Register MX and MY selection instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing MX select instruction. Refer to the following Figure 15. SEG Output MX SEG0 Segment Pads SEG131 0 Seg0 Segment Address Seg131 1 Seg131 Segment Address Seg0 COM Output MY COM0 Common Pads COM79 0 Com0 Common Address Com79 1 Com79 Common Address Com0 Data is downloaded in bytes into the RAM matrix of ST7588T as indicated in Figs.14, 15, 16. The display RAM has a matrix of 81 by 132 bits. The address pointer addresses the columns. The address range is: X=0~131 ( ); Y=0~10 (1010). Addresses out of this range are not allowed. In horizontal addressing mode, the X address increments after each access (see Figure 16). After reaching the last X address (X = 131), X address wraps around to 0 and Y address increases to address the next row. After the very last address (X = 131, Y = 10) the address pointers wrap around to address (X = 0, Y =0) Ver / /12/22

27 Data structure LSB D0 D7 MSB LSB MSB 1 bit X-address Y-address Figure 14 RAM format and addressing, if DO=0 LSB D7 D0 MSB LSB MSB 1 bit X-address Y-address Figure 15 RAM format and addressing, if DO= X-address Y-address Figure 16 Sequence of writing data bytes into RAM with horizontal addressing Ver / /12/22

28 LCD DRIVER CIRCUIT This driver circuit is configured by 81-channel common drivers and 132-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M (Frame Indicator) signal. COM0 M V DD V SS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM0 COM1 V0 V1 V2 V3 V4 V SS V0 V1 V2 V3 V4 V SS COM8 COM9 COM10 COM2 V0 V1 V2 V3 V4 V SS COM11 COM12 COM13 COM14 COM15 SEG SEG0 SEG1 V0 V1 V2 V3 V4 V SS V0 V1 V2 V3 V4 V SS COM0 to SEG0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 COM0 to SEG1 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 Figure 17 LCD Driver output waveform Ver / /12/22

29 REFERENCE BOOSTER CIRCUIT EXAMPLE Figure 18 Booster Configuration Notes: 1. C1 = 1uF ~ 4.7uF. Please take care about the Voltage Rating of the capacitor. 2. V OUT should not exceed the Absolutely Maximum Rating. Ver / /12/22

30 RESET CIRCUIT Setting RESB to L or Reset instruction can initialize internal function. When RESB becomes L, the following procedure is entered. Page address: 0 Column address: 0 Display control: Display blank COM Scan Direction MY: 0 SEG Select Direction MX: 0 DO=0 Oscillator: OFF N-line inversion register: 0 (disable) Power down mode (PD = 1) Normal instruction set (H[1:0] = 00) Display blank (E = D = 0) Address counter X [7:0] = 0, Y [3:0] = 0 Bias system (BS [2:0] = 010) V0 is equal to 0; the HV generator is switched off (V OP [6:0] = 0) After power-on, RAM data are undefined While RESB is L or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB0. After DB0 becoming L, any instruction can be accepted. RESB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESB is essential before used. Ver / /12/22

31 Partial Display on LCD The ST7588T realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. Moreover, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages. Figure 20 Reference Example for Partial Display Figure 21 Partial Display (Partial Display Duty=16, initial COM0=0) Ver / /12/22

32 Figure 22 Moving Display (Partial Display Duty=16, Initial COM0=8) Ver / /12/22

33 INSTRUCTION TABLE INSTRUCTION A0 H independent instruction R/W COMMAND BYTE (WR) D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION Write data 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data to RAM Read data 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data to RAM Read status byte 0 1 PD 0 V D E MX MY DO Read status byte Function Set MX MY PD H1 H0 Mirror X, Mirror Y, Power Down, Extended table INSTRUCTION H[1:0]=[0:0] A0 R/W COMMAND BYTE (WR) D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION Set V0 (V OP) range PRS V0 (V OP) range L/H select END Release read/modify/write Read/modify/write RAM address at R:+0, W:+1 Display control D 0 E Sets display configuration SI3-8bit data (L)&start DA3 DA2 DA1 DA0 SI3-8bit data (M) DA7 DA6 DA5 DA4 SI3-8bit data (H) DA10 DA9 DA8 Set Y address Y3 Y2 Y1 Y0 Set X Address (L) X3 X2 X1 X0 Set X Address (H) X7 X6 X5 X4 H[1:0]=[0:1] Display configuration DO 0 V Set the number of data bytes, Low-bit (8 bit 3-line SPI) Set the number of data bytes, Middle-bit (8 bit 3-line SPI) Set the number of data bytes, High-bit (8 bit 3-line SPI) Set Y address of RAM 0 Y 9 Set X address of RAM, Low-bit. 0 X 131 Set X address of RAM, High-bit. 0 X 131 Top/bottom row mode set data order Bias system BS2 BS1 BS0 Sets bias system (BSx) Set V0 (V OP) V OP6 V OP5 V OP4 V OP3 V OP2 V OP1 V OP0 Write V0 (V OP) to register INSTRUCTION H[1:0]=[1:0] Set Partial screen mode A0 R/W COMMAND BYTE (WR) D7 D6 D5 D4 D3 D2 D1 D PS DESCRIPTION PS=1: Enable Partial screen mode. Partial Display WS Set partial screen size Set Partial Display part DP3 DP2 DP1 DP0 Set Start line S6 S5 S4 S3 S2 S1 S0 H[1:0]=[1:1] RESET Software reset Set display area for partial screen mode Specify the initial display line to realize vertical scrolling High Power Mode HP 0 0 High Power Mode SET Frame FR2 FR1 FR0 Frame rate control N line inversion NL4 NL3 NL2 NL1 NL0 Sets N line inversion Ver / /12/22

34 INSTRUCTION DESCRIPTION H[1:0] is independent. Write data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 0 0 Write data Read data 8-bit data of Display Data from the RAM location specified by the column address and page address can be read to the microprocessor. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 1 1 Read data Read status byte Indicates the internal status of the ST7588T A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 0 1 PD 0 V D E MX MY DO Flag PD V D,E MX MY PD=0:chip is active PD=1:chip is in power down mode Description When V = 0, the horizontal addressing is selected. When V = 1, the vertical addressing is selected. D E The bits D and E select the display mode. 0 0 Display OFF 0 1 All display segments on 1 0 Normal mode 1 1 Inverse video mode SEG bi-direction selection MY=0:normal direction (SEG0(SEG131) MY=1:reverse direction (SEG131(SEG0) COM bi-direction selection MY=0:normal direction (COM0(COM79) MY=1:reverse direction (COM79(COM0) DO=0:MSB is on top DO DO=1:LSB is on top Function Set A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D MX MY PD H1 H0 Flag MX MY PD Description SEG bi-direction selection MY=0:normal direction (SEG0 SEG131); MY=1:reverse direction (SEG131 SEG0) COM bi-direction selection MY=0:normal direction (COM0 COM79); MY=1:reverse direction (COM79 COM0) PD=0:chip is active; PD=1:chip is in power down mode All LCD outputs at VSS (display off), bias generator and V OUT generator off, V0 can be disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data can be written. H0, H1 Selection of Extended Command Table Ver / /12/22

35 H[1:0]=[0:0] Set V0 (V OP ) range V0 (V OP) range L/H select A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D PRS PRS=0: V0 (V OP) programming range LOW PRS=1: V0 (V OP) programming range HIGH END This command releases the read/modify/write mode, and returns the column and row address to the address it was at when the mode was entered. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D Read/modify/write This command is used coupled with the END command. Once this command has been input, the display data read command does not change the column and row address, but only the display data write command increments (+1) the address depend on V register setting. This mode is kept until the END command is input. When the END command is input, the address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. Ver / /12/22